SVD5867NLT4G

NVD5867NL Power MOSFET 60 V, 22 A, 39 mW, Single N−Channel Features • • • • • Low RDS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com RDS(on) V(BR)DSS ID 39 mW @ 10 V 60 V 22 A 50 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS "20 V ID 22 A Continuous Drain Current RqJC (Notes 1 & 3) Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2 & 3) Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current TC = 25°C Steady State TC = 100°C TC = 25°C Steady State PD W 43 21 ID TA = 100°C TA = 25°C A 6.0 4 PD W 3.3 1.7 TA = 25°C, tp = 10 ms IDM 85 A TA = 25°C IDmaxpkg 30 A TJ, Tstg −55 to 175 °C IS 36 A EAS 18 mJ TL 260 °C Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 19 A, L = 0.1 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter S N−CHANNEL MOSFET 4.0 TA = 100°C Current Limited by Package (Note 3) G 16 TC = 100°C TA = 25°C D Symbol Value Unit Junction−to−Case (Drain) (Note 1) RqJC 3.5 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 45 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 1 2 3 DPAK CASE 369AA STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain AYWW V58 67LG Parameter 2 1 Drain 3 Gate Source A = Assembly Location* Y = Year WW = Work Week V5867L = Device Code G = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 4 1 Publication Order Number: NVD5867NL/D NVD5867NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 60 VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 1.0 TJ = 125°C 100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.5 1.8 5.2 mV/°C mW VGS = 10 V, ID = 11 A 26 39 VGS = 4.5 V, ID = 11 A 33 50 VDS = 15 V, ID = 11 A 8.0 S 675 pF CHARGES, CAPACITANCES AND GATE RESISTANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VGS = 0 V, f = 1.0 MHz, VDS = 25 V 68 47 Total Gate Charge QG(TOT) 15 Threshold Gate Charge QG(TH) 1.0 Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge Gate Resistance VGS = 10 V, VDS = 48 V, ID = 22 A QGD QG(TOT) nC 2.2 4.3 VGS = 4.5 V, VDS = 48 V, ID = 22 A 7.6 nC RG 1.3 W td(on) 6.5 ns SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 10 V, VDD = 48 V, ID = 22 A, RG = 2.5 W tf 12.6 18.2 2.4 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.87 TJ = 125°C 0.78 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 10 A 17 VGS = 0 V, dIs/dt = 100 A/ms, IS = 22 A QRR 1.2 V ns 13 4.0 12 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVD5867NL TYPICAL PERFORMANCE CURVES 40 40 4.5 V ID, DRAIN CURRENT (AMPS) 35 4V 30 3.8 V 25 3.6 V 20 3.4 V 15 3.2 V 10 3.0 V 5 2.8 V 0 1 2 3 4 15 TJ = 125°C 10 TJ = 25°C 5 TJ = −55°C 2 3 4 5 Figure 2. Transfer Characteristics 0.040 0.030 5 4 6 7 9 8 10 0.040 TJ = 25°C 0.035 VGS = 4.5 V 0.030 VGS = 10 V 0.025 0.020 5 10 15 20 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.4 10000 VGS = 0 V ID = 22 A VGS = 10 V 2.0 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 20 Figure 1. On−Region Characteristics 0.050 2.2 25 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID = 22 A TJ = 25°C 3 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.060 0.020 VDS ≥ 10 V 35 0 5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C ID, DRAIN CURRENT (AMPS) 10V 1.8 1.6 1.4 1.2 1.0 TJ = 150°C 1000 100 TJ = 125°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 10 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage www.onsemi.com 3 60 NVD5867NL TYPICAL PERFORMANCE CURVES VGS = 0 V 900 C, CAPACITANCE (pF) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) 1000 TJ = 25°C 800 Ciss 700 600 500 400 300 200 Coss 100 0 0 Crss 10 20 30 40 50 60 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 10 QT 8 VGS 6 Qgs 4 2 VDS = 48 V ID = 22 A TJ = 25°C 0 0 5 15 Figure 8. Gate−To−Source Voltage vs. Total Charge 1000 20 100 tf IS, SOURCE CURRENT (AMPS) VDD = 48 V ID = 22 A VGS = 10 V t, TIME (ns) 10 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation td(off) tr 10 td(on) 1 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V TJ = 25°C 15 10 5 0 0.5 100 100 ms 1 ms 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 10 ms VGS = 10 V SINGLE PULSE TC = 25°C 0.8 0.9 1.0 Figure 10. Diode Forward Voltage vs. Current 100 10 0.7 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance I D, DRAIN CURRENT (AMPS) Qgd 20 ID = 19 A 15 10 5 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature www.onsemi.com 4 175 NVD5867NL TYPICAL PERFORMANCE CURVES RqJC(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 D = 0.5 1.0 0.2 0.1 0.05 0.02 0.1 0.01 SINGLE PULSE 0.01 0.000001 0.00001 0.0001 t, PULSE TIME (s) 0.001 0.01 0.1 Figure 13. Thermal Response ORDERING INFORMATION Package Shipping† NVD5867NLT4G DPAK (Pb−Free) 2500 / Tape & Reel SVD5867NLT4G DPAK (Pb−Free) 2500 / Tape & Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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