SVD5865NLT4G

NVD5865NL Power MOSFET 60 V, 46 A, 16 mW, Single N−Channel Features • • • • • Low RDS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC−Q101 Qualified These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com RDS(on) V(BR)DSS ID 16 mW @ 10 V 60 V 46 A 19 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS "20 V ID 46 A Continuous Drain Current RqJC (Notes 1 & 3) Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2 & 3) Power Dissipation RqJA (Notes 1 & 2) TC = 25°C Steady State TC = 100°C TC = 25°C Steady State PD W 71 36 ID TA = 100°C TA = 25°C 4 7.0 PD TA = 100°C W 3.1 203 A TA = 25°C IDmaxpkg 60 A TJ, Tstg −55 to 175 °C IS 46 A Single Pulse Drain−to−Source Avalanche Energy (L = 0.1 mH) EAS 36 mJ IAS 27 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Operating Junction and Storage Temperature Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter 1 2 3 1.5 IDM Current Limited by Package (Note 3) S N−CHANNEL MOSFET A 10 TA = 25°C, tp = 10 ms Pulsed Drain Current G 33 TC = 100°C TA = 25°C D Symbol Value Unit Junction−to−Case (Drain) (Note 1) RqJC 2.1 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 49 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. DPAK CASE 369AA STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain AYWW V58 65LG Parameter 2 1 Drain 3 Gate Source A = Assembly Location* Y = Year WW = Work Week V5865L = Device Code G = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2016 September, 2016 − Rev. 4 1 Publication Order Number: NVD5865NL/D NVD5865NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current 55 IDSS Gate−to−Source Leakage Current V VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 1.0 TJ = 125°C 100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.0 V ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ 1.0 5.6 mV/°C Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 19 A 13 16 mW Drain−to−Source on Resistance RDS(on) VGS = 4.5 V, ID = 19 A 16 19 mW gFS VDS = 15 V, ID = 19 A 15 S 1400 pF Forward Transconductance CHARGES, CAPACITANCES AND GATE RESISTANCES Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz, VDS = 25 V Output Capacitance Coss Reverse Transfer Capacitance Crss 95 Total Gate Charge QG(TOT) 29 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge Gate Resistance QG(TOT) VGS = 10 V, VDS = 48 V, ID = 38 A 137 nC 1.1 4 8 VGS = 4.5 V, VDS = 48 V, ID = 38 A 15 nC RG 1.3 W td(on) 8.4 ns SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 10 V, VDD = 48 V, ID = 38 A, RG = 2.5 W tf 12.4 26 4.4 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 38 A TJ = 25°C 0.95 TJ = 125°C 0.85 tRR ta tb 20 VGS = 0 V, dIs/dt = 100 A/ms, IS = 38 A QRR 1.2 V ns 13 7 13 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVD5865NL TYPICAL CHARACTERISTICS 80 3.8 V 3.6 V 50 3.4 V 40 3.2 V 30 20 3V 10 2.8 V 1 2 3 4 30 TJ = 25°C 20 5 TJ = 125°C 1 TJ = −55°C 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 38 A TJ = 25°C 0.025 0.020 0.015 0.010 3 4 5 6 7 8 9 10 0.018 TJ = 25°C VGS = 4.5 V 0.016 0.014 VGS = 10 V 0.012 0.010 5 10 15 20 25 30 35 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current 40 10000 2.2 2.0 40 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.030 2 50 0 ID = 38 A VGS = 10 V VGS = 0 V TJ = 150°C 1.8 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 60 10 2.6 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID, DRAIN CURRENT (A) 4.5 V 60 VDS ≥ 10 V 70 TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 70 80 4V VGS = 10 V 1.6 1.4 1.2 1.0 1000 TJ = 125°C 0.8 0.6 −50 100 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 60 NVD5865NL TYPICAL CHARACTERISTICS 10 VGS = 0 V TJ = 25°C 1600 Ciss C, CAPACITANCE (pF) 1400 VGS, GATE−TO−SOURCE VOLTAGE (V) 1800 1200 1000 800 600 400 Coss 200 Crss 0 0 10 20 30 40 50 60 8 6 4 Qgs Qgd 2 VDS = 48 V ID = 38 A TJ = 25°C 0 0 5 10 15 20 25 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge 1000 30 40 VDD = 48 V ID = 38 A VGS = 10 V IS, SOURCE CURRENT (A) td(off) tr 10 VGS = 0 V 35 100 td(on) tf 1 10 TJ = 25°C 30 25 20 15 10 5 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1 100 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 ID, DRAIN CURRENT (A) t, TIME (ns) QT 100 VGS = 10 V SINGLE PULSE TC = 25°C 100 ms 10 ms 10 ms 1 ms 10 dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 4 100 NVD5865NL TYPICAL CHARACTERISTICS RqJC(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 Duty Cycle = 0.5 1 0.2 0.1 0.05 0.1 0.02 0.01 SINGLE PULSE 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, PULSE TIME (s) Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† NVD5865NLT4G DPAK (Pb−Free) 2500 / Tape & Reel SVD5865NLT4G DPAK (Pb−Free) 2500 / Tape & Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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