TIP35A, TIP35B, TIP35C
(NPN); TIP36A, TIP36B,
TIP36C (PNP)
Complementary Silicon
High-Power Transistors
Designed for general−purpose power amplifier and switching
applications.
Features
• 25 A Collector Current
• Low Leakage Current −
ICEO = 1.0 mA @ 30 and 60 V
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25 AMPERE
COMPLEMENTARY SILICON
POWER TRANSISTORS
60−100 VOLTS, 125 WATTS
• Excellent DC Gain −
hFE = 40 Typ @ 15 A
• High Current Gain Bandwidth Product −
•
⎪hfe⎪ = 3.0 min @ IC
= 1.0 A, f = 1.0 MHz
These are Pb−Free Devices*
SOT−93 (TO−218)
CASE 340D
STYLE 1
MAXIMUM RATINGS
Rating
Symbol
TIP35A
TIP36A
TIP35B
TIP36B
TIP35C
TIP36C
Unit
Collector − Emitter Voltage
VCEO
60
80
100
Vdc
Collector − Base Voltage
VCB
60
80
100
Vdc
Emitter − Base Voltage
VEB
Collector Current
− Continuous
− Peak (Note 1)
IC
5.0
IB
5.0
Total Power Dissipation
@ TC = 25_C
Derate above 25_C
PD
125
TJ, Tstg
−65 to +150
Unclamped Inductive Load
ESB
Adc
25
40
Base Current − Continuous
Operating and Storage
Junction Temperature Range
Vdc
Adc
W
W/_C
_C
90
mJ
Symbol
Max
Unit
Thermal Resistance,
Junction−to−Case
RqJC
1.0
°C/W
Junction−To−Free−Air
Thermal Resistance
RqJA
35.7
°C/W
THERMAL CHARACTERISTICS
Characteristic
TO−247
CASE 340L
STYLE 3
NOTE: Effective June 2012 this device will
be available only in the TO−247
package. Reference FPCN# 16827.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle v 10%.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 6
1
Publication Order Number:
TIP35/D
TIP35A, TIP35B, TIP35C (NPN); TIP36A, TIP36B, TIP36C (PNP)
MARKING DIAGRAMS
TO−247
TO−218
TIP3xx
AYWWG
AYWWG
TIP3xx
1 BASE
3 EMITTER
1 BASE
2 COLLECTOR
TIP3xx
A
Y
WW
G
3 EMITTER
2 COLLECTOR
=
=
=
=
=
Device Code
Assembly Location
Year
Work Week
Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
TIP35AG
SOT−93 (TO−218)
(Pb−Free)
30 Units / Rail
TIP35BG
SOT−93 (TO−218)
(Pb−Free)
30 Units / Rail
TIP35CG
SOT−93 (TO−218)
(Pb−Free)
30 Units / Rail
TIP36AG
SOT−93 (TO−218)
(Pb−Free)
30 Units / Rail
TIP36BG
SOT−93 (TO−218)
(Pb−Free)
30 Units / Rail
TIP36CG
SOT−93 (TO−218)
(Pb−Free)
30 Units / Rail
TIP35AG
TO−247
(Pb−Free)
30 Units / Rail
TIP35BG
TO−247
(Pb−Free)
30 Units / Rail
TIP35CG
TO−247
(Pb−Free)
30 Units / Rail
TIP36AG
TO−247
(Pb−Free)
30 Units / Rail
TIP36BG
TO−247
(Pb−Free)
30 Units / Rail
TIP36CG
TO−247
(Pb−Free)
30 Units / Rail
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2
TIP35A, TIP35B, TIP35C (NPN); TIP36A, TIP36B, TIP36C (PNP)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Max
60
80
100
−
−
−
−
−
1.0
1.0
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 2)
(IC = 30 mA, IB = 0)
Collector−Emitter Cutoff Current
(VCE = 30 V, IB = 0)
(VCE = 60 V, IB = 0)
TIP35A, TIP36A
TIP35B, TIP36B
TIP35C, TIP36C
TIP35A, TIP36A
TIP35B, TIP35C, TIP36B, TIP36C
VCEO(sus)
Vdc
ICEO
mA
Collector−Emitter Cutoff Current
(VCE = Rated VCEO, VEB = 0)
ICES
−
0.7
mA
Emitter−Base Cutoff Current
(VEB = 5.0 V, IC = 0)
IEBO
−
1.0
mA
25
15
−
75
−
−
1.8
4.0
−
−
2.0
4.0
ON CHARACTERISTICS (Note 2)
DC Current Gain
(IC = 1.5 A, VCE = 4.0 V)
(IC = 15 A, VCE = 4.0 V)
hFE
Collector−Emitter Saturation Voltage
(IC = 15 A, IB = 1.5 A)
(IC = 25 A, IB = 5.0 A)
VCE(sat)
Base−Emitter On Voltage
(IC = 15 A, VCE = 4.0 V)
(IC = 25 A, VCE = 4.0 V)
VBE(on)
−
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Small−Signal Current Gain
(IC = 1.0 A, VCE = 10 V, f = 1.0 kHz)
hfe
25
−
−
Current−Gain — Bandwidth Product
(IC = 1.0 A, VCE = 10 V, f = 1.0 MHz)
fT
3.0
−
MHz
2. Pulse Test: Pulse Width = 300 ms, Duty Cycle v 2.0%.
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3
TIP35A, TIP35B, TIP35C (NPN); TIP36A, TIP36B, TIP36C (PNP)
PD, POWER DISSIPATION (WATTS)
125
100
75
50
25
0
0
25
50
75
125
100
TC, CASE TEMPERATURE (°C)
150
175
Figure 1. Power Derating
VCC
TURN−ON TIME
RL
+2.0 V
0
RB
VCC
TURN−OFF TIME
+9.0 V
RB
-11.0 V
10 TO 100 mS
DUTY CYCLE ≈ 2.0%
tr ≤ 20 ns
10 to 100 ms
DUTY CYCLE ≈ 2.0%
FOR CURVES OF FIGURES 3 & 4, RB & RL ARE VARIED.
INPUT LEVELS ARE APPROXIMATELY AS SHOWN.
FOR NPN, REVERSE ALL POLARITIES.
Figure 2. Switching Time Equivalent Test Circuits
2.0
TJ = 25°C
IC/IB = 10
VCC = 30 V
VBE(off) = 2 V
1.0
t, TIME (s)
μ
0.7
0.5
tr
0.2
0.1
(PNP)
(NPN)
td
0.07
0.05
0.03
0.02
0.3
0.5 0.7 1.0
5.0 7.0 10
2.0 3.0
IC, COLLECTOR CURRENT (AMPERES)
Figure 3. Turn−On Time
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4
20
30
VBB
-30 V
3.0
TO SCOPE
tr ≤ 20 ns
10
0
-11.0 V
0.3
RL
3.0
TO SCOPE
tr ≤ 20 ns
10
tr ≤
20 ns
-30 V
+4.0 V
TIP35A, TIP35B, TIP35C (NPN); TIP36A, TIP36B, TIP36C (PNP)
1000
(PNP)
(NPN)
3.0
ts
t, TIME (s)
μ
2.0
500
200
TJ = 25°C
VCC = 30 V
IC/IB = 10
IB1 = IB2
hFE , DC CURRENT GAIN
10
7.0
5.0
ts
1.0
0.7
0.5
tf
0.3
0.2
0.1
0.3 0.5 0.7
VCE = 4.0 V
TJ = 25°C
100
50
20
10
PNP
NPN
5.0
tf
2.0
1.0
1.0
2.0 3.0
5.0 7.0 10
IC, COLLECTOR CURRENT (AMPERES)
20
0.1
30
0.2
0.5 1.0
2.0
5.0 10
20
IC, COLLECTOR CURRENT (AMPS)
50
100
Figure 5. DC Current Gain
Figure 4. Turn−Off Time
FORWARD BIAS
100
IC, COLLECTOR CURRENT (AMPS)
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 6 is based on TC = 25_C; TJ(pk) is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when TC w 25_C. Second breakdown limitations do
not derate the same as thermal limitations.
For inductive loads, high voltage and high current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage−current conditions during
reverse biased turn−off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 7 gives RBSOA characteristics.
TC = 25°C
1.0ms
10
10ms
5.0
2.0
dc
SECONDARY BREAKDOWN
THERMAL LIMIT
BONDING WIRE LIMIT
1.0
0.5
0.3
0.2
0
REVERSE BIAS
300ms
50
30
20
TIP35A, 36A
TIP35B, 36B
TIP35C, 36C
1.0
20 30
50 70 100
2.0 3.0
5.0 7.0 10
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 6. Maximum Rated Forward Bias
Safe Operating Area
IC, COLLECTOR CURRENT (AMPS)
40
TJ ≤ 100°C
30
25
20
TIP35C
TIP36C
15
TIP35B
TIP36B
10
TIP35A
TIP36A
5.0
0
0
10
40
60
80
20
30
50
70
90
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Bias
Safe Operating Area
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5
100
TIP35A, TIP35B, TIP35C (NPN); TIP36A, TIP36B, TIP36C (PNP)
TEST CIRCUIT
VCE MONITOR
L1
(SEE NOTE A)
RBB1
MJE180
TUT
20
INPUT
L2
(SEE NOTE A)
50
RBB2 = 100
50
VCC = 10 V
+
IC MONITOR
VBB2 = 0
RS = 0.1 W
VBB1 = 10 V
+
VOLTAGE AND CURRENT WAVEFORMS
tw = 6.0 ms
(SEE NOTE B)
5.0 V
INPUT
VOLTAGE
0
100 ms
COLLECTOR
CURRENT
0
-3.0 A
0
-10 V
COLLECTOR
VOLTAGE
V(BR)CER
NOTES:
A. L1 and L2 are 10 mH, 0.11 W, Chicago Standard Transformer Corporation C−2688, or equivalent.
B. Input pulse width is increased until ICM = − 3.0 A.
C. For NPN, reverse all polarities.
Figure 8. Inductive Load Switching
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−93 (TO−218)
CASE 340D−02
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
SCALE 1:1
C
Q
B
U
S
E
DIM
A
B
C
D
E
G
H
J
K
L
Q
S
U
V
4
A
L
1
K
2
3
D
DATE 01/03/2002
J
H
MILLIMETERS
MIN
MAX
--20.35
14.70
15.20
4.70
4.90
1.10
1.30
1.17
1.37
5.40
5.55
2.00
3.00
0.50
0.78
31.00 REF
--16.20
4.00
4.10
17.80
18.20
4.00 REF
1.75 REF
INCHES
MIN
MAX
--0.801
0.579
0.598
0.185
0.193
0.043
0.051
0.046
0.054
0.213
0.219
0.079
0.118
0.020
0.031
1.220 REF
--0.638
0.158
0.161
0.701
0.717
0.157 REF
0.069
MARKING DIAGRAM
V
G
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
AYWW
xxxxx
ANODE
CATHODE
ANODE
CATHODE
A
Y
WW
xxxxx
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42643B
SOT−93
= Assembly Location
= Year
= Work Week
= Device Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247
CASE 340L
ISSUE G
DATE 06 OCT 2021
SCALE 1:1
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
STYLE 1:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE (S)
ANODE 2
CATHODES (S)
STYLE 5:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 6:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
DOCUMENT NUMBER:
DESCRIPTION:
STYLE 3:
PIN 1.
2.
3.
4.
98ASB15080C
TO−247
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 4:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
XXXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
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special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
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