PCS5I9350G-32-LT

November 2006 rev 0.3 3.3V 1:10 LVCMOS PLL Clock Generator Features • • • • • • • • • • • • • • Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ± 2.5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: Xtal or LVCMOS 150pS max output-output skew Phase-locked loop (PLL) bypass mode ‘SpreadTrak’ Output enable/disable Pin-compatible with MPC9350 and CY29350. Industrial temperature range: –40°C to +85°C 32-pin 1.0mm TQFP & LQFP Packages PCS5I9350 The PCS5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2. These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200MHz to 500MHz. This allows a wide range of output frequencies from 25MHz to 200MHz. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. low-voltage high-performance Functional Description The PCS5I9350 is a 200MHz PLL-based clock driver designed for high speed clock distribution applications. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 0.3 Block Diagram PCS5I9350 SELA PLL_EN REF_SEL TCLK XIN XOUT osc Phase Detector VCO 200-500MHz ÷2/ ÷4 QA LPF ÷16/ ÷32 FB_SEL SELB ÷4/ ÷8 QB QC0 QC1 QD0 QD1 QD2 QD3 QD4 ÷4/ ÷8 SELC ÷4/ ÷8 SELD OE# Pin Configuration REF_SEL PLL_EN VSS VDDQB TCLK VSS 24 23 22 QA QB 32 31 30 29 28 27 26 25 AVDD FB_SEL SELA SELB SELC SELD AVSS XOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 QC0 VDDQ C QC1 VSS QD0 VDDQD QD1 VSS PCS5I9350 21 20 19 18 17 XIN VDD VDDQD OE# QD3 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. QD4 QD2 VSS 2 of 12 November 2006 rev 0.3 Pin Discription1 Pin # 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 13, 17, 21, 25, 29 PCS5I9350 Pin Name XOUT XIN TCLK QA QB QC(1:0) QD(4:0) FB_SEL OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS VSS I/O O I I, PD O O O O I, PD I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Type Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground Description Oscillator Output. Connect to a crystal. Oscillator Input. Connect to a crystal. LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Clock output bank D Internal Feedback Select Input. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. Frequency select input, Bank (A:D). See Table 2. 2.5V or 3.3V Power supply for bank B output clock2,3 2.5V or 3.3V Power supply for bank C output clocks2,3 2.5V or 3.3V Power supply for bank D output clocks2,3 2.5V or 3.3V Power supply for PLL2,3 2.5V or 3.3V Power supply for core, inputs, and bank A output clock2,3 Analog ground Common ground Note: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin ( 100MHz 0.6V to 1.8V MHz % nS MHz 100 50 25 47.5 45 0.1 - DC tr, tf tsk(O) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tLOCK Output Duty Cycle Output Rise/Fall times Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter Maximum PLL Lock Time % nS pS nS nS MHz pS pS mS ÷16 Feedback ÷32 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies - Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 6 of 12 November 2006 rev 0.3 AC Electrical Specifications (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1 Parameter fVCO fin fXTAL frefDC tr, tf fMAX PCS5I9350 Description VCO Frequency Condition ÷16 Feedback Min 200 12.5 6.25 0 10 25 Typ 0.7 – 0.9 0.6 – 0.8 - Max 500 31.25 15.625 200 25 75 1.0 200 125 62.5 52.5 55 1.0 150 350 10 10 150 250 100 150 1 Unit MHz MHz MHz % nS MHz Input Frequency Crystal Oscillator Frequency Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency ÷32 Feedback Bypass mode (PLL_EN = 0) 0.8V to 2.0V ÷2 Output ÷4 Output ÷8 Output fMAX < 100MHz fMAX > 100MHz 0.8V to 2.4V Banks at same voltage Banks at different voltages 100 50 25 47.5 45 0.1 - DC tr, tf tsk(O) tsk(B) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tLOCK Output Duty Cycle Output Rise/Fall times Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (–3dB) Cycle-to-Cycle Jitter Period Jitter Maximum PLL Lock Time % nS pS pS nS nS MHz pS pS mS ÷16 Feedback ÷32 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies - Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 7 of 12 November 2006 rev 0.3 Zo = 50 ohm Pulse Generator Z = 50 ohm RT = 50 ohm RT = 50 ohm Zo = 50 ohm PCS5I9350 VTT VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V VDD LVCMOS_CLK VDD/2 tP GND DC = tP × 100% To T0 Figure 2. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(0) GND Figure 3. Output-to-Output Skew , tsk(O) Table 3. Suggested Oscillator Crystal Parameters Characteristic Frequency Tolerance Frequency Temperature Stability Aging Load Capacitance Effective Series Resistance Symbol TC TS TA CL RESR Conditions (TA–10 +60C) First three years @ 25°C Crystal’s rated load Min - Typ 20 40 Max ±100 ±00 5 80 Units ppm ppm ppm/yr pF Ω 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 8 of 12 November 2006 rev 0.3 Package Diagram 32-lead TQFP PCS5I9350 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max …. 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7° 0.03937 REF 1.00 REF 0.031 BASE 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 9 of 12 November 2006 rev 0.3 32-lead LQFP PCS5I9350 SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Inches Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° Millimeters Min Max … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 10 of 12 November 2006 rev 0.3 Ordering Information Part Number PCS5I9350G-32-ET PCS5I9350G-32-LT PCS5I9350 Marking PCS5I9350G PCS5I9350G Package Type 32-pin TQFP, Green 32-pin LQFP –Tape and Reel, Green Temperature Industrial Industrial Device Ordering Information PCS 5I9350 G-32-LT R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 11 of 12 November 2006 rev 0.3 PCS5I9350 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS5I9350 Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 12 of 12