FM3316

Pre-Production FM33256/FM3316 3V Integrated Processor Companion with Memory Features High Integration Device Replaces Multiple Parts • Serial Nonvolatile Memory • Real-time Clock (RTC) with Alarm • Low VDD Detection Drives Reset • Watchdog Window Timer • Early Power-Fail Warning/NMI • 16-bit Nonvolatile Event Counter • Serial Number with Write-lock for Security Ferroelectric Nonvolatile RAM • 256Kb and 16Kb versions • Unlimited Read/Write Endurance • 45 year Data Retention • NoDelay™ Writes Real-time Clock/Calendar • Backup Current under 1 µA • Seconds through Centuries in BCD format • Tracks Leap Years through 2099 • Uses Standard 32.768 kHz Crystal • Software Calibration • Supports Battery or Capacitor Backup Processor Companion • Active-low Reset Output for VDD and Watchdog • Programmable Low-VDD Reset Thresholds • Manual Reset Filtered and Debounced • Programmable Watchdog Window Timer • Nonvolatile Event Counter Tracks System Intrusions or other Events • Comparator for Power-Fail Interrupt or Other Use • 64-bit Programmable Serial Number with Lock Fast SPI Interface • Up to 16 MHz Maximum Bus Frequency • RTC, Supervisor Controlled via SPI Interface • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Easy to Use Configurations • Operates from 2.7 to 3.6V • Small Footprint “Green” 14-pin SOIC (-G) • Low Operating Current, 50µA Standby Current • -40°C to +85°C Operation • Underwriters Laboratory (UL) Recognized Description The FM33256 and FM3316 are devices that integrate F-RAM memory with the most commonly needed functions for processor-based systems. Major features include nonvolatile memory, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for a power-fail (NMI) interrupt or other purpose. The devices operate from 2.7 to 3.6V. Each FM33xx provides nonvolatile RAM available in memory capacity of 16Kb and 256Kb. Fast write speed and unlimited endurance allow the memory to serve as extra RAM or conventional nonvolatile storage. This memory is truly nonvolatile rather than battery backed. The real-time clock (RTC) provides time and date information in BCD format. It can be permanently powered from external backup voltage source, either a battery or a capacitor. The timekeeper uses a common external 32.768 kHz crystal and provides a calibration mode that allows software adjustment of timekeeping accuracy. The processor companion includes commonly needed CPU support functions. Supervisory functions include a reset output signal controlled by either a low VDD condition or a watchdog timeout. /RST goes active when VDD drops below a programmable threshold and remains active for 100 ms (max.) after VDD rises above the trip point. A programmable watchdog timer runs from 60 ms to 1.8 seconds. The timer may also be programmed for a delayed start, which functions as a window timer. The watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host within the time window. A flag-bit indicates the source of the reset. A comparator on PFI compares an external input pin to the onboard 1.5V reference. This is useful for generating a power-fail interrupt (NMI) but can be used for any purpose. The family also includes a programmable 64-bit serial number that can be locked making it unalterable. Additionally it offers an event counter that tracks the number of rising or falling edges detected on a dedicated input pin. The counter can be programmed to be non-volatile under VDD power or battery-backed using only VBAK. If VBAK is connected to a battery or capacitor, then events will be counted even in the absence of VDD. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 28 This is a product in the pre-production phase of development. Device characterization is complete and Ramtron does not expect to change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made. Rev. 2.0 Feb. 2009 FM33256/FM3316 SPI Companion w/ FRAM Pin Configuration CS SO CNT VBAK X2 X1 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD ACS SCK SI PFO RST PFI Pin Name /CS SCK SI SO PFI PFO CNT ACS /RST X1, X2 VDD VBAK VSS Function Chip Select Serial Clock Serial Data Input Serial Data Output Power Fail Input Power Fail Output (NMI) Event Counter Input Alarm/Calibration/SqWave Reset Input/Output Crystal Connections Supply Voltage Battery-Backup Supply Ground Pin Descriptions Pin Name /CS Type Input Pin Description Chip Select: This active low input activates the device. When high, the device enters lowpower standby mode, ignores the SCK and SI inputs, and the SO output is tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 16 MHz and may be interrupted at any time. Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. The SI pin may be connected to SO for a single pin data interface. Serial Output: This is the data output pin. It is driven during a read and remains tri-stated at all other times. Data transitions are driven on the falling edge of the serial clock. The SO pin may be connected to SI for a single pin data interface. Event Counter Input: This input increments the counter when an edge is detected on this pin. The polarity is programmable and the counter value is nonvolatile or battery-backed, depending on the mode. This pin should be tied to ground if unused. Alarm/Calibration/SquareWave: This is an open-drain output that requires an external pullup resistor. In normal operation, this pin acts as the active-low alarm output. In Calibration mode, a 512 Hz square-wave is driven out. In SquareWave mode, the user may select a frequency of 1, 512, 4096, or 32768 Hz to be used as a continuous output. The SquareWave mode is entered by clearing the AL/SW and CAL bits in register 18h. 32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1 and a DC mid-level to X2 (see Crystal Type section for suggestions). Reset: This active-low output is open drain with weak pull-up. It is also an input when used as a manual reset. This pin should be left floating if unused. Early Power-fail Input: Typically connected to an unregulated power supply to detect an early power failure. This pin must be tied to ground if unused. Early Power-fail Output: This pin is the early power-fail output and is typically used to drive a microcontroller NMI pin. PFO drives low when the PFI voltage is VSW) 0.8 VIH Input High Voltage 0.7 VDD VDD + 0.3 All inputs except as listed below VBAK – 0.5 CNT battery-backed (VDD < VSW) VBAK + 0.3 CNT VDD > VSW 0.7 VDD VDD + 0.3 PFI VDD + 0.3 Continued Units V mA mA µA V µA µA µA µA µA V V V V V V V µA µA V V V V V V V >> Notes 1 2 3 4 5 6 7 8 9 9 9 9 10 11 11 12 Rev. 2.0 Feb. 2009 Page 23 of 28 FM33256/FM3316 SPI Companion w/ FRAM DC Operating Conditions, continued (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units VOL Output Low Voltage @ IOL = 3 mA 0.4 V VOH Output High Voltage (SO, PFO) @ IOH = -2 mA VDD – 0.8 V RRST Pull-up resistance for /RST inactive 50 400 KΩ VPFI Power Fail Input Reference Voltage 1.475 1.50 1.525 V VHYS Power Fail Input (PFI) Hysteresis (Rising) 100 mV Notes Notes 1. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified. 2. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 3. All inputs at VSS or VDD, static. Trickle charger off (VBC=0). 4. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 5. VBAK = 3.0V, VDD < VSW, oscillator running, CNT at VBAK. 6. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max. 7. This is the VDD supply current contributed by enabling the trickle charger circuit, and does not account for IBAKTC. 8. This is the VDD supply current contributed by enabling the watchdog circuit, WDE=1 and WDET set to a non-zero value. 9. /RST is asserted active when VDD < VTP . 10. The minimum VDD to guarantee the level of /RST remains a valid VOL level. 11. VIN or VOUT = VSS to VDD. Does not apply to PFI, X1, or X2. 12. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM33xx. AC Parameters (TA = -40°C to + 85°C, VDD = 2.7V to 3.6V CL = 30 pF) Symbol Parameter Min fCK SCK Clock Frequency 0 tCH Clock High Time 28 tCL Clock Low Time 28 tCSU Chip Select Setup 10 tCSH Chip Select Hold 10 tOD Output Disable Time tODV Output Data Valid Time tOH Output Hold Time 0 tD Deselect Time 90 tR Data In Rise Time tF Data In Fall Time tSU Data Setup Time 6 tH Data Hold Time 6 Notes 1. tCH + tCL = 1/fCK. 2. This parameter is characterized but not 100% tested. 3. Rise and fall times measured between 10% and 90% of waveform. Max 16 20 24 50 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 2 1,3 1,3 Supervisor Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V) Symbol Parameter tRPW /RST Pulse Width (active low time) tRNR /RST Response Time to VDD VTP, and tRPU satisfied. The StartTime has a resolution of 25ms. The EndTime has a resolution of 60ms. The /RST pin will drive low for this amount of time after the internal reset circuit is activated due to a watchdog, low voltage, or manual reset event. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V) Symbol Parameter CIO Input/Output Capacitance CXTL X1, X2 Crystal pin Capacitance CCNT Max. Allowable Capacitance on CNT (polled mode) Notes 1 This parameter is characterized but not tested. The crystal attached to the X1/X2 pins must be rated as 12.5pF. 2 Typ 25 - Max 8 100 Units pF pF pF Notes 1 1, 2 Data Retention (VDD = 2.7V to 3.6V) Symbol Parameter TDR Data Retention @ +75°C @ +80°C @ +85°C Min 45 20 10 Units Years Years Years Notes AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output (SO) Load Capacitance Diagram Notes 10% and 90% of VDD 5 ns 0.5 VDD 30 pF All timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to op-code, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Serial Data Bus Timing tD CS tCSU SCK tSU SI tODV SO tOH tOD tH 1/tCK tF tR tCL t CH tCSH Rev. 2.0 Feb. 2009 Page 25 of 28 FM33256/FM3316 SPI Companion w/ FRAM /RST Timing V DD VTP VRST tRNR tRPU t VF t VR RST Rev. 2.0 Feb. 2009 Page 26 of 28 FM33256/FM3316 SPI Companion w/ FRAM Mechanical Drawing 14-pin SOIC (JEDEC Standard MS-012 variation AB) All dimensions in millimeters. Conversions to inches are not exact. SOIC Package Marking Scheme Legend: XXXX= part number, P= package type (-G) LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM33256, “Green” SOIC package, Year 2006, Work Week 14 FM33256-G1 A70012G RIC 0714 XXXXXXX-P LLLLLLL RIC YYWW Rev. 2.0 Feb. 2009 Page 27 of 28 FM33256/FM3316 SPI Companion w/ FRAM Revision History Revision 1.0 1.1 Date 12/18/2006 12/12/2007 Summary Initial release. Changed IQWD and IBAKTC spec limits. Added text that Event Counter does not roll over. Added suggestion to clear VBC bit when Vbak is not used. Added ESD and package MSL ratings. Changed status to Pre-Production. Added tape and reel ordering information. Expanded data retention ratings. Added UL Recognition of trickle charger. 2.0 2/9/2009 Rev. 2.0 Feb. 2009 Page 28 of 28