4524

REJ09B0107-0200Z 4 4524 Group User's Manual RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 2.00 Revision date: Aug 06, 2004 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. 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Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. REVISION HISTORY Rev. Date Page 1.00 Dec 19, 2003 – First edition issued 2.00 Aug 06, 2004 All pages 1-5 1-6 1-35 1-45 1-46 1-47 1-61 1-65 1-69 4524 Group User’s Manual Description Summary 1-78 2-57 2-74 2-77 3-47 Words standardized: On-chip oscillator, A/D converter Power dissipation revised. ____________ Description of RESET pin revised. Fig.26 : Note 9 added. Some description revised. Fig.31: “DI” instruction added. Table 11:Revised. (5) LCD power supply circuit revised. Fig.51: State of quartz-crystal oscillator added. Fig.55: • Note 5 added, • “T5F” added to the transitions between from state E to states B, A, C and D • “Key-on wakeup”→“Wakeup” Note on Power source Voltage added. Table 2.5.1 : Notes 4 revised. Fig.2.7.4: State of quartz-crystal oscillator added. Fig.2.9.1: • Note 5 added, • “T5F” added to the transitions between from state E to states B, A, C and D • “Key-on wakeup”→“Wakeup” Note on Power source Voltage added. BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization q C HAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q C HAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q C HAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. As for the Mask ROM confirmation form, the ROM programming confirmation form, and the Mark specification form which are to be submitted when ordering, refer to the “Renesas Technology Corp.” Hompage (http:/ /www.renesas.com/en/rom). As for the Development tools and related documents, refer to the Product Info - 4524 Group (http:// www.renesas.com/eng/products/mpumcu/specific/lcd_mcu/expand/e4524.htm) of “Renesas Technology Corp.” Homepage. 4524 Group Table of contents Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................... 2 FEATURES ......................................................................................................................................... 2 APPLICATION ................................................................................................................................... 2 PIN CONFIGURATION ..................................................................................................................... 3 BLOCK DIAGRAM ............................................................................................................................ 4 PERFORMANCE OVERVIEW .......................................................................................................... 5 PIN DESCRIPTION ........................................................................................................................... 6 MULTIFUNCTION ........................................................................................................................ 7 DEFINITION OF CLOCK AND CYCLE .................................................................................... 7 PORT FUNCTION ....................................................................................................................... 8 CONNECTIONS OF UNUSED PINS ........................................................................................ 9 PORT BLOCK DIAGRAMS ...................................................................................................... 10 FUNCTION BLOCK OPERATIONS .............................................................................................. 18 CPU ............................................................................................................................................. 18 PROGRAM MEMORY (ROM) .................................................................................................. 21 DATA MEMORY (RAM) ............................................................................................................ 22 INTERRUPT FUNCTION .......................................................................................................... 23 EXTERNAL INTERRUPTS ....................................................................................................... 27 TIMERS ...................................................................................................................................... 32 WATCHDOG TIMER ................................................................................................................. 45 A/D CONVERTER (COMPARATOR) ...................................................................................... 47 SERIAL I/O ................................................................................................................................. 53 LCD FUNCTION ........................................................................................................................ 57 RESET FUNCTION ................................................................................................................... 62 VOLTAGE DROP DETECTION CIRCUIT .............................................................................. 66 POWER DOWN FUNCTION .................................................................................................... 67 CLOCK CONTROL .................................................................................................................... 72 ROM ORDERING METHOD .......................................................................................................... 74 LIST OF PRECAUTIONS ............................................................................................................... 75 CONTROL REGISTERS ................................................................................................................. 79 INSTRUCTIONS ............................................................................................................................... 86 SYMBOL ..................................................................................................................................... 86 INDEX LIST OF INSTRUCTION FUNCTION ........................................................................ 87 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) .......................................................... 92 MACHINE INSTRUCTIONS (INDEX BY TYPES) (CONTINUED) ..................................... 132 INSTRUCTION CODE TABLE ............................................................................................... 148 BUILT-IN PROM VERSION ......................................................................................................... 150 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z i 4524 Group Table of contents CHAPTER 2 APPLICATION 2.1 I/O pins ....................................................................................................................................... 2 2.1.1 I/O ports ............................................................................................................................. 2 2.1.2 Related registers ............................................................................................................... 5 2.1.3 Port application examples .............................................................................................. 13 2.1.4 Notes on use ................................................................................................................... 14 2.2 Interrupts .................................................................................................................................. 16 2.2.1 Interrupt functions ........................................................................................................... 16 2.2.2 Related registers ............................................................................................................. 19 2.2.3 Interrupt application examples ....................................................................................... 22 2.2.4 Notes on use ................................................................................................................... 32 2.3 Timers ....................................................................................................................................... 33 2.3.1 Timer functions ................................................................................................................ 33 2.3.2 Related registers ............................................................................................................. 34 2.3.3 Timer application examples ........................................................................................... 39 2.3.4 Notes on use ................................................................................................................... 49 2.4 A/D converter .......................................................................................................................... 50 2.4.1 Related registers ............................................................................................................. 51 2.4.2 A/D converter application examples ............................................................................. 52 2.4.3 Notes on use ................................................................................................................... 54 2.5 Serial I/O ................................................................................................................................... 56 2.5.1 Carrier functions .............................................................................................................. 56 2.5.2 Related registers ............................................................................................................. 57 2.5.3 Operation description ...................................................................................................... 59 2.5.4 Serial I/O application example ...................................................................................... 62 2.5.5 Notes on use ................................................................................................................... 65 2.6 LCD function ............................................................................................................................ 66 2.6.1 Operation description ...................................................................................................... 66 2.6.2 Related registers ............................................................................................................. 67 2.6.3 LCD application examples ............................................................................................. 69 2.6.4 Notes on use ................................................................................................................... 71 2.7 Reset .......................................................................................................................................... 72 2.7.1 Reset circuit ..................................................................................................................... 72 2.7.2 Internal state at reset ..................................................................................................... 73 2.7.3 Notes on use ................................................................................................................... 74 2.8 Voltage drop detection circuit ............................................................................................. 75 2.8.1 Note on use ..................................................................................................................... 76 2.9 Power down ............................................................................................................................. 77 2.9.1 Power down mode .......................................................................................................... 78 2.9.2 Related registers ............................................................................................................. 81 2.9.3 Power down function application example .................................................................. 85 2.9.4 Notes on use ................................................................................................................... 86 2.10 Oscillation circuit ................................................................................................................. 87 2.10.1 Oscillation circuit ........................................................................................................... 87 2.10.2 Oscillation operation ..................................................................................................... 89 2.10.3 Related register ............................................................................................................. 90 2.10.4 Notes on use ................................................................................................................. 90 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z ii 4524 Group Table of contents CHAPTER 3 APPENDIX 3.1 Electrical characteristics ........................................................................................................ 2 3.1.1 Absolute maximum ratings ............................................................................................... 2 3.1.2 Recommended operating conditions ............................................................................... 3 3.1.3 Electrical characteristics ................................................................................................... 5 3.1.4 A/D converter recommended operating conditions ....................................................... 7 3.1.5 Voltage drop detection circuit characteristics ................................................................ 8 3.1.6 Basic timing diagram ........................................................................................................ 8 3.2 Typical characteristics ............................................................................................................ 9 3.2.1 V DD–IDD characteristics ...................................................................................................... 9 3.2.2 Frequency characteristics ............................................................................................... 15 3.2.3 Port typical characteristics (V DD = 5 .0 V) .................................................................... 18 3.2.4 Port typical characteristics (V DD = 3 .0 V) .................................................................... 21 3.2.5 Input threshold characteristics ....................................................................................... 24 3.2.6 Pull-up resistor: VDD–RPU characteristics example .................................................... 27 3.2.7 Internal resistor for LCD power: Ta–RVLC ................................................................. 28 3.2.8 A/D converter typical characteristics ............................................................................ 29 3.2.9 Analog input current characteristics example ............................................................. 32 3.2.10 A/D converter operation current (V DD–I ADD) characteristics ...................................... 36 3.2.11 Voltage drop detection circuit characteristics ........................................................... 36 3.3 List of precautions ................................................................................................................. 38 3.3.1 Program counter .............................................................................................................. 38 3.3.2 Stack registers (SKs) ...................................................................................................... 38 3.3.3 Notes on I/O port ............................................................................................................ 38 3.3.4 Notes on interrupt ........................................................................................................... 41 3.3.5 Notes on timer ................................................................................................................. 42 3.3.6 Notes on A/D conversion ............................................................................................... 43 3.3.7 Notes on serial I/O ......................................................................................................... 44 3.3.8 Notes on LCD function ................................................................................................... 45 3.3.9 Notes on reset ................................................................................................................. 45 3.3.10 Notes on voltage drop detection circuit ..................................................................... 45 3.3.11 Notes on power down .................................................................................................. 46 3.3.12 Notes on oscillation circuit ........................................................................................... 47 3.3.13 Electric characteristic differences between Mask ROM and One Time PROM version MCU ... 47 3.3.14 Notes on Power Source Voltage ................................................................................ 47 3.4 Notes on noise ........................................................................................................................ 48 3.4.1 Shortest wiring length ..................................................................................................... 48 3.4.2 Connection of bypass capacitor across V SS l ine and V DD l ine .................................. 50 3.4.3 wiring to analog input pins ............................................................................................ 51 3.4.4 Oscillator concerns .......................................................................................................... 51 3.4.5 setup for I/O ports .......................................................................................................... 52 3.4.6 providing of watchdog timer function by software ...................................................... 52 3.5 Package outline ...................................................................................................................... 54 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z iii 4524 Group List of figures List of figures CHAPTER 1 HARDWARE Pin configuration (top view) (4524 Group) .................................................................................... 3 Block diagram (4524 Group) ........................................................................................................... 4 Port block diagram (1) .................................................................................................................... 10 Port block diagram (2) .................................................................................................................... 11 Port block diagram (3) .................................................................................................................... 12 Port block diagram (4) .................................................................................................................... 13 Port block diagram (5) .................................................................................................................... 14 Port block diagram (6) .................................................................................................................... 15 Port block diagram (7) .................................................................................................................... 16 Port block diagram (8) .................................................................................................................... 17 Fig. 1 AMC instruction execution example .................................................................................. 18 Fig. 2 RAR instruction execution example .................................................................................. 18 Fig. 3 Registers A, B and register E ........................................................................................... 18 Fig. 4 TABP p instruction execution example ............................................................................. 18 Fig. 5 Stack registers (SKs) structure .......................................................................................... 19 Fig. 6 Example of operation at subroutine call .......................................................................... 19 Fig. 7 Program counter (PC) structure ........................................................................................ 20 Fig. 8 Data pointer (DP) structure ................................................................................................ 20 Fig. 9 SD instruction execution example ..................................................................................... 20 Fig. 10 ROM map of M34524ED .................................................................................................. 21 Fig. 11 Page 1 (addresses 008016 t o 00FF 16) structure ............................................................ 21 Fig. 12 RAM map ............................................................................................................................ 22 Fig. 13 Program example of interrupt processing ...................................................................... 24 Fig. 14 Internal state when interrupt occurs ............................................................................... 24 Fig. 15 Interrupt system diagram .................................................................................................. 24 Fig. 16 Interrupt sequence ............................................................................................................. 26 Fig. 17 External interrupt circuit structure ................................................................................... 27 Fig. 18 External 0 interrupt program example-1 ......................................................................... 30 Fig. 19 External 0 interrupt program example-2 ......................................................................... 30 Fig. 20 External 0 interrupt program example-3 ......................................................................... 30 Fig. 21 External 1 interrupt program example-1 ......................................................................... 31 Fig. 22 External 1 interrupt program example-2 ......................................................................... 31 Fig. 23 External 1 interrupt program example-3 ......................................................................... 31 Fig. 24 Auto-reload function .......................................................................................................... 32 Fig. 25 Timer structure (1) ............................................................................................................ 34 Fig. 26 Timer structure (2) ............................................................................................................ 35 Fig. 27 Timer 4 operation (reload register R4L: “03 16”, R4H: “0216”) ...................................... 42 Fig. 28 CNTR1 output auto-control function by timer 3 ............................................................ 43 Fig. 29 Timer 4 count start/stop timing ....................................................................................... 44 Fig. 30 Watchdog timer function ................................................................................................... 45 Fig. 31 Program example to start/stop watchdog timer ............................................................ 46 Fig. 32 Program example to enter the mode when using the watchdog timer ..................... 46 Fig. 33 A/D conversion circuit structure ...................................................................................... 47 Fig. 34 A/D conversion timing chart ............................................................................................. 50 Fig. 35 Setting registers ................................................................................................................. 50 Fig. 36 Comparator operation timing chart .................................................................................. 51 Fig. 37 Definition of A/D conversion accuracy ........................................................................... 52 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z iv 4524 Group List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 69 70 71 72 73 74 75 76 77 Serial I/O structure ............................................................................................................ 53 Serial I/O register state when transfer ........................................................................... 54 Serial I/O connection example ......................................................................................... 55 Timing of serial I/O data transfer .................................................................................... 55 LCD clock control circuit structure .................................................................................. 57 LCD controller/driver ......................................................................................................... 58 LCD RAM map ................................................................................................................... 59 LCD controller/driver structure ......................................................................................... 60 LCD power source circuit example (1/3 bias condition selected) .............................. 61 Reset release timing ......................................................................................................... 62 RESET pin input waveform and reset operation .......................................................... 62 Structure of reset pin and its peripherals, and power-on reset operation ................ 63 Internal state at reset ....................................................................................................... 64 Internal state at reset ....................................................................................................... 65 Voltage drop detection reset circuit ................................................................................ 66 Voltage drop detection circuit operation waveform ....................................................... 66 VDD a nd VRST ............................................................................................................................................................................................................... 66 State transition ................................................................................................................... 69 Set source and clear source of the P flag .................................................................... 69 Start condition identified example using the SNZP instruction ................................... 69 Clock control circuit structure .......................................................................................... 72 Switch to ceramic oscillation/RC oscillation ................................................................... 73 Handling of X IN a nd X OUT w hen operating on-chip oscillator ....................................... 73 Ceramic resonator external circuit .................................................................................. 73 External RC oscillation circuit .......................................................................................... 73 External clock input circuit ............................................................................................... 74 External quartz-crystal circuit ........................................................................................... 74 External 0 interrupt program example-1 ......................................................................... 76 External 0 interrupt program example-2 ......................................................................... 76 External 0 interrupt program example-3 ......................................................................... 76 External 1 interrupt program example-2 ......................................................................... 77 External 1 interrupt program example-3 ......................................................................... 77 A/D converter program example-3 .................................................................................. 77 Analog input external circuit example-1 ......................................................................... 78 Analog input external circuit example-2 ......................................................................... 78 VDD a nd VRST ............................................................................................................................................................................................................... 78 Pin configuration of built-in PROM version ................................................................. 150 PROM memory map ........................................................................................................ 151 Flow of writing and test of the product shipped in blank .......................................... 151 CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 2.1.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 Key input by key scan .................................................................................................. 13 Key scan input timing ................................................................................................... 13 External 0 interrupt operation example ...................................................................... 23 External 0 interrupt setting example .......................................................................... 24 External 1 interrupt operation example ...................................................................... 25 External 1 interrupt setting example .......................................................................... 26 Timer 1 constant period interrupt setting example ................................................... 27 Timer 2 constant period interrupt setting example ................................................... 28 Timer 3 constant period interrupt setting example ................................................... 29 Timer 4 constant period interrupt setting example ................................................... 30 Timer 5 constant period interrupt setting example ................................................... 31 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z v 4524 Group List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.1 Peripheral circuit example ............................................................................................ 39 2.3.2 Timer 4 operation .......................................................................................................... 40 2.3.3 Watchdog timer function ............................................................................................... 41 2.3.4 Constant period measurement setting example ........................................................ 42 2.3.5 CNTR 0 o utput setting example .................................................................................... 43 2.3.6 CNTR 0 i nput setting example ...................................................................................... 44 2.3.7 Timer start by external input setting example .......................................................... 45 2.3.8 PWM output control setting example ......................................................................... 46 2.3.9 Constant period counter by timer 5 setting example ............................................... 47 2.3.10 Watchdog timer setting example ............................................................................... 48 2.4.1 A/D converter structure ................................................................................................ 50 2.4.2 A/D conversion mode setting example ....................................................................... 53 2.4.3 Analog input external circuit example-1 ..................................................................... 54 2.4.4 Analog input external circuit example-2 ..................................................................... 54 2.4.5 A/D converter operating mode program example ..................................................... 54 2.5.1 Serial I/O block diagram .............................................................................................. 56 2.5.2 Serial I/O connection example .................................................................................... 59 2.5.3 Serial I/O register state when transfer ....................................................................... 59 2.5.4 Serial I/O transfer timing .............................................................................................. 60 2.5.5 Setting example when a serial I/O of master side is not used ............................. 63 2.5.6 Setting example when a serial I/O interrupt of slave side is used ....................... 64 2.6.1 LCD clock control circuit structure .............................................................................. 66 2.6.2 LCD RAM map .............................................................................................................. 67 2.6.3 LCD display panel example ......................................................................................... 69 2.6.4 Segment assignment example ..................................................................................... 69 2.6.5 LCD RAM assignment example .................................................................................. 69 2.6.6 Initial setting example ................................................................................................... 70 2.7.1 Structure of reset pin and its peripherals,, and power-on reset operation ........... 72 2.7.2 Oscillation stabilizing time after system is released from reset ............................. 72 2.7.3 Internal state at reset ................................................................................................... 73 2.7.4 Internal state at reset ................................................................................................... 74 2.8.1 Voltage drop detection circuit ...................................................................................... 75 2.8.2 Voltage drop detection circuit operation waveform example .................................. 75 2.8.3 V DD a nd V RST ....................................................................................................................................................................................................... 76 2.9.1 State transition ............................................................................................................... 77 2.9.2 Start condition identified example ............................................................................... 80 2.9.3 Software setting example ............................................................................................. 85 2.10.1 Switch to ceramic oscillation/RC oscillation ............................................................ 87 2.10.2 Handling of X IN a nd X OUT w hen operating on-chip oscillator ................................. 87 2.10.3 Ceramic resonator external circuit ............................................................................ 88 2.10.4 External RC oscillation circuit ................................................................................... 88 2.10.5 External clock input circuit ......................................................................................... 88 2.10.6 External quartz-crystal circuit .................................................................................... 88 2.10.7 Structure of clock control circuit ............................................................................... 89 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z vi 4524 Group List of figures CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.2.1 A/D conversion characteristics data ........................................................................... 29 3.3.1 Analog input external circuit example-1 ..................................................................... 43 3.3.2 Analog input external circuit example-2 ..................................................................... 43 3.3.3 A/D converter operating mode program example ..................................................... 43 3.3.4 V DD a nd V RST ....................................................................................................................................................................................................... 45 3.4.1 Selection of packages .................................................................................................. 48 3.4.2 Wiring for the RESET input pin .................................................................................. 48 3.4.3 Wiring for clock I/O pins .............................................................................................. 49 3.4.4 Wiring for CNV SS p in ..................................................................................................... 49 3.4.5 Wiring for the V PP p in of the built-in PROM version ................................................ 50 3.4.6 Bypass capacitor across the V SS l ine and the V DD l ine ........................................... 50 3.4.7 Analog signal line and a resistor and a capacitor ................................................... 51 3.4.8 Wiring for a large current signal line ......................................................................... 51 3.4.9 Wiring to a signal line where potential levels change frequently .......................... 52 3.4.10 V SS p attern on the underside of an oscillator ......................................................... 52 3.4.11 Watchdog timer by software ...................................................................................... 53 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z vii 4524 Group List of tables List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock ..................................................................................................... 7 1 ROM size and pages ....................................................................................................... 21 2 RAM size ........................................................................................................................... 22 3 Interrupt sources ............................................................................................................... 23 4 Interrupt request flag, interrupt enable bit and skip instruction ................................. 23 5 Interrupt enable bit function ............................................................................................ 23 6 Interrupt control registers ................................................................................................ 25 7 External interrupt activated conditions ........................................................................... 27 8 External interrupt control register ................................................................................... 29 9 Function related timers .................................................................................................... 33 10 Timer related registers ................................................................................................... 36 11 A/D converter characteristics ........................................................................................ 47 12 A/D control registers ...................................................................................................... 48 13 Change of successive comparison register AD during A/D conversion ................. 49 14 Serial I/O pins ................................................................................................................. 53 15 Serial I/O control register .............................................................................................. 53 16 Processing sequence of data transfer from master to slave ................................... 56 17 Duty and maximum number of displayed pixels ........................................................ 57 18 LCD control registers ..................................................................................................... 59 19 Port state at reset .......................................................................................................... 63 20 Voltage drop detection circuit operation state ............................................................ 66 21 Functions and states retained at power down ........................................................... 67 22 Return source and return condition ............................................................................. 68 23 Key-on wakeup control register, pull-up control register and interrupt control register ...... 70 24 Clock control register MR ............................................................................................. 74 25 Product of built-in PROM version .............................................................................. 150 CHAPTER 2 APPLICATION Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 Timer control register W3 ........................................................................................... 5 2.1.2 Timer control register W4 ........................................................................................... 5 2.1.3 Timer control register W6 ........................................................................................... 6 2.1.4 Serial I/O control register J1 ...................................................................................... 6 2.1.5 A/D control register Q2 ............................................................................................... 7 2.1.6 A/D control register Q3 ............................................................................................... 7 2.1.7 Pull-up control register PU0 ....................................................................................... 8 2.1.8 Pull-up control register PU1 ....................................................................................... 8 2.1.9 Port output structure control register FR0 ................................................................ 9 2.1.10 Port output structure control register FR1 .............................................................. 9 2.1.11 Port output structure control register FR2 ............................................................ 10 2.1.12 Port output structure control register FR3 ............................................................ 10 2.1.13 Key-on wakeup control register K0 ....................................................................... 11 2.1.14 Key-on wakeup control register K1 ....................................................................... 11 2.1.15 Key-on wakeup control register K2 ....................................................................... 12 2.1.16 Connections of unused pins ................................................................................... 15 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z viii 4524 Group List of tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.2.1 Interrupt control register V1 ...................................................................................... 19 2.2.2 Interrupt control register V2 ...................................................................................... 20 2.2.3 Interrupt control register I1 ....................................................................................... 20 2.2.4 Interrupt control register I2 ....................................................................................... 21 2.2.5 Interrupt control register I3 ....................................................................................... 21 2.3.1 Interrupt control register V1 ...................................................................................... 34 2.3.2 Interrupt control register V2 ...................................................................................... 34 2.3.3 Interrupt control register I3 ....................................................................................... 35 2.3.4 Timer control register PA .......................................................................................... 35 2.3.5 Timer control register W1 ......................................................................................... 35 2.3.6 Timer control register W2 ......................................................................................... 36 2.3.7 Timer control register W3 ......................................................................................... 36 2.3.8 Timer control register W4 ......................................................................................... 37 2.3.9 Timer control register W5 ......................................................................................... 37 2.3.10 Timer control register W6 ....................................................................................... 38 2.4.1 Interrupt control register V2 ...................................................................................... 51 2.4.2 A/D control register Q1 ............................................................................................. 51 2.4.3 A/D control register Q2 ............................................................................................. 52 2.4.4 A/D control register Q3 ............................................................................................. 52 2.4.5 Recommended operating conditions (when using A/D converter) ...................... 55 2.5.1 Interrupt control register V2 ...................................................................................... 57 2.5.2 Interrupt control register I3 ....................................................................................... 57 2.5.3 Serial I/O mode register J1 ...................................................................................... 58 2.6.1 Duty and maximum number of displayed pixels .................................................... 66 2.6.2 LCD control register L1 ............................................................................................. 67 2.6.3 LCD control register L2 ............................................................................................. 68 2.6.4 Timer control register W6 ......................................................................................... 68 2.8.1 Voltage drop detection circuit operation state ....................................................... 75 2.9.1 Functions and states retained at power down mode ............................................ 79 2.9.2 Return source and return condition ......................................................................... 80 2.9.3 Start condition identification ...................................................................................... 80 2.9.4 Interrupt control register I1 ....................................................................................... 81 2.9.5 Interrupt control register I2 ....................................................................................... 81 2.9.6 Clock control register MR ......................................................................................... 82 2.9.7 Pull-up control register PU0 ..................................................................................... 82 2.9.8 Pull-up control register PU1 ..................................................................................... 83 2.9.9 Key-on wakeup control register K0 ......................................................................... 83 2.9.10 Key-on wakeup control register K1 ....................................................................... 84 2.9.11 Key-on wakeup control register K2 ....................................................................... 84 2.10.1 Clock control register MR ....................................................................................... 90 CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.3.1 3.3.2 Absolute maximum ratings .......................................................................................... 2 Recommended operating conditions 1 ...................................................................... 3 Recommended operating conditions 2 ...................................................................... 4 Electrical characteristics 1 .......................................................................................... 5 Electrical characteristics 2 .......................................................................................... 6 A/D converter recommended operating conditions .................................................. 7 A/D converter characteristics ...................................................................................... 7 Voltage drop detection circuit characteristics ........................................................... 8 Connections of unused pins ..................................................................................... 40 Recommended operating conditions (when using A/D converter) ...................... 44 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z ix CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS CONTROL REGISTERS INSTRUCTIONS BUILT-IN PROM VERSION HARDWARE 4524 Group DESCRIPTION/FEATURES/APPLICATION DESCRIPTION The 4524 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with main clock selection function, serial I/O, four 8-bit timers (each timer has one or two reload registers), 10-bit A/D converter, interrupts, and LCD control circuit. The various microcomputers in the 4524 Group include variations of the built-in memory size as shown in the table below. FEATURES q Minimum instruction execution time .................................. 0.5 µs (at 6 MHz oscillation frequency, in high-speed through-mode) q Supply voltage Mask ROM version ...................................................... 2.0 to 5.5 V One Time PROM version ............................................. 2.5 to 5.5 V (It depends on oscillation frequency and operation mode) q Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 4 ................................. 8-bit timer with two reload registers Timer 5 .............................. 16-bit timer (fixed dividing frequency) Part number M34524M8-XXXFP M34524MC-XXXFP M34524EDFP (Note) Note: Shipped in blank. q Interrupt ........................................................................ 9 sources q Key-on wakeup function pins ................................................... 10 q LCD control circuit Segment output ........................................................................ 20 Common output .......................................................................... 4 q Serial I/O ......................................................................... 8-bit ✕ 1 q A/D converter .............. 10-bit successive approximation method q Voltage drop detection circuit (Reset) ......................... Typ. 3.5 V q Watchdog timer q Clock generating circuit Main clock (ceramic resonator/RC oscillation/on-chip oscillator) Sub-clock (quartz-crystal oscillation) q LED drive directly enabled (port D) APPLICATION Household appliance, consumer electronics, office automation equipment ROM (PROM) size (✕ 10 bits) 8192 words 12288 words 16384 words RAM size (✕ 4 bits) 512 words 512 words 512 words Package 64P6N-A 64P6N-A 64P6N-A ROM type Mask ROM Mask ROM One Time PROM Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-2 HARDWARE 4524 Group PIN CONFIGURATION PIN CONFIGURATION COM0 COM1 COM2 COM3 P00 P01 P02 P03 P10 P11 P12 P13 D0 D1 D2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VLC3/SEG0 VLC2/SEG1 VLC1/SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D4/SIN D5/SOUT D6/SCK C N VS S VDCE XCIN XCOUT VDD VSS XOUT XIN RESET D7/CNTR0 C/CNTR1 M34524Mx-XXXFP M34524EDFP D8/INT0 D9/INT1 P32/AIN6 P31/AIN5 P30/AIN4 P23/AIN3 OUTLINE 64P6N-A Pin configuration (top view) (4524 Group) P22/AIN2 P21/AIN1 P33/AIN7 P20/AIN0 SEG17 SEG18 SEG19 P43 P42 SEG16 P41 P40 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-3 4524 Group 4 4 4 4 4 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Block diagram (4524 Group) I/O port Port P0 Port P1 Port P2 Port P3 Port P4 Internal peripheral functions System clock generation circuit XIN -XOUT (Main clock) XCIN -XCOUT (Sub-clock) Power-on reset circuit Voltage drop detection circuit Timer Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits) Timer 5(16 bits) Watchdog timer (16 bits) A/D converter (10 bits ✕ 8 ch) Memory ROM 8192, 12288, 16384 words ✕ 10 bits Serial I/O (8 bits ✕ 1) 4500 series CPU core ALU(4 bits) Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) LCD drive control circuit (Max.20 segments ✕ 4 common) RAM 512 words ✕ 4 bits LCD display RAM including 20 words ✕ 4 bits Segment output 4 Common output Port C Port D BLOCK DIAGRAM HARDWARE 20 1 2 8 1-4 HARDWARE 4524 Group PERFORMANCE OVERVIEW PERFORMANCE OVERVIEW Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34524M8 M34524MC M34524ED RAM Input/Output D0–D7 I/O ports Function 159 0.5 µs (at 6 MHz oscillation frequency, in high-speed through mode) 8192 words ✕ 10 bits 12288 words ✕ 10 bits 16384 words ✕ 10 bits 512 words ✕ 4 bits (including LCD display RAM 20 words ✕ 4 bits) Eight independent I/O ports. Input is examined by skip decision. The output structure can be switched by software. Ports D4, D5, D6 and D7 are also used as SIN, SOUT, SCK and CNTR0 pin. Two independent output ports. Ports D8 and D9 are also used as INT0 and INT1, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; Ports P20–P23 are also used as AIN0–AIN3, respectively. 4-bit I/O port; Ports P30–P33 are also used as AIN4–AIN7, respectively. 4-bit I/O port; The output structure can be switched by software. 1-bit output; Port C is also used as CNTR1 pin. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with two reload registers. 16-bit timer, fixed dividing frequency 10-bit ✕ 1, 8-bit comparator is equipped. 8-bit ✕ 1 1/2, 1/3 bias 2, 3, 4 duty 4 20 2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (they can be switched by software.) 9 (two for external, five for timer, A/D, serial I/O) 1 level 8 levels CMOS silicon gate 64-pin plastic molded QFP (64P6N) –20 °C to 85 °C 2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.8 mA (Ta=25°C, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN)) 20 µA (Ta=25°C, VDD = 5 V, f(XCIN) = 32 kHz) 0.1 µA (Ta=25°C, VDD = 5 V) D 8 , D9 Output P00–P03 I/O P10–P13 I/O P20–P23 P30–P33 P40–P43 C Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 I/O I/O I/O Output Timers A/D converter Serial I/O LCD control Selective bias value circuit Selective duty value Common output Segment output Internal resistor for power supply Interrupt Sources Nesting Subroutine nesting Device structure Package Operating temperature range Supply Mask ROM version voltage One Time PROM version Power Active mode dissipation Clock operating mode At RAM back-up Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-5 HARDWARE 4524 Group PIN DESCRIPTION PIN DESCRIPTION Pin VDD VSS CNVSS VDCE Name Power supply Ground CNVSS Voltage drop detection circuit enable Reset input/output Input/Output — — — Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is input to this pin, the circuit starts operating. When “L“ level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the built-in power-on reset, or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins X IN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports D4–D7 is also used as SIN, SOUT, SCK and CNTR0 pin. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D8 and D9 are also used as INT0 pin and INT1 pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P20–P23 are also used as AIN0–AIN3, respectively. Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to “1”. Ports P30–P33 are also used as AIN4–AIN7, respectively. Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR1 pin. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0– COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty. LCD segment output pins. SEG0–SEG2 pins are used as VLC3–VLC1 pins, respectively. LCD power supply pins. When the internal resistor is used, VDD pin is connected to VLC3 pin (if luminance adjustment is required, VDD pin is connected to VLC3 pin through a resistor). When the external power supply is used, apply the voltage 0 ≤ VLC1 ≤ VLC2 ≤ VLC3 ≤ VDD. VLC3–VLC1 pins are used as SEG0–SEG2 pins, respectively. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D7 and C, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports D8 and D9, respectively. A/D converter analog input pins. AIN0–AIN7 are also used as ports P20–P23 and P30– P33, respectively. Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port D6. Serial I/O data output pin. SOUT pin is also used as port D5. Serial I/O data input pin. SIN pin is also used as port D4. RESET I/O XIN XOUT XCIN XCOUT D0–D7 Main clock input Main clock output Sub-clock input Sub-clock output I/O port D Input is examined by skip decision. Output port D Input Output Input Output I/O D 8 , D9 Output P00–P03 I/O port P0 I/O P10–P13 I/O port P1 I/O P20–P23 I/O port P2 I/O P30–P33 I/O port P3 I/O P40–P43 I/O port P4 I/O Output port C Port C Common output COM0– COM3 SEG0–SEG19 Segment output VLC3–VLC1 LCD power supply Output Output Output – CNTR0, CNTR1 Timer input/output I/O INT0, INT1 Interrupt input Input AIN0–AIN7 SCK SOUT SIN Analog input Serial I/O data I/O Serial I/O data output Serial I/O clock input Input I/O Output Input Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-6 HARDWARE 4524 Group MULTIFUNCTION/DEFINITION OF CLOCK AND CYCLE MULTIFUNCTION Pin D4 D5 D6 D7 D8 D9 VLC3 VLC2 VLC1 Multifunction SIN SOUT SCK CNTR0 INT0 INT1 SEG0 SEG1 SEG2 Pin SIN SOUT SCK CNTR0 INT0 INT1 SEG0 SEG1 SEG2 Multifunction D4 D5 D6 D7 D8 D9 VLC3 VLC2 VLC1 Pin C P20 P21 P22 P23 P30 P31 P32 P33 Multifunction CNTR1 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Pin CNTR1 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Multifunction C P20 P21 P22 P23 P30 P31 P32 P33 Notes 1: Pins except above have just single function. 2: The output of D8 and D9 can be used even when INT0 and INT1 are selected. 3: The input of ports D4–D6 can be used even when SIN, SOUT and SCK are selected. 4: The input/output of D7 can be used even when CNTR0 (input) is selected. 5: The input of D7 can be used even when CNTR0 (output) is selected. 6: The port C “H” output function can be used even when CNTR1 (output) is selected. DEFINITION OF CLOCK AND CYCLE q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. • Clock (f(XIN)) by the external ceramic resonator • Clock (f(XIN)) by the external RC oscillation • Clock (f(XIN)) by the external input • Clock (f(RING)) of the on-chip oscillator which is the internal oscillator • Clock (f(XCIN)) by the external quartz-crystal oscillation Table Selection of system clock Register MR System clock MR3 MR2 MR1 MR0 0 0 0 0 f(STCK) = f(XIN) or f(RING) ✕ 1 f(STCK) = f(XCIN) 0 1 0 0 f(STCK) = f(XIN)/2 or f(RING)/2 ✕ 1 f(STCK) = f(XCIN)/2 1 0 0 0 f(STCK) = f(XIN)/4 or f(RING)/4 ✕ 1 f(STCK) = f(XCIN)/4 1 1 0 0 f(STCK) = f(XIN)/8 or f(RING)/8 ✕ 1 f(STCK) = f(XCIN)/8 ✕: 0 or 1 Note: The f(RING)/8 is selected after system is released from reset. q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode High-speed through mode Low-speed through mode High-speed frequency divided by 2 mode Low-speed frequency divided by 2 mode High-speed frequency divided by 4 mode Low-speed frequency divided by 4 mode High-speed frequency divided by 8 mode Low-speed frequency divided by 8 mode Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-7 HARDWARE 4524 Group PORT FUNCTION PORT FUNCTION Port Port D Pin D0–D3, D4/SIN, D5/SOUT, D6/SCK, D7/CNTR0 D8/INT0, D9/INT1 Input Output I/O (8) Output (2) I/O (4) I/O (4) I/O (4) I/O (4) I/O (4) Output (1) Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain N-channel open-drain/ CMOS CMOS 4 OP0A IAP0 OP1A IAP1 OP2A IAP2 OP3A IAP3 OP4A IAP4 RCP SCP I/O unit 1 Control instructions SD, RD SZD CLD Control registers FR1, FR2 J1 W6 I1, I2 K2 FR0 PU0 K0 FR0 PU1 K1 Q2 Q3 FR3 W4 Output structure selection function (programmable) Remark Output structure selection function (programmable) Key-on wakeup function (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable) Port P0 P00–P03 Port P1 P10–P13 4 Port P2 P20/AIN0–P23/AIN3 Port P3 P30/AIN4–P33/AIN7 Port P4 P40–P43 Port C C/CNTR1 4 4 4 1 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-8 HARDWARE 4524 Group CONNECTION OF UNUSED PINS CONNECTIONS OF UNUSED PINS Pin XIN Connection Connect to VSS. Usage condition Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) Sub-clock input is selected for system clock (MR0=1). (Note 2) Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) RC oscillator is selected (CRCK instruction is executed) External clock input is selected for main clock (CMCK instruction is executed). (Note 3) Sub-clock input is selected for system clock (MR0=1). (Note 2) Sub-clock is not used. Sub-clock is not used. N-channel open-drain is selected for the output structure. (Note 4) SIN pin is not selected. N-channel open-drain is selected for the output structure. N-channel open-drain is selected for the output structure. SCK pin is not selected. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. “0” is set to output latch. “0” is set to output latch. CNTR1 input is not selected for timer 3 count source. The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) XOUT Open. XCIN XCOUT D0–D3 D4/SIN D5/SOUT D6/SCK D7/CNTR0 D8/INT0 D9/INT1 C/CNTR1 P00–P03 Connect to VSS. Open. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Open. Connect to Vss. P10–P13 Open. Connect to Vss. P20/AIN0– P23/AIN3 P30/AIN4– P33/AIN7 P40–P43 COM0–COM3 VLC3/SEG0 VLC2/SEG1 VLC1/SEG2 SEG3–SEG19 Open. Connect to Vss. Open. Connect to Vss. Open. Connect to Vss. Open. Open. Open. Open. Open. N-channel open-drain is selected for the output structure. (Note 5) SEG0 pin is selected. SEG1 pin is selected. SEG2 pin is selected. Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock. 2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting “1” to bit 1 (MR1) of clock control register MR, main clock is stopped. 3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock. 4: Be sure to select the output structure of ports D0–D3 and P40–P43 and the pull-up function and key-on wakeup function of P00–P03 and P10–P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open. (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-9 HARDWARE 4524 Group PORT BLOCK DIAGRAM PORT BLOCK DIAGRAMS Clock (input) for timer 3 event count W 31 PWMOD W 30 (Note 1) C/CNTR1 (Note 2, Note 3) SCP instruction RCP instruction SQ R D Q R T W61 Timer 3 underflow signal W32 Register Y Decoder Skip decision (SZD instruction) FR 10 (Note 1) S RQ Skip decision (SZD instruction) FR11 (Note 1) S D1 (Note 2) D0 (Note 2) CLD instruction SD instruction RD instruction Register Y Decoder CLD instruction SD instruction RD instruction RQ Skip decision (SZD instruction) FR12 (Note 1) S RQ Skip decision (SZD instruction) FR13 (Note 1) S RQ D3 (Note 2) D2 (Note 2) Register Y Decoder CLD instruction SD instruction RD instruction Register Y Decoder CLD instruction SD instruction RD instruction This symbol represents a parasitic diode on the port. Notes 1: 2: Applied potential to these ports must be VDD or less. 3: When CNTR1 input is selected, output transistor is turned OFF. Port block diagram (1) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-10 HARDWARE 4524 Group PORT BLOCK DIAGRAM Register Y Decoder Skip decision (SZD instruction) CLD instruction SD instruction RD instruction F R 20 (Note 1) SQ R J11 Serial data input Skip decision (SZD instruction) FR21 S J10 RQ 0 1 D4/SIN (Note 2) Register Y Decoder CLD instruction SD instruction RD instruction Serial data output (Note 1) D5/SOUT (Note 2) Register Y Decoder Skip decision (SZD instruction) CLD instruction SD instruction RD instruction J11 J10 Synchronous clock (output) for serial data transfer Synchronous clock (input) for serial data transfer R FR22 (Note 1) SQ D6/SCK (Note 2) J13 J12 Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (2) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-11 HARDWARE 4524 Group PORT BLOCK DIAGRAM Register Y Decoder Skip decision (SZD instruction) F R 23 S W60 RQ 0 1 CLD instruction SD instruction RD instruction (Note 1) D7/CNTR0 (Note 2) Underflow signal divided by 2 of timer 1 or timer 2 Clock (input) for timer 1 event count Timer 1 count start synchronous circuit input Key-on wakeup External 0 interrupt Register Y Decoder CLD instruction SD instruction RD instruction Timer 3 count start synchronous circuit input Key-on wakeup External 1 interrupt Register Y Decoder CLD instruction SD instruction RD instruction S RQ S RQ W11 W10 (Note 3) External 0 interrupt circuit (Note 1) D8/INT0 (Note 2) (Note 3) External 1 interrupt circuit (Note 1) D9/INT1 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the description of external interrupt circuit. Port block diagram (3) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-12 HARDWARE 4524 Group PORT BLOCK DIAGRAM IAP0 instruction Register A A0 FR00 Pull-up transistor PU00 (Note 1) A0 OP0A instruction D TQ K00 Key-on wakeup “L” level detection circuit P00 (Note 2) IAP0 instruction Register A A1 FR00 Pull-up transistor PU01 (Note 1) A1 OP0A instruction D TQ K01 Key-on wakeup “L” level detection circuit P01 (Note 2) Register A A2 IAP0 instruction Pull-up transistor PU02 FR01 A2 OP0A instruction D TQ K02 Key-on wakeup “L” level detection circuit (Note 1) P02 (Note 2) Register A A3 IAP0 instruction Pull-up transistor PU03 FR01 A3 OP0A instruction D TQ K03 Key-on wakeup “L” level detection circuit (Note 1) P03 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (4) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-13 HARDWARE 4524 Group PORT BLOCK DIAGRAM IAP1 instruction Register A A0 F R 02 Pull-up transistor PU10 (Note 1) A0 OP1A instuction D TQ K10 Key-on wakeup “L” level detection circuit Pull-up transistor P10 (Note 2) IAP1 instruction Register A A1 F R 02 PU11 (Note 1) A1 OP1A instuction D TQ K11 Key-on wakeup “L” level detection circuit Pull-up transistor P11 (Note 2) IAP1 instruction Register A A2 F R 03 PU12 (Note 1) A2 OP1A instuction D TQ K12 Key-on wakeup “L” level detection circuit Pull-up transistor P12 (Note 2) IAP1 instruction Register A A3 F R 03 PU13 (Note 1) A3 OP1A instuction D TQ K13 Key-on wakeup “L” level detection circuit P13 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (5) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-14 HARDWARE 4524 Group PORT BLOCK DIAGRAM Ai IAP2 instruction Register A (Note 3) Ai OP2A instruction D TQ (Note 3) Q2i 0 1 Q2i (Note 3) (Note 1) P20/AIN0–P23/AIN3 (Note 2) Q1 Decoder Analog input Ai Register A (Note 3) Ai OP3A instruction D TQ IAP3 instruction Q3i (Note 3) Q3i 0 1 (Note 3) (Note 1) P30/AIN4–P33/AIN7 (Note 2) Q1 Decoder Analog input IAP4 instruction Ai Register A (Note 3) Ai OP4A instruction (Note 3) FR3i (Note 1) D TQ P40–P43 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. Port block diagram (6) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-15 HARDWARE 4524 Group PORT BLOCK DIAGRAM LCD power supply LCD control signal Connecting to • when SEG is selected. (Note 1) VLC3/SEG0 (Notes 2 and 3) VDD L23 LCD power supply LCD power supply (VLC3/VDD) LCD power supply LCD control signal Connecting to • when SEG is selected. (Note 1) VLC2/SEG1 (Note 2) L22 LCD power supply (VLC2) LCD power supply L11 LCD control signal Connecting to • when SEG is selected. LCD power supply (Note 1) VLC1/SEG2 (Note 2) L21 LCD power supply LCD power supply (VLC1) L13 L20 Reset signal L12 EPOF+POF2 instruction (Continuous execution) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential when VLC is selected must be as follows; • VDD ≥ VLC3 ≥ VLC2 ≥ VLC1 3: VLC3 = VDD when SEG is selected. Port block diagram (7) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-16 HARDWARE 4524 Group PORT BLOCK DIAGRAM LCD power supply LCD control signal Pch SEG3–SEG19 LCD control signal LCD power supply LCD power supply LCD control signal Nch Pch COM0–COM3 Pch LCD control signal LCD power supply LCD power supply LCD control signal Nch Nch LCD control signal Port block diagram (8) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-17 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. (CY) (M(DP)) Addition (A) Fig. 1 AMC instruction execution example ALU (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A TBA instruction Fig. 3 Registers A, B and register E TABP p instruction Specifying address ROM 8 4 0 p6 p5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1DR0 A3 A2 A1 A0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) Immediate field value p The contents of The contents of register D register A Fig. 4 TABP p instruction execution example Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-18 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1 : NOP · · · RT (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. (PC) ← (SK0) (SP) ← 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-19 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H ( most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Register Y (4) Specifying RAM digit Register X (4) Specifying RAM file Register Z (2) Specifying RAM file group Fig. 8 Data pointer (DP) structure Specifying bit position Set D3 D2 D1 D0 0 0 0 1 1 Port D output latch Register Y (4) Fig. 9 SD instruction execution example Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-20 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34524ED. Table 1 ROM size and pages Part number M34524M8 M34524MC M34524ED ROM (PROM) size (✕ 10 bits) 8192 words 12288 words 16384 words Pages 64 (0 to 63) 96 (0 to 95) 128 (0 to 127) 9876543210 000016 007F16 008016 00FF16 010016 017F16 018016 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3 Note: Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. 3FFF16 Page 127 Fig. 10 ROM map of M34524ED 008016 008216 008416 008616 008816 008A16 008C16 008E16 9876543210 External 0 interrupt address External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address Timer 5 interrupt address A/D interrupt address T imer 4, Serial I/O interrupt address 00FF16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-21 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). RAM includes the area for LCD. When writing “1” to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map. • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Table 2 RAM size Part number M34524M8 M34524MC M34524ED RAM size 512 words ✕ 4 bits (2048 bits) 512 words ✕ 4 bits (2048 bits) 512 words ✕ 4 bits (2048 bits) RAM 512 words ✕ 4 bits (2048 bits) Register Z 1 0 Register X 0 1 2 3 ... 12 13 14 15 0 1 2 ... 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Y 12 13 14 15 0 1 2 3 4 5 6 8 16 9 17 10 18 11 19 12 13 14 7 15 Note: The numbers in the shaded area indicate the corresponding segment output pin numbers. Fig. 12 RAM map Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-22 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 5 6 7 8 External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt A/D interrupt Timer 4 interrupt or Serial I/O interrupt (Note) Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 5 underflow Completion of A/D conversion Timer 4 underflow or completion of serial I/O transmit/ receive (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1 (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4, serial I/O interrupt source selection bit (I30). Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt A/D interrupt Timer 4 interrupt Serial I/O interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T5F ADF T4F SIOF Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT5 SNZAD SNZT4 SNZSI Interrupt nable bit V10 V11 V12 V13 V20 V21 V22 V23 V23 (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “ 1. ” E ach interrupt request flag is cleared to “0” when either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. Each interrupt request flag is set to “1” when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until it is cleared to “0” by the interrupt occurrence or the skip instruction. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set to “1” when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0 Skip instruction Invalid Valid Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-23 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.” • Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). • Program counter (PC) ............................................................... Each interrupt address • Stack register (SK) The address of main routine to be .................................................................................................... executed when returning • Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 • Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Activated condition INT0 pin interrupt waveform input Request flag Enable bit (state retained) Enable flag EXF0 V10 Address 0 in page 1 INT1 pin interrupt waveform input EXF1 V11 Address 2 in page 1 Timer 1 underflow Main routine Timer 2 underflow T1F V12 Address 4 in page 1 Interrupt service routine Interrupt occurs T2F V13 Address 6 in page 1 Timer 3 underflow T3F V20 Address 8 in page 1 • • • • Timer 5 underflow T5F V21 Address A in page 1 EI R TI Interrupt is enabled A/D conversion completed ADF V 22 Address C in page 1 Timer 4 underflow T4F V23 INTE Address E in page 1 0 Serial I/O transmit/receive completed 1 SIOF I30 : Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing Fig. 15 Interrupt system diagram Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-24 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. • Interrupt control register V2 The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 • Interrupt control register I3 The timer 4, serial I/O interrupt source selection bit is assigned to register I3. Set the contents of this register through register A with the TI3A instruction. The TAI3 instruction can be used to transfer the contents of register I3 to register A. at reset : 00002 at power down : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) (Note 2) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2) R/W TAV2/TV2A Interrupt control register V2 V23 V22 V21 V20 Timer 4, serial I/O interrupt enable bit (Note 3) A/D interrupt enable bit Timer 5 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 Interrupt disabled (SNZT4, SNZSI instruction is valid) Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) Interrupt disabled (SNZT5 instruction is valid) Interrupt enabled (SNZT5 instruction is invalid) (Note 2) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) (Note 2) R/W TAI3/TI3A Interrupt control register I3 I30 Timer 4, serial I/O interrupt source selection bit 0 1 at reset : 02 at power down : state retained Timer 4 interrupt valid, serial I/O interrupt invalid Serial I/O interrupt valid, timer 4 interrupt invalid Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30). (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V1 3, V20–V23), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the machine cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles when the interrupt conditions are satisfied on execution of two-cycle instructions or three-cycle instructions. (Refer to Figure 16). Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-25 4524 Group Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z T3 T1 T1 T1 T1 T2 T3 T2 T3 T2 T3 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) The program starts from the interrupt address. Fig. 16 Interrupt sequence q When an interrupt request flag is set after its interrupt is enabled (Note 1) 1 machine cycle T1 T2 System clock (STCK) EI instruction execution cycle Interrupt enable flag (INTE) INT0,INT1 External interrupt EXF0,EXF1 Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, A/D and Serial I/O interrupts T1F,T2F,T3F,T4F T5F,ADF,SIOF F UNCTION BLOCK OPERATIONS Notes 1: The address to be executed when returning to the main routine is stacked to the last machine cycle. 2: The cycles are as follows according to the executed instruction at the time when each interrupt activated condition is satisfied. On execution of one-cycle instruction: Interrupt occurs after 2 machine cycles. On execution of two-cycle instruction: Interrupt occurs after 3 machine cycles. On execution of three-cycle instruction: Interrupt occurs after 3 machine cycles. HARDWARE 1-26 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS EXTERNAL INTERRUPTS The 4524 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin D8/INT0 Activated condition When the next waveform is input to D8/INT0 pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms External 1 interrupt D9/INT1 When the next waveform is input to D9/INT1 pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms I21 I22 Valid waveform selection bit I11 I12 (Note 1) D8/INT0 I12 Falling 0 1 Rising One-sided edge detection circuit I11 0 EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit 1 External 0 interrupt I13 Timer 1 count start synchronous circuit K21 0 Key-on wakeup 1 Skip decision (SNZI0 instruction) (Note 1) D9/INT1 I22 Falling 0 1 Rising One-sided edge detection circuit I21 0 EXF1 Both edges detection circuit (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Skip decision (SNZI1 instruction) 1 External 1 interrupt I23 Timer 3 count start synchronous circuit K23 0 Key-on wakeup 1 Notes 1: This symbol represents a parasitic diode on the port. 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Fig. 17 External interrupt circuit structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-27 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to D8/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D8/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V10) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the D8/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to D9/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to D9/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. ➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I2. ➂ Clear the EXF1 flag to “0” with the SNZ1 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. ➄ Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid waveform is input to the D9/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-28 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (3) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 • Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. at reset : 00002 at power down : state retained R/W TAI1/TI1A INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I12 Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) I11 I10 INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W TAI2/TI2A INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected I22 Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) I21 I20 INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-29 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (4) Notes on External 0 interrupts ➀ Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “ 0 ” a fter executing at least one instruction (refer to Figure 18➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂). ➂ Note on bit 2 of register I1 When the interrupt valid waveform of the D8/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “ 0 ” a fter executing at least one instruction (refer to Figure 20➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂). ••• ••• LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT0 pin input is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared, the power down function is selected and the input of INT0 pin is disabled, be careful about the following notes. • W hen the input of INT0 pin is disabled, invalidate the key-on wakeup function of INT0 pin (register K2 0 = “0”) before system goes into the power down mode. (refer to Figure 19➀). ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3 ••• LA 0 TK2A DI EPOF POF2 ; (✕✕✕02) ; INT0 key-on wakeup invalid ........... ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2 ••• ••• Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-30 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (5) Notes on External 1 interrupts ➀ Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. • Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 21➀) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “ 0 ” a fter executing at least one instruction (refer to Figure 21➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21➂). ➂ Note on bit 2 of register I2 When the interrupt valid waveform of the D9/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. • Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 23➀) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to “ 0 ” a fter executing at least one instruction (refer to Figure 23➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23➂). ••• ••• LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT1 pin input is changed ........................................................... ➁ ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP ; (✕✕0✕2) ; The SNZ1 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 21 External 1 interrupt program example-1 ➁ Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared, the power down function is selected and the input of INT1 pin is disabled, be careful about the following notes. • W hen the input of INT1 pin is disabled, invalidate the key-on wakeup function of INT1 pin (register K2 2 = “0”) before system goes into the power down mode. (refer to Figure 22➀). ✕ : these bits are not used here. Fig. 23 External 1 interrupt program example-3 ••• LA 0 TK2A DI EPOF POF2 ; (✕0✕✕2) ; INT1 key-on wakeup invalid ........... ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 22 External 1 interrupt program example-2 ••• ••• Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-31 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS TIMERS The 4524 Group has the following timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). • Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. F F1 6 n : Counter initial value Count starts n Reload Reload The contents of counter 1st underflow 2nd underflow 0016 Time n+1 count “1” Timer interrupt “0” request flag An interrupt occurs or a skip instruction is executed. n+1 count Fig. 24 Auto-reload function The 4524 Group timer consists of the following circuits. • Prescaler : 8-bit programmable timer • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 8-bit programmable timer • Timer 4 : 8-bit programmable timer • Timer 5 : 16-bit fixed dividing frequency timer • Timer LC : 4-bit programmable timer • Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-32 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Table 9 Function related timers Circuit Prescaler Timer 1 Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) Count source • Instruction clock (INSTCK) • Instruction clock (INSTCK) • Prescaler output (ORCLK) • Timer 5 underflow (T5UDF) • CNTR0 input Timer 2 8-bit programmable binary down counter • System clock (STCK) • Prescaler output (ORCLK) • Timer 1 underflow (T1UDF) • PWM output (PWMOUT) Timer 3 8-bit programmable binary down counter (link to INT1 input) • PWM output (PWMOUT) • Prescaler output (ORCLK) • Timer 2 underflow (T2UDF) • CNTR1 input Timer 4 8-bit programmable binary down counter Timer 5 • XIN input • Prescaler output (ORCLK) 8192 16384 32768 65536 Timer LC Watchdog timer 4-bit programmable binary down counter 16-bit fixed dividing frequency • Bit 4 of timer 5 • Prescaler output (ORCLK) • Instruction clock (INSTCK) 65534 • System reset (count twice) • WDF flag decision 1 to 16 • LCD clock W6 1 to 256 • Timer 2, 3 count source • CNTR1 output • Timer 4 interrupt • Timer 1, LC count source • Timer 5 interrupt W5 W4 1 to 256 • CNTR1 output control • Timer 3 interrupt W3 1 to 256 • Timer 3 count source • CNTR0 output • Timer 2 interrupt W2 Frequency dividing ratio 1 to 256 1 to 256 Use of output signal • Timer 1, 2, 3, 4 and LC count sources • Timer 2 count source • CNTR0 output • Timer 1 interrupt Control register PA W1 W2 (PWM output function) • XCIN input 16-bit fixed dividing frequency Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-33 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Division circuit On-chip oscillator (CMCK) Ceramic resonance Multiplexer (CMCK/CRCK) (Note 1) MR0 0 1 Divided by 8 Divided by4 Divided by 2 MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) XI N RC oscillation (CRCK) PA0 (Note 4) 0 Prescaler (8) 1 XCIN Quartz-crystal oscillation W60 0 Port D7 output W23 0 1 I1 2 Falling 0 1 Rising I10 W13 ORCLK D7/CNTR0 1 1 /2 1 /2 T1UDF T2UDF (TABPS) Reload register RPS (8) (TPSAB) (TPSAB) (TPSAB) (TABPS) Register B Register A D8/INT0 I1 3 One-sided edge detection circuit I11 0 1 (Note 2) SQ I10 1 0 Both edges detection circuit R T1UDF W11, W10 00 (Note 4) W12 0 1 (TAB1) (T1AB) Timer 1 (8) Reload register R1 (8) (TR1AB) (T1AB) (T1AB) (TAB1) T1F Timer 1 interrupt INSTCK ORCLK T5UDF D7/CNTR0 01 10 11 Register B Register A Timer 1 underflow signal (T1UDF) W21, W20 00 STCK ORCLK T1UDF PWMOUT 01 10 11 (Note 4) W22 0 1 (TAB2) Timer 2 (8) Reload register R2 (8) (T2AB) (T2AB) (T2AB) (TAB2) T2F Timer 2 interrupt Register B Register A Timer 2 underflow signal (T2UDF) D9/INT1 I23 I2 2 Falling 0 1 Rising I20 W33 One-sided edge detection circuit I2 1 (Note 3) 0 SQ 1 R I20 1 0 Both edges detection circuit T3UDF W31, W30 00 (Note 4) W32 0 1 (TAB3) (T3AB) Timer 3 (8) Reload register R3 (8) (TR3AB) (T3AB) (T3AB) (TAB3) T3F Timer 3 interrupt PWMOUT ORCLK T2UDF C/CNTR1 01 10 11 Register B Register A Timer 3 underflow signal (T3UDF) T5UDF: Timer 5 underflow signal (from timer 5) PWMOUT: PWM output signal (from timer 4 output unit) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When any instructions are not executed, on-chip oscillator clock (internal oscillation) is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of D8/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: Timer 3 count start synchronous circuit is set by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 4: Count source is stopped by clearing to “0.” Fig. 25 Timer structure (1) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-34 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Register B Register A (T4HAB) Reload register R4H (8) (Note 5) W40 0 1 /2 1 (Note 4) W41 0 Reload control circuit W 42 XIN ORCLK Timer 4 (8) 1 (T4R4L) (T4AB) “H” interval expansion 1 T 0 Q R W43 PWMOD Reload register R4L (8) (TAB4) (T4AB) (TAB4) Register B Register A SIOF T4F (From Serial I/O) Port C output I30 0 1 Timer 4, Serial I/O interrupt PWMOUT (To timer 2 and timer 3) C/CNTR1 W31 W30 W32 (Note 4) W52 0 Q R D T W61 PWMOD T3UDF Timer 5 (16) (Note 6) 1 - - 4 - - - - - - - -13 14 15 16 W51, W50 11 10 01 00 (Note 4) W63 0 Timer LC (4) 1 XCIN 1 T5F Timer 5 interrupt Timer 5 underflow signal (T5UDF) W 62 0 1/2 LCD clock ORCLK 1 Reload register RLC (4) (TLCA) (TLCA) Register A Watchdog timer (16) INSTCK 1 - - - - - - - - - - - - - - - - - - - 16 (Note 7) S Q WDF1 R WRST instruction Reset signal S Q (Note 9) WEF DWDT instruction R + WRST instruction(Note 8) D Q WDF2 TR Watchdog reset signal Reset signal INSTCK : Instruction clock (system clock divided by 3) ORCLK : Prescaler output (instruction clock divided by 1 to 256) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 4: Count source is stopped by clearing to “0.” 5: XIN cannot be used as count source when bit 1 (MR1) of register MR is set to “1” and f(XIN) oscillation is stopped. 6: This timer is initialized (initial value = FFFF16) by stop of count source (W52 = “0”). 7: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = “1”. The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = “0”. 8: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 9: The WEF flag is set to “1” at system reset or RAM back-up mode. Fig. 26 Timer structure (2) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-35 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state initialized) Operating R/W TAW1/TW1A at power down : 02 W TPAA Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit 0 1 0 1 at reset : 00002 at power down : state retained Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating W11 W10 Count source 0 Instruction clock (INSTCK) 0 0 Prescaler output (ORCLK) 1 1 Timer 5 underflow signal (T5UDF) 0 1 CNTR0 input 1 R/W TAW2/TW2A Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output control bit Timer 2 control bit 0 1 0 1 at reset : 00002 at power down : state retained Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating W21 W20 Count source 0 System clock (STCK) 0 0 Prescaler output (ORCLK) 1 1 Timer 1 underflow signal (T1UDF) 0 1 PWM signal (PWMOUT) 1 R/W TAW3/TW3A Timer control register W3 W33 W32 W31 Timer 3 count source selection bits (Note 4) Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit 0 1 0 1 at reset : 00002 at power down : state retained W30 Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating W31 W30 Count source 0 PWM signal (PWMOUT) 0 0 Prescaler output (ORCLK) 1 1 Timer 2 underflow signal (T2UDF) 0 1 CNTR1 input 1 Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”). 4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-36 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Timer control register W4 W43 W42 W41 W40 CNTR1 output control bit PWM signal “H” interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 R/W TAW4/TW4A CNTR1 output invalid CNTR1 output valid PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2 Timer control register W5 W53 W52 W51 Timer 5 count value selection bits W50 Not used Timer 5 control bit 0 1 0 1 at reset : 00002 at power down : state retained R/W TAW5/TW5A This bit has no function, but read/write is enabled. Stop (state initialized) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts R/W TAW6/TW6A W51 W50 0 0 0 1 1 0 1 1 Timer control register W6 W63 W62 W61 W60 Timer LC control bit Timer LC count source selection bit CNTR1 output auto-control circuit selection bit D7/CNTR0 pin function selection bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained Stop (state retained) Operating Bit 4 (T54) of timer 5 Prescaler output (ORCLK) CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D7(I/O)/CNTR0 input CNTR0 input/output/D7 (input) Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-37 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (1) Timer control registers • Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. • Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. • Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. • Timer control register W3 Register W3 controls the selection of timer 3 count auto-stop circuit, and the count operation and count source of timer 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. • Timer control register W4 Register W4 controls the CNTR1 output, the expansion of “H” interval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. • Timer control register W5 Register W5 controls the count operation and count source of timer 5. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. • Timer control register W6 Register W6 controls the operation and count source of timer LC, the selection of CNTR1 output auto-control circuit and the D7/ CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.. (2) Prescaler (interrupt function) Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, 4 and LC count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to “0” and setting bit 0 of register W6 to “1”. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-38 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 2 of register W2 to “1.” When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to “1” and setting bit 0 of register W6 to “1”. (6) Timer 4 (interrupt function) Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; ➀ set data in timer 4 ➁ set count source by bit 0 of register W4, and ➂ set the bit 1 of register W4 to “1.” When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4L, and count continues (auto-reload function). When bit 3 of register W4 is set to “1”, timer 4 reloads data from reload register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the “L” interval set as reload register R4L, and the “H” interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to “ 1 ” a t this time, the interval (PWM signal “H” interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set “1” or more to reload register R4H. When bit 1 of register W6 is set to “1”, the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to “0”), this function is canceled. Even when bit 1 of a register W4 is cleared to “0” in the “H” interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. When clearing bit 1 of register W4 to “0” to stop timer 4, avoid a timing when timer 4 underflows. (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; ➀ set data in timer 3 ➁ set count source by bits 0 and 1 of register W3, and ➂ set the bit 2 of register W3 to “1.” When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to “1.” Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to “1.” Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-39 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (7) Timer 5 (interrupt function) Timer 5 is a 16-bit binary down counter. Timer 5 starts counting after the following process; ➀ set count value by bits 0 and 1 of register W5, and ➁ set the bit 2 of register W5 to “1.” Count source for timer 5 is the sub-clock input (XCIN). Once count is started, when timer 5 underflows (the set count value is counted), the timer 5 interrupt request flag (T5F) is set to “1,” and count continues. Bit 4 of timer 5 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W5 is cleared to “0”, timer 5 is initialized to “FFFF16” and count is stopped. Timer 5 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 5 underflow occurs at clock operating mode, system returns from the power down state. (9) Timer input/output pin (D7/CNTR0 pin, C/CNTR1 pin) CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. When the PWM signal is output from C/CNTR1 pin, set “0” to the output latch of port C. The D7/CNTR0 pin function can be selected by bit 0 of register W6. The selection of CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising waveform of CNTR0 input. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising waveform of CNTR1 input. Also, when the CNTR1 input is selected, the output of port C is invalid (high-impedance state). (8) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; ➀ set data in timer LC, ➁ select the count source with the bit 2 of register W6, and ➂ set the bit 3 of register W6 to “1.” When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes “0”), new data is loaded from reload register RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock. (10) Timer interrupt request flags (T1F, T2F, T3F, T4F, T5F) Each timer interrupt request flag is set to “ 1 ” w hen each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-40 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (11) Count start synchronization circuit (timer 1, timer 3) Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to “1” and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to “0” or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (13) Precautions Note the following for the use of timers. • Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. • Timer count source Stop timer 1, 2, 3, 4 and LC counting to change its count source. • Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. • Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its data. • Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. • Timer 4 Avoid a timing when timer 4 underflows to stop timer 4. When “H” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R4H. • Timer 5 Stop timer 5 counting to change its count source. • Timer input/output pin Set the port C output latch to “0” to output the PWM signal from C/CNTR pin. (12) Count auto-stop circuit (timer 1, timer 3) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to “1”. It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-41 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS q CNTR1 output: invalid (W43 = “0”) Timer 4 count source 0316 (R4L) (R4L) Timer 4 underflow signal PWM signal (output invalid) PWM signal “L” fixed Timer 4 start (R4L) (R4L) (R4L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 Timer 4 count value (Reload register) q CNTR1 output: valid (W43 = “1”) PWM signal “H” interval extension function: invalid (W42 = “0”) Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3 clock PWM period 7 clock 3 clock PWM period 7 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 q CNTR1 output: valid (W43 = “1”) PWM signal “H” interval extension function: valid (W42 = “1”) (Note) Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R4H. Fig. 27 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-42 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS CNTR1 output auto-control circuit by timer 3 is selected. q CNTR1 output: valid (W43 = “1”) CNTR1 output auto-control circuit selected (W61 = “1”) PWM signal Timer 3 underflow signal Timer 3 start CNTR1 output CNTR1 output start q CNTR1 output auto-control function PWM signal Timer 3 underflow signal Timer 3 start Register W61 ➀ ➁ Timer 3 stop ➂ CNTR1 output CNTR1 output start CNTR1 output stop ➀ ➁ ➂ When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to “0”. Fig. 28 CNTR1 output auto-control function by timer 3 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-43 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS qWaveform extension function of CNTR1 output “H” interval: Invalid (W42 = “0”), CNTR1 output: valid (W43 = “1”), Count source: XIN input selected (W40 = “0”), Reload register R4L: “0316” Reload register R4H: “0216” Timer 4 count start timing Machine cycle Mi Mi+1 Mi+2 TW4A instruction execution cycle (W41) ¨ 1 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal 0316 (R4L) 0216 0116 0016 0216 0116 0016 0316 0216 0116 (R4H) (R4L) Timer 4 count start timing Timer 4 count stop timing Machine cycle Mi Mi+1 Mi+2 TW4A instruction execution cycle (W41) ¨ 0 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal (Note 1) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R4H) (R4L) 0216 (R4H) Timer 4 count stop timing Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = “1”), avoid a timing when timer 4 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. 2: At CNTR1 output valid, timer 4 stops after “H” interval of PWM signal set by reload register R4H is output. Fig. 29 Timer 4 count start/stop timing Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-44 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “0000 16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of less than 65534 machine cycle by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. FFFF 1 6 Value of 16-bit timer (WDT) 000016 WDF1 flag ➁ ➁ 65534 count (Note) WDF2 flag ➃ RESET pin output ➀ Reset released ➂ WRST instruction executed (skip executed) ➄ System reset ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock. Fig. 30 Watchdog timer function Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-45 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS When the watchdog timer is used, clear the WDF1 flag at a cycle of less than 65534 machine cycles with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 31). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the system enters the power down state (refer to Figure 32). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and the WRST instruction continuously every system is returned from the power down. WRST ••• ; WDF1 flag cleared DI DWDT WRST ••• ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared Fig. 31 Program example to start/stop watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ↓ Oscillation stop Fig. 32 Program example to enter the mode when using the watchdog timer ••• ••• ••• Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-46 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS A/D CONVERTER (Comparator) The 4524 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values. Table 11 A/D converter characteristics Characteristics Parameter Successive comparison method Conversion format Resolution Relative accuracy Conversion speed Analog input pin 10 bits Linearity error: ±2LSB Differential non-linearity error: ±0.9LSB 31 µs (High-speed through-mode at 6.0 MHz oscillation frequency) 8 Register B (4) Register A (4) 4 4 IAP2 (P20–P23) IAP3 (P30–P33) OP2A (P20–P23) OP3A (P30–P33) TAQ1 TQ1A 4 TAQ2 TQ2A 4 TAQ3 TQ3A 2 Q13 Q12 Q11 Q10 Q23 Q22 Q21 Q20 Q33 Q32 Q31 Q30 4 4 4 8 TABAD 8 TADAB TALA Instruction clock 1/6 3 Q13 0 8-channel multi-plexed analog switch A/D control circuit 1 P20/AIN0 P21/AIN1 P22/AIN2 P23/AIN3 P30/AIN4 P31/AIN5 P32/AIN6 P33/AIN7 ADF (1) A/D interrupt 1 Comparator 0 Successive comparison register (AD) (10) 10 10 1 Q13 8 0 1 Q13 DAC operation signal 0 1 Q13 8 DA converter (Note 1) 8 VDD 8 VSS Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. Fig. 33 A/D conversion circuit structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-47 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Table 12 A/D control registers A/D control register Q1 Q13 A/D operation mode selection bit at reset : 00002 A/D conversion mode Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7 at power down : state retained R/W TAQ1/TQ1A Analog input pins Q12 Q11 Analog input pin selection bits Q10 A/D control register Q2 Q23 Q22 Q21 Q20 P23/AIN3 pin function selection bit P22/AIN2 pin function selection bit P21/AIN1 pin function selection bit P20/AIN0 pin function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 P23 AIN3 P22 AIN2 P21 AIN1 P20 AIN0 at power down : state retained R/W TAQ2/TQ2A A/D control register Q3 Q33 Q32 Q31 Q30 P33/AIN7 pin function selection bit P32/AIN6 pin function selection bit P31/AIN5 pin function selection bit P30/AIN4 pin function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 P33 AIN7 P32 AIN6 P31 AIN5 P30 AIN4 at power down : state retained R/W TAQ3/TQ3A Note: “R” represents read enabled, and “W” represents write enabled. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-48 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (1) A/D control register • A/D control register Q1 Register Q1 controls the selection of A/D operation mode and the selection of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. • A/D control register Q2 Register Q2 controls the selection of P20/AIN0–P23/AIN3. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A. • A/D control register Q3 Register Q3 controls the selection of P30/AIN4–P33/AIN7. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A. (4) A/D conversion completion flag (ADF) A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: ➀ When the A/D conversion starts, the register AD is cleared to “00016.” ➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage V ref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4524 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (31 µs when f(X IN) = 6.0 MHz in high-speed through mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A/D conversion completes (Figure 34). (2) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” (3) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref = V DD ✕n 1024 n: The value of register AD (n = 0 to 1023) Table 13 Change of successive comparison register AD during A/D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes ✼1: 1st comparison result ✼3: 3rd comparison result ✼9: 9th comparison result Change of successive comparison register AD ------------- Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4 ○ ○ ○ ○ 1 ✼1 ✼1 0 1 ✼2 0 0 1 ----------------------------------------------------------------- 0 0 0 0 0 0 0 0 0 --------- ± ± ± ± ± 8 VDD 1024 A/D conversion result ------------- ✼1 ✼2 ✼3 ------------- ----- ✼8 ✼9 ✼A 2 ✼2: 2nd comparison result ✼8: 8th comparison result ✼A: 10th comparison result Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-49 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (7) A/D conversion timing chart Figure 34 shows the A/D conversion timing chart. ADST instruction 62 machine cycles A/D conversion completion flag (ADF) DAC operation signal Fig. 34 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P30/AIN4 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. ➀ Select the AIN4 pin function with the bit 0 of the register Q3. Select the A IN4 p in function and A/D conversion mode with the register Q1 (refer to Figure 35). ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). (Bit 3) (Bit 0) ✕ ✕ ✕ 1 A/D control register Q2 A IN4 p in function selected (Bit 3) (Bit 0) 0 1 0 0 A/D control register Q1 A IN4 p in selected A/D conversion mode ✕ : Set an arbitrary value. Fig. 35 Setting registers Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-50 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (9) Operation at comparator mode The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to “1.” Below, the operation at comparator mode is described. (12) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (4 µs at f(XIN) = 6.0 MHz in high-speed through mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” (10) Comparator register In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 ✕n (13) Notes for the use of A/D conversion • TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” • Operation mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag. n: The value of register AD (n = 0 to 255) (11) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal Comparator operation completed. (The value of ADF is determined) Fig. 36 Comparator operation timing chart → Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-51 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (14) Definition of A/D converter accuracy The A/D conversion accuracy is defined below (refer to Figure 37). • Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.” ➁ Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.” ➂ Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. ➃ Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. • Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022) • 1LSB at relative accuracy → VFST–V0T (V) 1022 VDD 1024 • 1LSB at absolute accuracy → (V) Output data 1023 1022 Full-scale transition voltage (VFST) Differential non-linearity error = b–a [LSB] a Linearity error = c [LSB] a b a n+1 n Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1–Vn c: Difference between ideal Vn and actual Vn Ideal line of A/D conversion between V0–V1022 1 0 V0 V1 Zero transition voltage (V0T) Vn Vn+1 V1022 Analog voltage VDD Fig. 37 Definition of A/D conversion accuracy Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-52 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS SERIAL I/O The 4524 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; • serial I/O register SI • serial I/O control register J1 • serial I/O transmit/receive completion flag (SIOF) • serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1. Table 14 Serial I/O pins Pin D6/SCK D5/SOUT D4/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN) Note: Even when the SCK, S OUT, SIN pin functions are used, the input of D6, D5, D4 are valid. 1/8 1/4 INSTCK SCK 1/2 J13J12 00 01 10 11 Synchronous circuit Serial I/O counter (3) SIOF Serial I/O interrupt D6/SCK Q S R SST instruction Internal reset signal D5/SOUT SOUT D4/SIN SIN MSB Serial I/O register (8) LSB TABSI J11 J10 TSIAB TABSI Register B (4) Register A (4) Fig. 38 Serial I/O structure Table 15 Serial I/O control register Serial I/O control register J1 at reset : 00002 at power down : state retained R/W TAJ1/TJ1A J13 J12 J11 J10 J13 J12 Synchronous clock 0 Instruction clock (INSTCK) divided by 8 0 Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (SCK input) 1 J11 J10 Port function 0 D6, D5, D4 selected/SCK, SOUT, SIN not selected 0 Serial I/O port function selection bits 1 SCK, SOUT, D4 selected/D6, D5, SIN not selected 0 0 SCK, D5, SIN selected/D6, SOUT, D4 not selected 1 1 SCK, SOUT, SIN selected/D6, D5, D4 not selected 1 Note: “R” represents read enabled, and “W” represents write enabled. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-53 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS At transmit (D7–D0: transfer data) SIN pin At receive SOUT pin Serial I/O register (SI) D7 D6 D5 D4 D3 D2 D1 D0 SOUT pin SIN pin Serial I/O register (SI) * ** ** ** * Transfer data set D7 D6 D5 D4 D3 D2 D1 D0 * ** ** ** * D0 *D 7 D6 D5 D4 D3 D2 D1 Transfer start ** ** ** * ****** * *D 7 D6 D5 D4 D3 D2 D1 D0 * ** ** ** * Fig. 39 Serial I/O register state when transfer Transfer complete D7 D6 D5 D4 D3 D2 D1 D0 (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, do not select the SCK pin. (3) Serial I/O start instruction (SST) When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial I/O transmission/reception is started. (4) Serial I/O control register J1 Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and D4/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. (2) Serial I/O transmit/receive completion flag (SIOF) Serial I/O transmit/receive completion flag (SIOF) is set to “1” when serial data transmit or receive operation completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-54 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (5) How to use serial I/O Figure 40 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the Master (clock control) wiring between each pin with a resistor. Figure 40 shows the data transfer timing and Table 16 shows the data transfer sequence. Slave (external clock) D3 SCK SOUT SIN SRDY signal D3 SCK SIN SOUT (Bit 3) 0 0 1 (Bit 0) 1 (Bit 3) Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN Instruction clock/8 selected as synchronous clock (Bit 0) 1 1 1 Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN External clock selected as synchronous clock 1 (Bit 3) 0 ✕ ✕ (Bit 0) ✕ Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction valid) (Bit 3) 0 ✕ ✕ (Bit 0) ✕ Interrupt control register V2 Serial I/O interrupt enable bit (SNZSI instruction valid) ✕: Set an arbitrary value. Fig. 40 Serial I/O connection example Master SOUT SIN SST instruction M7’ S7 ’ M0 S0 M1 S1 M2 S2 M3 S3 M4 S4 M5 S5 M6 S6 M7 S7 SCK Slave SST instruction SRDY signal SOUT SI N S7 ’ M7’ S0 M0 S1 M1 S2 M2 S3 M3 S4 M4 S5 M5 S6 M6 S7 M7 M0–M7: Contents of master serial I/O register S0–S7: Contents of slave serial I/O register Rising of SCK: Serial input Falling of SCK: Serial output Fig. 41 Timing of serial I/O data transfer Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-55 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS Table 16 Processing sequence of data transfer from master to slave Master (transmission) [Initial setting] • Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 40. TJ1A and TV2A instructions • S etting the port received the reception enable signal (SRDY) to the input mode. (Port D3 is used in this example) SD instruction * [Transmission enable state] • Storing transmission data to serial I/O register SI. TSIAB instruction [Initial setting] • Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 40. TJ1A and TV2A instructions • Setting the port transmitted the reception enable signal (SRDY) and outputting “H” level (reception impossible). (Port D3 is used in this example) SD instruction *[Reception enable state] • The SIOF flag is cleared to “0.” SST instruction • “L” level (reception possible) is output from port D3. RD instruction [Transmission] •Check port D3 is “L” level. SZD instruction •Serial transfer starts. SST instruction •Check transmission completes. SNZSI instruction •Wait (timing when continuously transferring) • Check reception completes. SNZSI instruction • “H” level is output from port D3. SD instruction [Data processing] 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transmit/receive is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to “1” when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to “H.” [Reception] Slave (reception) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-56 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS LCD FUNCTION The 4524 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply input pins (VLC1 – V LC3 ) and data are set in timer control register (W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (VLC1–VLC3) are also used as pins SEG0–SEG2. When SEG0–SEG2. The internal power (VDD) is used for the LCD power. (2) LCD clock control The LCD clock is determined by the timer LC count source selection bit (W6 2 ), timer LC control bit (W6 3 ), and timer LC. Accordingly, the LCD clock frequency (F) is obtained by the following formula. Numbers ( ➀ t o ➂ ) shown below the formula correspond to numbers in Figure 42, respectively. • W hen using the prescaler output (ORCLK) as timer LC count source (W62=“1”) F = ORCLK ✕ ➀ 1 ✕ LC + 1 ➁ 1 2 ➂ (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. • 1/2 duty, 1/2 bias • 1/3 duty, 1/3 bias • 1/4 duty, 1/3 bias Table 17 Duty and maximum number of displayed pixels Duty 1/2 1/3 1/4 Maximum number of displayed pixels Used COM pins 40 segments COM0, COM1 (Note) 60 segments COM0–COM2 (Note) 80 segments COM0–COM3 • When using the bit 4 of timer 5 as timer LC count source (W62=“0”) F = T54 ➀ [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = F n n F (Hz) 1 ✕ LC + 1 ➁ ✕ 1 2 ➂ Frame period = (s) F: LCD clock frequency 1/n: Duty Note: Leave unused COM pins open. (Note) W63 W62 T54 ORCLK 0 1 ➀ Reload register RLC (TLCA) (TLCA) (4) 0 1 ➁ Timer LC ➂ (4) 1/2 LCD clock Register A Note: Count source is stopped by setting “0” to this bit. Fig. 42 LCD clock control circuit structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-57 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS VLC3/SEG0 COM3 COM1 COM2 COM0 VLC1/SEG2 SEG3 to SEG19 VLC2/ SEG1 r r r r SEG0 to SEG2 output ......... Multiplexer r r Control signal Common driver Bias control Segment driver ... Segment driver Selector ... Selector ... RAM Decoder 1/2,1/3,1/4 counter LCD clock (from timer block) RAM LCD ON/OFF control L13 L12 L11 L10 L23 L22 L21 L20 Register A Fig. 43 LCD controller/driver Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-58 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed. (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lV LC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level. Z X Y 8 9 10 11 12 13 14 15 COM Bits 1 3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2 12 1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 13 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 3 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3 2 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 3 SEG16 SEG17 SEG18 SEG19 14 2 1 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 0 SEG16 SEG17 SEG18 SEG19 COM3 COM2 COM1 COM0 Note: The area marked “ ” is not the LCD display RAM. Fig. 44 LCD RAM map Table 18 LCD control registers LCD control register L1 L13 L12 L11 LCD duty and bias selection bits L10 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1 L11 L10 0 0 0 1 1 0 1 1 at reset : 00002 2r ✕ 3, 2r ✕ 2 r ✕ 3, r ✕ 2 Off On Duty Not available 1/2 1/3 1/4 1/2 1/3 1/3 W TL2A Bias at power down : state retained R/W TAL1/TL1A LCD control register L2 L23 L22 L21 L20 VLC3/SEG0 pin function switch bit (Note 3) VLC2/SEG1 pin function switch bit (Note 4) VLC1/SEG2 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1 at reset : 11112 at power down : state retained SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG 2 pins are selected. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-59 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM. 1 flame (2/F) M (1, 14, 8) COM0 COM1 1/F COM1 COM0 SEG16 COM1 SEG16 COM0 SEG16 Voltage level 0 (bit 0) 1 X X (bit 3) VLC3 VLC1=VLC2 VSS SEG16 VLC3 VLC1=VLC2 VSS ON 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM. OFF 1 flame (3/F) M (1, 14, 8) COM0 COM1 COM2 1/F COM2 Voltage level 1 (bit 0) 0 1 X (bit 3) COM1 VLC3 VLC2 VLC1 VSS SEG16 COM0 VLC3 VLC2 VLC1 VSS SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16 ON OFF ON 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM. 1 flame (4/F) M (1, 14, 8) COM0 COM1 COM2 COM3 SEG16 COM1 1 /F COM3 Voltage level 0 (bit 0) 1 0 1 (bit 3) COM2 VLC3 VLC2 VLC1 VSS COM0 VLC3 VLC2 VLC1 VSS F : LCD clock frequency SEG16 COM3 SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16 X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.) ON OFF ON OFF Fig. 45 LCD controller/driver structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-60 HARDWARE 4524 Group F UNCTION BLOCK OPERATIONS (5) LCD power supply circuit Select the LCD power circuit suitable for the LCD panel. The LCD control circuit structure is fixed by the following setting. ➀ Set the control of internal dividing resistor by bit 0 of register L2. ➁ Select the internal dividing resistor by bit 3 of register L1. ➂ Select the bias condition by bits 0 and 1 of register L1. • Internal dividing resistor The 4524 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to “0”, the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to “0”, the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows; • L13 = “0”, 1/3 bias used: 2r ✕ 3 = 6r • L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r • L13 = “1”, 1/3 bias used: r ✕ 3 = 3r • L13 = “1”, 1/2 bias used: r ✕ 2 = 2r • VLC3/SEG0 pin The selection of VLC3/SEG0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of V LC3 < VDD to the pin externally. When the SEG0 pin function is selected, VLC3 is connected to VDD internally. • VLC2/SEG1, VLC1/SEG2 pin The selection of VLC2/SEG1 pin function is controlled with the bit 2 of register L2. The selection of VLC1/SEG2 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0