4556

4556 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0025-0302 Rev.3.02 2006.12.22 DESCRIPTION The 4556 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has one or two reload registers), a 16bit timer for clock count, interrupts, and oscillation circuit switch function. The various microcomputers in the 4556 Group include variations of the built-in memory size as shown in the table below. FEATURES q Minimum instruction execution time Mask ROM version .............................................................. 0.5 µs (at 6 MHz oscillation frequency, in high-speed through-mode) One Time PROM version ................................................... 0.68 µs (at 4.4 MHz oscillation frequency, in high-speed through-mode) q Supply voltage Mask ROM version ...................................................... 1.8 to 5.5 V One Time PROM version ............................................. 1.8 to 3.6 V (It depends on operation source clock, oscillation frequency and operation mode) q Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ................................. 8-bit timer with two reload registers Timer 3 .............................. 16-bit timer (fixed dividing frequency) q Interrupt ........................................................................ 4 sources q Key-on wakeup function pins ..................................................... 9 q LCD control circuit Segment output ........................................................................ 23 Common output .......................................................................... 4 q Voltage drop detection circuit (only H version) Reset occurrence .................................... Typ. 1.8 V (Ta = 25 °C) Reset release .......................................... Typ. 1.9 V (Ta = 25 °C) q Watchdog timer q Clock generating circuit Built-in clock (on-chip oscillator) Main clock (ceramic resonator/RC oscillation) Sub-clock (quartz-crystal oscillation) q LED drive directly enabled (port D) APPLICATION Remote control transmitter ROM (PROM) size (✕ 10 bits) 4096 words 8192 words 8192 words 4096 words 8192 words 8192 words RAM size (✕ 4 bits) 288 words 288 words 288 words 288 words 288 words 288 words Part number M34556M4-XXXFP M34556M8-XXXFP M34556G8FP (Note) M34556M4H-XXXFP M34556M8H-XXXFP M34556G8HFP (Note) Package 42P2R-A 42P2R-A 42P2R-A 42P2R-A 42P2R-A 42P2R-A ROM type Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Note: Shipped in blank. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 4556 Group page 1 of 142 4556 Group PIN CONFIGURATION XIN XOUT CNVSS XCIN/D6 XCOUT/D7 RESET COM0 COM1 COM2 COM3 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS VDD C/CNTR D5/INT D4 D3 D2 D1 D0 P13/SEG28 P12/SEG27 P11/SEG26 P10/SEG25 P03/SEG24 P02/SEG23 P01/SEG22 P00/SEG21 P23/SEG20 P22/SEG19 P21/SEG18 P20/SEG17 Pin configuration (top view) (4556 Group) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 2 of 142 M34556Mx-XXXFP M34556G8FP M34556MxH-XXXFP M34556G8HFP 4556 Group 4 4 4 Block diagram (4556 Group) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 I/O por t Port P0 Port P1 Port P2 Internal peripheral functions System clock generation circuit XIN -XOUT (Ceramic/RC) XCIN -XCOUT (Quartz-crystal) On-chip oscillator page 3 of 142 Timer Timer 1(8 bits) Timer 2(8 bits) Timer 3(16 bits) Watchdog timer (16 bits) Voltage drop detection circuit Memory ROM 4096, 8192 words ✕ 10 bits 4500 series CPU core ALU(4 bits) Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) LCD drive control circuit (Max.23 segments ✕ 4 common) RAM 288 words ✕ 4 bits LCD display RAM including 23 words ✕ 4 bits Segment output 4 Common output Port C 1 Port D 2 23 6 Note: The voltage drop detection circuit is equipped with only H version . 4556 Group PERFORMANCE OVERVIEW Parameter Number of basic M34556M4/M8/G8 instructions M34556M4H/M8H/G8H Minimum Mask ROM version instruction execution time One Time PROM version Memory sizes ROM M34556M4 Function 123 124 0.5 µs (at 6 MHz oscillation frequency, in through mode) 0.68 µs (at 4.4 MHz oscillation frequency, in through mode) 4096 words ✕ 10 bits M34556M4H 8192 words ✕ 10 bits M34556M8/G8 M34556M8H/G8H RAM M34556M4/M8/G8 288 words ✕ 4 bits (including LCD display RAM 23 words ✕ 4 bits) M34556M4H/M8H/G8H Input/Output D0–D5 Six independent I/O ports. I/O ports Input is examined by skip decision. The output structure can be switched by software. Port D5 is also used as INT pin. Two independent output ports. D 6, D 7 Output Ports D6 and D7 are also used as XCIN and XCOUT, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched P00–P03 I/O by software. Ports P00–P03 are also used as SEG21–SEG24, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched P10–P13 I/O by software. Ports P10–P13 are also used as SEG25–SEG28, respectively. 4-bit I/O port; The output structure can be switched by software. Ports P20–P23 are also used P20–P23 I/O as SEG17–SEG20, respectively. 1-bit output; Port C is also used as CNTR pin. C Output Timers 8-bit programmable timer with a reload register and has an event counter. Timer 1 8-bit programmable timer with two reload registers and PWM output function. Timer 2 16-bit timer, fixed dividing frequency (timer for clock count) Timer 3 4-bit timer with a reload register (for LCD clock) Timer LC 16-bit timer (fixed dividing frequency) (for watchdog) Watchdog timer LCD control Selective bias value 1/2, 1/3 bias circuit 2, 3, 4 duty Selective duty value 4 Common output 23 Segment output 2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (r = 80 kΩ, (Ta = 25 °C, Typical value)) Internal resistor for power supply Interrupt 4 (one for external, three for timer ) Sources 1 level Nesting Subroutine nesting 8 levels Device structure CMOS silicon gate Package 42-pin plastic molded SSOP (42P2R-A) Operating temperature range –20 °C to 85 °C Supply 1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) Mask ROM version voltage One Time PROM version 1.8 to 3.6 V (It depends on operation source clock, oscillation frequency and operation mode) Power 2.2 mA (at room temperature, VDD = 5 V, f(XIN) = 6 MHz, f(X CIN) = stop, f(RING) = stop, Active mode f(STCK) = f(XIN)/1) (Mask ROM version) dissipation At clock operating mode 6 µA (at room temperature, VDD = 5 V, f(XCIN) = 32 kHz) (Typ.value) (Mask ROM version) 0.1 µA (at room temperature, VDD = 5 V, output transistor is cut-off state) At RAM back-up (Mask ROM version) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 4 of 142 4556 Group PIN DESCRIPTION Pin VDD VSS CNVSS RESET Name Power supply Ground CNVSS Reset input/output Input/Output — — — I/O Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins X IN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port D5 is also used as INT pin. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D6 and D7 are also used as XCIN pin and XCOUT pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P0 0–P03 are also used as SEG21–SEG24, respectively. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P1 0–P13 are also used as SEG25–SEG28, respectively. Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to “1” and select the N-channel open-drain. Ports P20–P23 are also used as SEG17–SEG20, respectively. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0– COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty. LCD segment output pins. SEG0–SEG2 pins are used as VLC3–VLC1 pins, respectively. SEG 17 – SEG 28 p ins are used as Ports P20 – P23, Ports P0 0 – P03 a nd Ports P10–P13, respectively. CNTR pin has the function to input the clock for the timer 1 event counter and to output the PWM signal generated by timer 2.CNTR pin is also used as Port C. INT pin accepts external interrupts. They have the key-on wakeup function which can be switched by software. INT pin is also used as Port D5. XIN XOUT XCIN XCOUT D 0– D 5 Main clock input Main clock output Sub-clock input Sub-clock output I/O port D Input is examined by skip decision. Output port D Input Output Input Output I/O D 6, D 7 Output P00–P03 I/O port P0 I/O P10–P13 I/O port P1 I/O P20–P23 I/O port P2 I/O Port C COM0– COM3 SEG0–SEG10 SEG17–SEG28 (Note) CNTR INT Output port C Common output Segment output Output Output Output Timer input/output Interrupt input I/O Input Note: SEG11 to SEG16 pins are not existed in the 4556 Group. MULTIFUNCTION Pin XCIN XCOUT P00 P01 P02 P03 P10 P11 P12 P13 Multifunction D6 D7 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Pin D6 D7 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Multifunction XCIN XCOUT P00 P01 P02 P03 P10 P11 P12 P13 Pin P20 P21 P22 P23 D5 C SEG0 SEG1 SEG2 Multifunction SEG17 SEG18 SEG19 SEG20 INT CNTR VLC3 VLC2 VLC1 Pin SEG17 SEG18 SEG19 SEG20 INT CNTR VLC3 VLC2 VLC1 Multifunction P20 P21 P22 P23 D5 C SEG0 SEG1 SEG2 Notes 1: Pins except above have just single function. 2: The input/output of D5 can be used even when INT is selected. The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used. 3: The port C “H” output function can be used even when CNTR (output) is selected. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 5 of 142 4556 Group DEFINITION OF CLOCK AND CYCLE q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. • Clock (f(XIN)) by the external ceramic resonator • Clock (f(XIN)) by the external RC oscillation • Clock (f(XIN)) by the external input • Clock (f(RING)) of the on-chip oscillator which is the internal oscillator • Clock (f(XCIN)) by the external quartz-crystal resonator Table Selection of system clock Register MR MR2 MR3 MR1 MR0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode Internal frequency divided by 8 mode Internal frequency divided by 4 mode Internal frequency divided by 2 mode Internal frequency through mode High-speed frequency divided by 8 mode High-speed frequency divided by 4 mode High-speed frequency divided by 2 mode High-speed through mode Low-speed frequency divided by 8 mode Low-speed frequency divided by 4 mode Low-speed frequency divided by 2 mode Low-speed through mode System clock f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) Note: The f(RING)/8 is selected after system is released from reset. PORT FUNCTION Port Port D Pin D0–D4, D5/INT Input Output I/O (6) Output (2) I/O (4) Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS 4 OP0A IAP0 I/O unit 1 Control Control instructions registers SD, RD FR1, FR2 SZD I1, K2 CLD RG FR0, PU0 K0 C1 FR0, PU1 K0, K1 C2 FR2 L3 W1 Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Output structure selection func tion (programmable) Remark Output structure selection function (programmable) XCIN/D6, XCOUT/D7 Port P0 P00/SEG21–P03/SEG24 Port P1 P10/SEG25–P13/SEG28 I/O (4) N-channel open-drain/ CMOS 4 OP1A IAP1 Port P2 P20/SEG17–P23/SEG20 Port C C/CNTR I/O (4) Output (1) N-channel open-drain/ CMOS CMOS 4 1 OP2A IAP2 RCP SCP Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 6 of 142 4556 Group CONNECTIONS OF UNUSED PINS Pin XIN XOUT XCIN/D6 XCOUT/D7 D 0– D 4 D5/INT C/CNTR P00/SEG21– P03/SEG24 Connection Connect to VSS. Open. Connect to VSS. Open. Open. Connect to VSS. Open. Connect to VSS. Open. Open. Connect to VSS. Usage condition RC oscillator is not selected P10/SEG25– P13/SEG28 Open. Connect to Vss. N-channel open-drain is selected for the output structure. INT pin input is disabled. N-channel open-drain is selected for the output structure. CNTR input is not selected for timer 1 count source. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. SEG0 pin is selected. SEG1 pin is selected. SEG2 pin is selected. P20/SEG17– P23/SEG20 COM0–COM3 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3–SEG10 (Note) Open. Connect to Vss. Open. Open. Open. Open. Open. Note: SEG11 to SEG16 pins are not existed in the 4556 Group. (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 7 of 142 4556 Group PORT BLOCK DIAGRAMS Skip decision Register Y Decoder SZD instruction (Note 3) FR1i (Note 1) S SD instruction RD instruction RQ D0—D3 (Note 2) (Note 1) CLD instruction Skip decision Register Y Decoder SZD instruction FR20 (Note 1) S SD instruction RD instruction RQ D4 (Note 1) (Note 2) CLD instruction Skip decision Register Y Decoder SZD instruction FR21 (Note 1) S SD instruction RD instruction RQ (Note 4) External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input External 0 interrupt circuit D5/INT (Note 2) (Note 1) CLD instruction Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. 4: As for details, refer to the external interrupt structure. Port block diagram (1) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 8 of 142 4556 Group Register Y Decoder CLD instruction S SD instruction RD instruction RQ RG2 1 0 (Note 1) XCIN/D6 (Note 2) (Note 1) Sub-clock input Register Y Decoder Quartz-crystal oscillation circuit RG2 (Note 1) S RG2 RQ 1 0 CLD instruction SD instruction RD instruction XCOUT/D7 (Note 2) (Note 1) Clock input for timer 1 event count Timer 1 underflow signal W41 D T R Q (Note 1) C/CNTR (Note 1) SQ R W10 W11 (Note 2) W12 PWMOD SCP instruction RCP instruction Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (2) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 9 of 142 4556 Group LCD power supply LCD control signal C1j 0 1 (Note 1) P00/SEG21, P01/SEG22 (Note 1) C1j key-on wakeup input K00 Edge detection circuit IAP0 instruction LCD power supply Register A Aj FR00 Pull-up transistor PU0j Aj OP0A instruction D TQ LCD power supply LCD control signal C1k 0 1 (Note 1) P02/SEG23, P03/SEG24 (Note 1) C1k key-on wakeup input K01 Edge detection circuit IAP0 instruction LCD power supply Register A Ak FR01 Pull-up transistor PU0K Ak OP0A instruction D TQ Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Port block diagram (3) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 10 of 142 4556 Group LCD power supply LCD control signal C2j 0 1 (Note 1) P10/SEG25, P11/SEG26 (Note 1) key-on wakeup input K11 0 1 Edge detection circuit Level detection circuit K10 0 K02 C2j LCD power supply 1 Register A Aj IAP1 instruction FR02 Pull-up transistor PU1j Aj OP1A instruction D TQ LCD power supply LCD control signal C2k 0 1 (Note 1) P12/SEG27, P13/SEG28 (Note 1) K13 key-on wakeup input 0 1 Edge detection circuit Level detection circuit K12 0 1 K03 C2k LCD power supply Register A Ak IAP1 instruction FR03 Pull-up transistor PU1k Ak OP1A instruction D TQ Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Port block diagram (4) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 11 of 142 4556 Group (Note 3) LCD power supply LCD control signal L3j 0 1 (Note 1) P20/SEG17, P21/SEG18 (Note 2) (Note 1) LCD power supply (Note 3) L3j (Note 3) Register A Aj FR22 IAP2 instruction Aj OP2A instruction D TQ (Note 4) LCD power supply LCD control signal L3k 0 1 (Note 1) P22/SEG19, P23/SEG20 (Note 2) (Note 1) LCD power supply (Note 4) L3k (Note 4) Register A Ak FR23 IAP2 instruction Ak OP2A instruction D TQ Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. Port block diagram (5) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 12 of 142 4556 Group LCD power supply LCD control signal (Note 1) SEG3–SEG10 (Note 1) LCD control signal LCD power supply LCD power supply LCD control signal (Note 1) COM0–COM3 (Note 2) (Note 2) (Note 1) LCD control signal LCD power supply LCD power supply LCD control signal LCD control signal Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (6) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 13 of 142 4556 Group LCD power supply LCD control signal L23 1 0 (Note 1) SEG0/VLC3 (Note 2) (Note 1) L23 LCD power supply LCD power supply (VLC3) LCD power supply LCD control signal L22 1 0 (Note 1) SEG1/VLC2 (Note 2) (Note 1) L22 LCD power supply (VLC2) LCD control signal LCD power supply L21 1 0 LCD power supply L21 (Note 1) SEG2/VLC1 (Note 2) (Note 1) L21 LCD power supply LCD power supply (VLC1) L13 L20 Reset signal L12 EPOF+POF2 instruction Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (7) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 14 of 142 4556 Group (Note 1) D5/INT (Note 1) I12 0 1 One-sided edge detection circuit I11 0 1 Timer 1 count start synchronization circuit input External 0 EXF0 interrupt Both edges detection circuit I13 SNZI0 instruction Skip decision K20 Level detection circuit Edge detection circuit K21 0 1 Key-on wakeup input • This symbol represents a parasitic diode on the port. Block diagram of external interrupt Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 15 of 142 4556 Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. (CY) (M(DP)) Addition (A) Fig. 1 AMC instruction execution example ALU (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the power down mode. Accordingly, set the initial value. A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction Register A (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Also, when the TABP p instruction is executed at UPTF flag = “1”, the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is “ 0 ” . When the TABP p instruction is executed at UPTF flag = “0”, the contents of register D remains unchanged. The UPTF flag is set to “1” with the SUPT instruction and cleared to “0” with the RUPT instruction. The initial value of UPTF flag is “0”. Register D is undefined after system is released from reset and returned from the power down mode. Accordingly, set the initial value. B3 B2 B1 B0 A3 A2 A1 A0 TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A TBA instruction Fig. 3 Registers A, B and register E TABP p instruction Specifying address ROM 8 4 0 p6 p 5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1DR0 A3 A2 A1 A0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) Immediate field value p The contents of The contents of register D register A High-order 2 bits Register D (3) * UPTF=1, high-order 1 bit of register D is “0”. UPTF=0, data is not transferred to register D. Fig. 4 TABP p instruction execution example Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 16 of 142 4556 Group (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from power down mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1 : NOP · · · RT (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. (PC) ← (SK0) (SP) ← 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 17 of 142 4556 Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H ( most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the power down mode. After system is returned from the power down mode, set these registers. Register Y (4) Specifying RAM digit Register X (4) Specifying RAM file Register Z (2) Specifying RAM file group Fig. 8 Data pointer (DP) structure Specifying bit position Set D3 D2 D1 D0 0 0 0 1 1 Port D output latch Register Y (4) Fig. 9 SD instruction execution example Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 18 of 142 4556 Group PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34556ED. Table 1 ROM size and pages Part number M34556M4 M34556M4H M34556M8 M34556M8H M34556G8 M34556G8H ROM (PROM) size (✕ 10 bits) 4096 words 8192 words Pages 32 (0 to 31) 64 (0 to 63) 9876543210 000016 007F16 008016 00FF16 010016 017F16 018016 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3 1FFF16 Page 63 A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. Fig. 10 ROM map of M34556M8/M8H/G8/G8H 9 008016 008216 008416 008616 008816 008A16 008C16 008E16 876543210 External 0 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address 00FF16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 19 of 142 4556 Group DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from power down mode). RAM includes the area for LCD. When writing “1” to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map. • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the power down mode, set these registers. Table 2 RAM size Part number M34556M4/M4H M34556M8/M8H M34556G8/G8H RAM size 288 words ✕ 4 bits (1152 bits) RAM 288 words ✕ 4 bits (1152 bits) Register Z Register X 0 12 0 1 3 ... 12 13 14 15 0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Register Y 0 8 16 1 9 17 2 10 18 3 11 19 4 12 20 5 13 21 6 14 22 7 15 23 24 25 26 27 28 Note: The numbers in the shaded area indicate the corresponding segment output pin numbers. Fig. 12 RAM map Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 20 of 142 4556 Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) Table 3 Interrupt sources Priority Interrupt name Activated condition level 1 External 0 interrupt Level change of INT pin 2 Timer 1 interrupt Timer 1 underflow 3 4 Timer 2 interrupt Timer 3 interrupt Timer 2 underflow Timer 3 underflow Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Request flag EXF0 T1F T2F T3F Skip instruction SNZ0 SNZT1 SNZT2 SNZT3 Enable bit V10 V12 V13 V20 (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. Table 5 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “ 1. ” E ach interrupt request flag is cleared to “0” when either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 21 of 142 4556 Group (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.” • Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). • Program counter (PC) ............................................................... Each interrupt address • Stack register (SK) The address of main routine to be .................................................................................................... executed when returning • Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 • Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Activated condition INT pin interrupt waveform input Request flag Enable bit (state retained) Enable flag EXF0 V10 Address 0 in page 1 Timer 1 underflow T1F V12 Address 4 in page 1 Main routine Interrupt service routine Interrupt occurs Timer 2 underflow Timer 3 underflow T2F V13 Address 6 in page 1 T3F V20 INTE Address 8 in page 1 Fig. 15 Interrupt system diagram • • • • EI R TI Interrupt is enabled : Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 22 of 142 4556 Group (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 • Interrupt control register V2 The timer 3 interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. at reset : 00002 at power down : 00002 R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A Interrupt control register V2 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) Note: “R” represents read enabled, and “W” represents write enabled. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 23 of 142 4556 Group (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V12, V13, V20), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). q When an interrupt request flag is set after its interrupt is enabled (Note 1) 1 machine cycle T1 System clock (STCK) T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 EI instruction execution cycle Interrupt enable flag (INTE) Interrupt enabled state Interrupt disabled state INT External interrupt EXF0 Interrupt activated condition is satisfied. Timer 1, Timer 2, Timer 3 interrupts T1F,T2F,T3F Retaining level of system clock for 4 periods or more is necessary. Flag cleared 2 to 3 machine cycles (Notes 1, 2) Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. The program starts from the interrupt address. Fig. 16 Interrupt sequence Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 24 of 142 4556 Group EXTERNAL INTERRUPTS The 4556 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin D5/INT Activated condition When the next waveform is input to D5/INT pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms Valid waveform selection bit I11 I12 (Note 1) D5/INT I12 Falling 0 1 Rising One-sided edge detection circuit I11 0 EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit 1 External 0 interrupt I13 Timer 1 count start synchronous circuit K21 0 Key-on wakeup 1 Skip decision (SNZI0 instruction) This symbol represents a parasitic diode on the port. Notes 1: 2: I12 (I22) = 0: “L” level detected I12 (I22) = 1: “H” level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Fig. 17 External interrupt circuit structure Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 25 of 142 4556 Group (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D5/INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V10) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. Table 8 External interrupt control register Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1 (2) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. at reset : 00002 at power down : state retained R/W TAI1/TI1A INT pin input disabled INT pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected I12 Interrupt valid waveform for INT pin/ return level selection bit (Note 2) I11 I10 INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of these bits (I12 , I13) are changed, the external interrupt request flag (EXF0) may be set. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 26 of 142 4556 Group (3) Notes on External 0 interrupts ➀ Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18 ➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂). ➂ Note on bit 2 of register I1 When the interrupt valid waveform of the D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20 ➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂). ••• ••• LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT pin input is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. • When the key-on wakeup function of INT pin is not used (register K20 = “0”), clear bits 2 and 3 of register I1 before system enters to the power down mode. (refer to Figure 19➀). ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3 ••• LA 0 TI1A DI EPOF POF2 ; (00✕✕2) ; Input of INT disabled ........................ ➀ ; power down mode ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2 Rev.3.02 Dec 22, 2006 REJ03B0025-0302 ••• page 27 of 142 ••• 4556 Group TIMERS The 4556 Group has the following timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). • Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. F F1 6 n : Counter initial value Count starts n Reload Reload The contents of counter 1st underflow 2nd underflow 0016 Time n+1 count Timer interrupt “1” “0” request flag An interrupt occurs or a skip instruction is executed. n+1 count Fig. 21 Auto-reload function The 4556 Group timer consists of the following circuits. • Prescaler : 8-bit programmable timer • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 16-bit fixed dividing frequency timer • Timer LC : 4-bit programmable timer • Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, and 3 have the interrupt function, respectively) Prescaler and timers 1, 2, 3 and LC can be controlled with the timer control registers PA, W1 to W4. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 28 of 142 4556 Group Table 9 Function related timers Circuit Prescaler Timer 1 Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT input) Count source • Instruction clock (INSTCK) • PWM output (PWMOUT) • Prescaler output (ORCLK) • Timer 3 underflow (T3UDF) • CNTR input Timer 2 8-bit programmable binary down counter (PWM output function) Timer 3 16-bit fixed dividing frequency • XIN input • Prescaler output (ORCLK) divided by 2 • XCIN input • ORCLK 8192 16384 32768 65536 Timer LC Watchdog timer 4-bit programmable binary down counter 16-bit fixed dividing frequency • Bit 4 of timer 3 • System clock (STCK) • Instruction clock (INSTCK) 1 to 16 65534 • LCD clock • System reset (count twice) • WDF flag decision W4 1 to 256 • Timer 1 count source • CNTR output • Timer 2 interrupt • Timer 1 count source • Timer 3 interrupt • Timer LC count source W3 W2 Frequency dividing ratio 1 to 256 1 to 256 Use of output signal • Timer 1, 2, and 3 count sources • CNTR output control • Timer 1 interrupt Control register PA W1 Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 29 of 142 4556 Group Division circuit Divided by 8 On-chip oscillator Ceramic resonance MR1, MR0 Multiplexer (CRCK) 00 01 10 Divided by 4 Divided by 2 MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) XIN RC oscillation XCIN Quartz-crystal oscillation PA0 Prescaler (8) ORCLK Reload register RPS (8) (TPSAB) (TABPS) I1 2 (TPSAB) (TPSAB) (TABPS) Register B Register A D5/INT I1 3 0 1 One-sided edge detection circuit I1 1 0 SQ 1 R I10 1 0 Both edges detection circuit I10 W13 T1UDF W11, W10 00 01 10 11 0 W12 1 W40 (TAB1) Timer 1 (8) Reload register R1 (8) (T1AB) (T1AB) (T1AB) (TAB1) T1F Timer 1 interrupt PWMOUT ORCLK T3UDF C/CNTR Register B Register A Timer 1 underflow signal (T1UDF) PWMOUT Port C output Q D T1UDF W41 W12 W10 W11 R T Register B Register A (T2HAB) T Q PWMOD W23 Reload register R2H (8) W20 XIN ORCLK 1 /2 0 1 W21 Reload control circuit Timer 2 (8) (T2R2L) W 22 1 R “H” interval expansion T2F 0 Timer 2 interrupt Reload register R2L (8) (T2AB) (TAB2) (T2AB) (T2AB) (TAB2) Register B Register A Data is set automatically from each reload register when timer underflows (auto-reload function). Fig. 22 Timer structure (1) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 30 of 142 4556 Group XCIN ORCLK W33 0 Timer 3 (16) 1 W32 1 - - 4 - - - - - - - - 13 14 15 16 W31, W30 11 10 01 00 T3F Timer 3 interrupt Timer 3 underflow signal (T3UDF) W 42 0 STCK 1 W43 Timer LC (4) Reload register RLC (4) (TLCA) (TLCA) 1/2 LCD clock Register A INTSNC Watchdog timer 1 - - - - - - - - - - - - - - 16 S Q WDF1 WRST instruction RESET signal (Note) DWDT instruction + WRST instruction R S Q WEF R D Q Watchdog reset signal T Notes: The WEF flag is set to “1” at system reset or RAM back-up mode. Data is set automatically from each reload register when timer underflows (auto-reload function). R RESET signal Fig. 23 Timer structure (2) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 31 of 142 4556 Group Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state retained) Operating R/W TAW1/TW1A at power down : 02 W TPAA Timer control register W1 W13 W12 W11 Timer 1 count source selection bits (Note 3) Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit 0 1 0 1 at reset : 00002 at power down : state retained W10 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating W11 W10 Count source 0 PWM signal (PWMOUT) 0 0 Prescaler output (ORCLK) 1 1 Timer 3 underflow signal (T3UDF) 0 1 CNTR input 1 R/W TAW2/TW2A Timer control register W2 W23 W22 W21 W20 CNTR pin output control bit PWM signal interrupt valid waveform/ return level selection bit Timer 2 control bit Timer 2 count soruce selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 CNTR pin output invalid CNTR pin output valid PWM signal “H” interval expansion function invalid PWM signal “H” interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK)/2 signal output R/W TAW3/TW3A Timer control register W3 W33 W32 W31 Timer 3 count value selection bits W30 Timer 3 count auto-stop circuit selection bit Timer 3 control bit 0 1 0 1 at reset : 00002 at power down : state retained XCIN input Prescaler output (ORCLK) Stop (Initial state) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts W31 W30 0 0 0 1 1 0 1 1 Timer control register W4 W43 W42 W41 W40 Timer LC control bit Timer LC count source selection bit CNTR output auto-control circuit selection bit CNTR pin input count edge selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W TAW4/TW4A Stop (state retained) Operating Bit 4 (T34) of timer 3 System clock (STCK) CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”). 3: Port C output is invalid when CNTR input is selected for the timer 1 count source. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 32 of 142 4556 Group (1) Timer control registers • Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. • Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. • Timer control register W2 Register W2 controls the CNTR output, the expansion of “H” interval of PWM output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. • Timer control register W3 Register W3 controls the count operation and count source of timer 3. Set the contents of this register through register A with the TW5A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. • Timer control register W4 Register W4 controls the operation and count source of timer LC, the selection of CNTR output auto-control circuit and the count edge of CNTR input. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.. (2) Prescaler (interrupt function) Prescaler is an 8-bit binary down counter with the prescaler reload register RPS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; ➀ set data in prescaler, and ➁ set the bit 0 of register PA to “1.” When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes “0”), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, and 3 count sources. (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1 ➁ set count source by bits 0 and 1 of register W1, and ➂ set the bit 2 of register W1 to “1.” When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to “1.” Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 33 of 142 4556 Group (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with two timer 2 reload registers (R2L, R2H). Data can be set simultaneously in timer 2 and the reload register R2L with the T2AB instruction. Data can be set in the reload register R2H with the T2HAB instruction. The contents of reload register R2L set with the T2AB instruction can be set to timer 2 again with the T2R2L instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. When executing the T2HAB instruction to set data to reload register R2H while timer 2 is operating, avoid a timing when timer 2 underflows. Timer 2 starts counting after the following process; ➀ set data in timer 2 ➁ set count source by bit 0 of register W2, and ➂ set the bit 1 of register W2 to “1.” When a value set in reload register R2L is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2L, and count continues (auto-reload function). When bit 3 of register W2 is set to “1”, timer 2 reloads data from reload register R2L and R2H alternately each underflow. Timer 2 generates the PWM signal (PWMOUT) of the “L” interval set as reload register R2L, and the “H” interval set as reload register R2H. The PWM signal (PWMOUT) is output from CNTR pin. When bit 2 of register W2 is set to “ 1 ” a t this time, the interval (PWM signal “H” interval) set to reload register R2H for the counter of timer 2 is extended for a half period of count source. In this case, when a value set in reload register R2H is n, timer 2 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set “1” or more to reload register R2H. When bit 1 of register W4 is set to “1”, the PWM signal output to CNTR pin is switched to valid/invalid each timer 1 underflow. However, when timer 1 is stopped (bit 2 of register W1 is cleared to “0”), this function is canceled. Even when bit 1 of a register W2 is cleared to “0” in the “H” interval of PWM signal, timer 2 does not stop until it next timer 2 underflow. When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a timing when timer 2 underflows. (5) Timer 3 (interrupt function) Timer 3 is a 16-bit binary down counter. Timer 3 starts counting after the following process; ➀ set count value by bits 0 and 1 of register W3, ➁ set count source by bit 3 of register W3, and ➂ set the bit 2 of register W3 to “1.” Once count is started, when timer 3 underflows (the set count value is counted), the timer 3 interrupt request flag (T3F) is set to “1,” and count continues. Bit 4 of timer 3 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W3 is cleared to “0”, timer 3 is initialized to “FFFF16” and count is stopped. Timer 3 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 3 underflow occurs at clock operating mode, system returns from the power down state. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register W3 to “1” till executing the POF instruction. (6) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; ➀ set data in timer LC, ➁ select the count source with the bit 2 of register W4, and ➂ set the bit 3 of register W4 to “1.” When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes “0”), new data is loaded from reload register RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 34 of 142 4556 Group (7) Timer input/output pin (C/CNTR pin) CNTR pin is used to input the timer 1 count source and output the PWM signal generated by timer 2. When the PWM signal is output from C/CNTR pin, set “0” to the output latch of port C. The selection of CNTR output signal can be controlled by bit 3 of register W2. When the CNTR input is selected for timer 1 count source, timer 1 counts the waveform of CNTR input selected by bit 0 of register W4. Also, when the CNTR input is selected, the output of port C is invalid (high-impedance state). (10) Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. (11) Precautions Note the following for the use of timers. • Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. • Timer count source Stop timer 1, 2, and LC counting to change its count source. • Reading the count value Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data. • Writing to the timer Stop timer 1, 2 or LC counting and then execute the data write instruction (T1AB, T2AB, TLCA) to write its data. • Writing to reload register R1, R2H When writing data to reload register R1 or reload regiser R2H while timer 1 or timer 2 is operating, avoid a timing when timer 1 or timer 2 underflows. • Timer 2 Avoid a timing when timer 2 underflows to stop timer 2 at PWM output function used. When “H” interval extension function of the PWM signal is set to be “valid”, set “1” or more to reload register R2H. • Timer 3 Stop timer 3 counting to change its count source. • Timer input/output pin Set the port C output latch to “0” to output the PWM signal from C/CNTR pin. (8) Timer interrupt request flags (T1F, T2F, T3F) Each timer interrupt request flag is set to “ 1 ” w hen each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. (9) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT pin input can be performed. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT pin. The valid waveform of INT pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 to “0” or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 35 of 142 4556 Group • Prescaler and Timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after Prescaler and Timer 1 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of Timer 1, Timer 1 operates synchronizing with the falling edge of CNTR input. (2) Count Source Count Source Selecting CNTR input falling edge Timer Value 3 2 1 0 3 2 1 0 3 2 Timer Underflow signal (3) (1) Timer Start (4) Fig. 24 Timer count start timing and count time when operation starts (Prescaler and Timer 1) • Timer 2 and Timer LC count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 2 and Timer LC operations start (1). Time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source operations after count starts. (2) Count Source Timer Value 3 2 1 0 3 2 1 0 3 Timer Underflow Signal (3) (1) Timer Start (4) Fig. 25 Timer count start timing and count time when operation starts (Timer 2 and Timer LC) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 36 of 142 4556 Group q CNTR output: invalid (W23 = “0”) Timer 2 count source 0316 (R2L) (R2L) (R2L) (R2L) (R2L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal (output invalid) Timer 2 start PWM signal “L” fixed q CNTR output: valid (W23 = “1”) PWM signal “H” interval extension function: invalid (W22 = “0”) Timer 2 count source Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal 3 clock Timer 2 start PWM period 7 clock 3 clock PWM period 7 clock 0316 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 q CNTR output: valid (W23 = “1”) PWM signal “H” interval extension function: valid (W22 = “1”) (Note) Timer 2 count source Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal Timer 2 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R2H. Fig. 26 Timer 2 operation (reload register R2L: “0316”, R2H: “0216”) Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 37 of 142 4556 Group CNTR output auto-control circuit by timer 1 is selected. q CNTR output: valid (W23 = “1”) CNTR output auto-control circuit selected (W41 = “1”) PWM signal Timer 1 underflow signal Timer 1 start CNTR output CNTR output start q CNTR output auto-control function PWM signal Timer 1 underflow signal Timer 1 start Register W41 ➀ ➁ Timer 1 stop ➂ CNTR output CNTR output start CNTR output stop ➀ ➁ ➂ When the CNTR output auto-control function is set to be invalid while the CNTR output is invalid, the CNTR output invalid state is retained. When the CNTR output auto-control function is set to be invalid while the CNTR output is valid, the CNTR output valid state is retained. When timer 1 is stopped, the CNTR output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR pin, set the output latch of port C to “0”. Fig. 27 CNTR output auto-control function by timer 1 Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 38 of 142 4556 Group qWaveform extension function of CNTR output “H” interval: Invalid (W22 = “0”), CNTR output: valid (W23 = “1”), Count source: XIN input selected (W20 = “0”), Reload register R2L: “0316” Reload register R2H: “0216” Timer 2 count start timing Machine cycle Mi Mi+1 Mi+2 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W21 Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal TW2A instruction execution cycle (W21) ← 1 0316 (R2L) 0216 0116 0016 0216 0116 0016 0316 0216 0116 (R2H) (R2L) Timer 2 count start timing Timer 2 count stop timing Machine cycle Mi Mi+1 Mi+2 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W21 Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal TW2A instruction execution cycle (W21) ← 0 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R2H) (R2L) 0216 (R2H) (Note 1) Timer 2 count stop timing Notes 1: In order to stop timer 2 at CNTR output valid (W23 = “1”), avoid a timing when timer 2 underflows. If these timings overlap, a hazard may occur in a CNTR output waveform. 2: At CNTR output valid, timer 2 stops after “H” interval of PWM signal set by reload register R2H is output. Fig. 28 Timer 2 count start/stop timing Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 39 of 142 4556 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “ 000016, ” t he next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “ 0 ” a nd the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. FFFF 1 6 Value of 16-bit timer (WDT) 000016 WDF1 flag ➁ ➁ 65534 count (Note) WDF2 flag ➃ RESET pin output ➀ Reset released ➂ WRST instruction executed (skip executed) ➄ System reset ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock. Fig. 29 Watchdog timer function Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 40 of 142 4556 Group When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 30). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down state (refer to Figure 31). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down, and stop the watchdog timer function. WRST ••• ; WDF1 flag cleared DI DWDT WRST ••• ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared Fig. 30 Program example to start/stop watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ↓ Oscillation stop Fig. 31 Program example to enter the mode when using the watchdog timer Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 41 of 142 ••• ••• ••• 4556 Group LCD FUNCTION The 4556 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply input pins (V LC1– V LC3) and data are set in timer control register (W4), timer LC, LCD control registers (L1, L2, L3, C1, C2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 23 segment signal output pins can be used to drive the LCD. By using these pins, up to 92 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (VLC1–VLC3) are also used as pins SEG 0–SEG 2. When SEG 0–SEG2 are selected, the internal power (VDD) is used for the LCD power. (2) LCD clock control The LCD clock is determined by the timer LC count source selection bit (W4 2 ), timer LC control bit (W4 3 ), and timer LC. Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers (➀ to ➂) shown below the formula correspond to numbers in Figure 32, respectively. • W hen using the prescaler output (ORCLK) as timer LC count source (W42=“1”) F = ORCLK ✕ ➀ 1 ✕ LC + 1 ➁ 1 2 ➂ (1) Duty and bias There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. • 1/2 duty, 1/2 bias • 1/3 duty, 1/3 bias • 1/4 duty, 1/3 bias Table 11 Duty and maximum number of displayed pixels Duty 1/2 1/3 1/4 Maximum number of displayed pixels Used COM pins 46 segments COM0, COM1 (Note) 69 segments COM0–COM2 (Note) 92 segments COM0–COM3 • When using the bit 4 of timer 3 as timer LC count source (W42=“0”) F = T34 ➀ [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = F n n F (Hz) 1 ✕ LC + 1 ➁ ✕ 1 2 ➂ Frame period = (s) F: LCD clock frequency 1/n: Duty Note: Leave unused COM pins open. (Note) W43 W42 T34 STCK 0 1 ➀ Reload register RLC ( TLCA ) ( TLCA ) (4 ) 0 1 ➁ Timer LC ➂ (4 ) 1/2 LCD clock Register A Note: Count source is stopped by setting “0” to this bit. Fig. 32 LCD clock control circuit structure Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 42 of 142 4556 Group SEG0/VLC3 COM3 COM1 COM2 COM0 SEG2/VLC1 SEG3 to SEG17 to SEG10 SEG28 SEG1 /VLC2 r r r r SEG0 to SEG2 output ......... Multiplexer r r Control signal Common driver Bias control Segment driver ... Segment driver Selector ... Selector ... RAM Decoder 1/2,1/3,1/4 counter LCD clock (from timer block) RAM LCD ON/ OFF control L13 L12 L11 L10 L23 L22 L21 L20 Register A Fig. 33 LCD controller/driver (3) LCD RAM RAM contains areas corresponding to the liquid crystal display. When “1” is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed. (4) LCD drive waveform When “1” is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lVLC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level. Z X Y 8 9 10 11 12 13 14 15 COM Bits 1 0 3 2 1 0 3 2 1 1 0 3 2 2 1 0 3 2 3 1 0 SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG24 SEG24 SEG24 SEG24 SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25 SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26 SEG3 SEG3 SEG3 SEG3 SEG4 SEG4 SEG4 SEG4 SEG5 SEG5 SEG5 SEG5 SEG19 SEG20 SEG21 SEG22 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG19 SEG27 SEG27 SEG27 SEG27 SEG20 SEG28 SEG28 SEG28 SEG28 SEG21 SEG22 SEG6 SEG6 SEG6 SEG6 SEG7 SEG7 SEG7 SEG7 SEG23 SEG23 SEG23 SEG23 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 Note: The area marked “ ” is not the LCD display RAM. Fig. 34 LCD RAM map Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 43 of 142 4556 Group Table 12 LCD control registers (1) LCD control register L1 L13 L12 L11 LCD duty and bias selection bits L10 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1 L11 L10 0 0 0 1 1 0 1 1 at reset : 00002 2r ✕ 3, 2r ✕ 2 r ✕ 3, r ✕ 2 Stop Operating Duty Not available 1/2 1/3 1/4 1/2 1/3 1/3 W TL2A Bias at power down : state retained R/W TAL1/TL1A LCD control register L2 L23 L22 L21 L20 SEG0/VLC3 pin function switch bit (Note 3) SEG1/VLC2 pin function switch bit (Note 4) SEG2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1 at reset : 00002 SEG0 at power down : state retained VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid LCD control register L3 L33 L32 L31 L30 P23/SEG20 pin function switch bit P22/SEG19 pin function switch bit P21/SEG18 pin function switch bit P20/SEG17 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG20 P23 SEG19 P22 SEG18 P21 SEG17 P20 at power down : state retained W TL3A Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG 2 pins are selected. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 44 of 142 4556 Group Table 12 LCD control registers (2) LCD control register C1 C13 C12 C11 C10 P03/SEG24 pin function switch bit P02/SEG23 pin function switch bit P01/SEG22 pin function switch bit P00/SEG21 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG24 P03 SEG23 P02 SEG22 P01 SEG21 P00 W TC2A at power down : state retained W TC1A LCD control register C2 C23 C22 C21 C20 P13/SEG28 pin function switch bit P12/SEG27 pin function switch bit P11/SEG26 pin function switch bit P10/SEG25 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG28 P13 SEG27 P12 SEG26 P11 SEG25 P10 at power down : state retained Note: “R” represents read enabled, and “W” represents write enabled. Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 45 of 142 4556 Group 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 9) in RAM. 1 flame (2/F) M (1, 2, 9) COM0 COM1 1/F COM1 Voltage level 0 (bit 0) 1 X X (bit 3) COM0 VLC3 VLC1=VLC2 VSS SEG17 SEG17 COM1 SEG17 COM0 SEG17 VLC3 VLC1=VLC2 VSS ON 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 9) in RAM. OFF 1 flame (3/F) M (1, 2, 9) COM0 COM1 COM2 1/F COM2 Voltage level 1 (bit 0) 0 1 X (bit 3) COM1 VLC3 VLC2 VLC1 VSS SEG17 COM0 VLC3 VLC2 VLC1 VSS SEG17 COM2 SEG17 COM1 SEG17 COM0 SEG17 ON OFF ON 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 9) in RAM. 1 flame (4/F) M (1, 2, 9) COM0 COM1 COM2 COM3 SEG17 COM1 1/F COM3 Voltage level 0 (bit 0) 1 0 1 (bit 3) COM2 VLC3 VLC2 VLC1 VSS COM0 VLC3 VLC2 VLC1 VSS F : LCD clock frequency SEG17 COM3 SEG17 COM2 SEG17 COM1 SEG17 COM0 SEG17 X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.) ON OFF ON OFF Fig. 35 LCD controller/driver structure Rev.3.02 Dec 22, 2006 REJ03B0025-0302 page 46 of 142 4556 Group (5) LCD power supply circuit Select the LCD power supply circuit suitable for the using LCD panel. The LCD power supply circuit is fixed by the followings; • The internal dividing resistor is controlled by bit 0 of register L2. • The internal dividing resistor is selected by bit 3 of register L1. • The bias condition is selected by bits 0 and 1 of register L1. q Internal dividing resistor The 4556 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to “0”, the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to “0”, the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows; • L13 = “0”, 1/3 bias used: 2r ✕ 3 = 6r • L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r • L13 = “1”, 1/3 bias used: r ✕ 3 = 3r • L13 = “1”, 1/2 bias used: r ✕ 2 = 2r q VLC3/SEG0 pin The selection of VLC3/SEG0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG0 pin function is selected, VLC3 is connected to VDD internally. q VLC2/SEG1, VLC1/SEG2 pin The selection of VLC2/SEG1 pin function is controlled with the bit 2 of register L2. The selection of VLC1/SEG2 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0