557MI-01LF

DATASHEET ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE Description Features The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package. • Supports PCI-ExpressTM HCSL Outputs • • • Using IDT’s patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal Level) differential outputs at 100 MHz clock frequency. LVDS signal levels can also be supported via an alternative termination scheme. • • • • • • • • 0.7 V current mode differential pair Supports LVDS Output Levels Packaged in 8-pin SOIC RoHS 5 (green) or RoHS 6 (green and lead free) compliant packaging Operating voltage of 3.3 V Low power consumption Input frequency of 25 MHz Short term jitter 100 ps (peak-to-peak) Output Enable via pin selection Industrial temperature range available For PCIe Gen2 applications, see the 5V41064 For PCIe Gen3 applications, see the 5V41234 Block Diagram VDD CLK Phase Lock Loop X1 25 MHz crystal /clock X2 Clock Buffer/ Crystal Oscillator Crystal Tuning Capacitors GND IDT® PCI-EXPRESS GEN1 CLOCK SOURCE CLK 1 OE RR(IREF) ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Pin Assignment OE 1 8 V DD X1 2 7 CL K X2 3 6 CL K GN D 4 5 I RE F 8 P i n ( 1 5 0 mi l ) S OI C Pin Descriptions Pin Number Pin Name Pin Type 1 OE Input Output Enable signal (H = outputs are enabled, L = outputs are disabled/tristated). Internal pull-up resistor. 2 X1 Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 3 X2 XO 4 GND Power 5 IREF Output A 475Ω precision resistor connected between this pin and ground establishes the external reference current. 6 CLK Output HCSL differential complementary clock output. 7 CLK Output HCSL differential clock output. 8 VDD Power IDT® PCI-EXPRESS GEN1 CLOCK SOURCE Pin Description Crystal Connection. Connect to a parallel mode crystal. Leave floating if clock input. Connect to ground. Connect to +3.3 V. 2 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Applications Information Output Structures External Components A minimum number of external components are required for proper operation. IREF =2.3 mA 6*IREF Decoupling Capacitors Decoupling capacitors of 0.01 μF should be connected between VDD and the ground plane (pin 4) as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into IDT pin. Crystal See Output Termination R R 475W Sections - Pages 3 ~ 5 A 25 MHz fundamental mode parallel resonant crystal with CL = 16 pF should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-01 to meet PCI Express specifications. Crystal Capacitors General PCB Layout Recommendations Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. CL= Crystal’s load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 2. No vias should be used between decoupling capacitor and VDD pin. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Current Source (Iref) Reference Resistor - RR If board target trace impedance (Z) is 50Ω, then RR = 475Ω (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-01.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Output Termination The PCI-Express differential clock outputs of the ICS557-01 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-01can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section IDT® PCI-EXPRESS GEN1 CLOCK SOURCE 3 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1,2 1,2 1,2 1,2 1,2 Notes Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Figure 1 1 Notes Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch Figure 2 2 Notes Figure 1: PCI-Express Device Routing L1 L2 L4 RS L1’ L4’ L2’ RS RT ICS557-01 Output Clock L3’ RT L3 PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 500 ps 0.52 V 0.175 V IDT® PCI-EXPRESS GEN1 CLOCK SOURCE tOF 0.52 V 0.175 V 4 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE LVDS Compatible Layout Guidelines Vdiff Vp-p 0.45v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 R2a = R2b = R2 Alternative T ermination for LVDS and other Common Differential Signals Vcm R1 R2 R3 R4 Note 1.08 33 150 100 100 0.6 33 78.7 137 100 0.6 33 78.7 none 100 ICS874003i-02 input compatible 1.2 33 174 140 100 Standard LVDS Figure: LVDS Device Routing Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps 1250 mV 1150 mV IDT® PCI-EXPRESS GEN1 CLOCK SOURCE tOF 1250 mV 1150 mV 5 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Ambient Operating Temperature (industrial) -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Supply Voltage Input High Voltage1 Input Low Voltage 1 2 Conditions Min. Typ. Max. Units V 3.135 3.465 VIH 2.0 VDD +0.3 V VIL VSS-0.3 0.8 V Input Leakage Current IIL 0 < Vin < VDD 5 μA Operating Supply Current IDD With 50Ω and 2 pF load 55 mA OE =Low 35 mA Input pin capacitance 7 pF IDDOE Input Capacitance CIN Output Capacitance COUT Pin Inductance LPIN Output Resistance Rout CLK outputs Pull-up Resistor RPUP OE -5 Output pin capacitance 6 pF 5 nH 3.0 kΩ 60 kΩ 1 Single edge is monotonic when transitioning through region. 2 Inputs with pull-ups/-downs are not included. IDT® PCI-EXPRESS GEN1 CLOCK SOURCE 6 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE AC Electrical Characteristics - CLK/CLK Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Input Frequency Typ. Max. 25 Output Frequency Units MHz 100 MHz Output High Voltage1,2 VOH 660 700 850 mV Voltage1,2 VOL -150 0 27 mV 250 350 550 mV 140 mV 80 ps Output Low Crossing Point Voltage1,2 Absolute Crossing Point Voltage1,2,4 Variation over all edges Jitter, Cycle-to-Cycle1,3 Rise Fall Time1,2 Time1,2 tOR From 0.175 V to 0.525 V 175 332 700 ps tOF From 0.525 V to 0.175 V 175 344 700 ps 125 ps 55 % Rise/Fall Time Variation1,2 Duty Cycle1,3 45 Output Enable Time5 All outputs 30 µs Output Disable Time5 All outputs 30 µs From power-up VDD=3.3 V 3.0 ms Stabilization Time 1 Test tSTABLE setup is RL=50 ohms with 2 pF, RR = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured 5 CLKOUT at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high. Thermal Characteristics (8-pin SOIC) Parameter Thermal Resistance Junction to Ambient Symbol θJA IDT® PCI-EXPRESS GEN1 CLOCK SOURCE Still air θJA θJA Thermal Resistance Junction to Case Conditions 1 m/s air flow 3 m/s air flow θJC 7 Min. Typ. Max. Units 150 ° C/W 140 ° C/W 120 ° C/W 40 ° C/W ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Marking Diagram (ICS557M-01LF) 8 Marking Diagram (ICS557MI-01LF) 5 8 557M01LF LOT YYWW 1 5 557MI01L LOT YYWW 4 1 4 Notes: 1. “LOT” is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “L” or “LF” designates Pb (lead) free packaging. 4. “I” denotes industrial temperature. 5. Bottom marking: (origin). Origin = country of origin if not USA. IDT® PCI-EXPRESS GEN1 CLOCK SOURCE 8 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 8 E Inches* H INDEX AREA e 1 2 D 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 a 0° 8° 0° 8° *For reference only. Controlling dimensions in mm. A h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 557M-01LF See Page 8 Tubes 8-pin SOIC 0 to +70° C 557M-01LFT Tape and Reel 8-pin SOIC 0 to +70° C 557MI-01LF Tubes 8-pin SOIC -40 to +85° C 557MI-01LFT Tape and Reel 8-pin SOIC -40 to +85° C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® PCI-EXPRESS GEN1 CLOCK SOURCE 9 ICS557-01 REV P 072512 ICS557-01 PCI-EXPRESS GEN1 CLOCK SOURCE PCIE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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