5L2503-000NVGI

MicroClock Programmable Clock Generator 5L2503 Datasheet Description Features The 5L2503 MicroClock programmable clock generator is intended for low-power, consumer, wearable and smart devices. ▪ Configurable OE1 pin function as OE, PPS or DFC control function ▪ Proactive Power Saving (PPS) features save power during the end device power down mode ▪ Dynamic Frequency Control (DFC) feature allows programming up to 4 difference frequencies switch dynamically ▪ Spread spectrum clock support to lower system EMI ▪ I2C Interface The 5L2503 device is a 3 PLL architecture design. Each PLL is individually programmable, allowing up to 3 unique frequency outputs. The 5L2503 has built-in unique features such as Proactive Power Saving (PPS) to deliver better system level power management. An internal OTP memory allows the user to store the configuration in the device without programming after power-up, and then can be reprogrammed again through the I2C interface. Output Features The device has programmable VCO and PLL source selection allowing the user to do power-performance optimization based on the application requirements. A low-power 32.768kHz clock is supported with only less than 2μA current consumption for system RTC reference clock needs. ▪ 3 LVCMOS outputs: 1MHz–125MHz ▪ Low Power 32.768kHz clock supported ▪ Wireless clock crystal integration and fan out directly Key Specifications Typical Applications ▪ ▪ ▪ ▪ ▪ 2μA operation for RTC clock 32.768kHz output ▪ 2.5 × 2.5 mm 12-DFN small form factor package SmartDevice Handheld Wearable applications Consumer application crystal replacements Block Diagram VDD1_8 VSS Power Monitor OE1 POR PLL1 XOUT OUT1 OSC CLKIN/ XIN Mux & Divider PLL2 Calibration OUT2 VDDO VSS PLL3 OUT3 32.768K DCO SEL_DFC/ SCL_DFC1/OE3 SDA_DFC0/OE2 I2C Engine Overshoot Reduction (ORT) OTP memory (1 configuration ) ©2017 Integrated Device Technology, Inc. Dynamic Frequency Control Logic (DFC) Proactive Power Saving Logic (PPS) 1 October 24, 2017 5L2503 Datasheet Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View SDA_DFC0/OE2 1 12 VSS SEL_DFC/SCL_DFC1/OE3 2 11 OUT3 VSS 3 10 VDDO XOUT 4 9 OUT2 XIN 5 8 OE1 VDD1_8 6 7 OUT1 2.5 × 2.5 mm 12-DFN Pin Descriptions Table 1. Pin Descriptions Number Name Type 1 SDA_DFC0/OE2 I/O 2 SEL_DFC/SCL_DFC1/ OE3 Input I2C clock pin; can be DFC1 function by OTP programming selected by SEL_DFC at power-on default. Output enable pin for OUT3. 3 VSS Power Ground pin. 4 XOUT I/O 5 XIN Input Crystal oscillator interface input or clock input pin (CLKIN). 6 VDD1_8 Power 1.8V power rail. 7 OUT1 Output 1.8V LVCMOS clock output. 8 OE1 Input 9 OUT2 Output 1.8V LVCMOS clock output. 10 VDDO Power 1.8V output clock power supply pin; supports OUT2/3. 11 OUT3 Output 1.8V LVCMOS clock output. 12 VSS Power Ground pin. EPAD Power Connect to ground pad. ©2017 Integrated Device Technology, Inc. Description I2C data pin; can be DFC0 function by OTP programming or selected by SEL_DFC at power-on default. Output enable pin for OUT2. Crystal oscillator interface output. Output enable control 1. 2 October 24, 2017 5L2503 Datasheet Power Group Table 2. Power Group Power Supply SE DIV MUX OUT2/OUT3 VDDO VDD1_8 OUT1 PLL DCO XTAL V V V V V Output Source Selection Register Settings Table 3. OUT3 Source OUT3 Source B35b7 B35b6 Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1 B35b5 B35b4 Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1 B35b3 B35b2 Divider 3 (DIV3) 0 0 Divider 5 (DIV5) 0 1 Divider 1 (DIV1) 1 0 32.768kHz DCO 1 1 B35b1 B35b0 PLL1 0 0 DIV4 seed 1 X ©2017 Integrated Device Technology, Inc. 3 Table 4. OUT2 Source OUT2 Source Table 5. OUT1 Source OUT1 source Table 6. DIV1 Source DIV1 source October 24, 2017 5L2503 Datasheet Device Features and Functions DFC – Dynamic Frequency Control ▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2. ▪ ORT (overshoot reduction) function will be applied automatically during the VCO frequency change. ▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection. Figure 2. DFC Function Block Diagram M divider PLL2 OUT DIV Selector 00 N divider 01 N divider 10 N divider 11 N divider DFC1:0 OTP/I2C Table 7. DFC Function Priority DFC Mode OE Pin DFC_EN bit (W32[4]) OE1_fun_sel I2C Pins SCL_DFC1 SDA_DFC0 DFC[1:0] Notes Off OE In * 0 00 or 01 or 10 * Active (SCL = 1 at POR) SCL input SDA I/O Not applicable DFC disable On DFC0 In 1 11 Active SCL input SDA I/O DFC0 = OE One pin DFC via OE1 On OE In * 1 00 or 01 or 10 * Inactive (SCL= 0 at POR) DFC1 DFC0 DFC1 = SCL_DFC1 I2C pin as DFC control pins On OE In * 1 00 or 01 or 10 * Active (SCL = 1 at POR) SCL input SDA I/O W30[1:0] I2C control DFC mode * See OE Pin Function table. DFC Function Programming ▪ Register B63b3:2 select DFC00–DFC11 configuration. ▪ Byte16–19 are the register for PLL2 VCO setting. Based on B63b3:2 configuration selection, the data write to B16–19 will be stored in selected configuration OTP memory. ▪ Refer to DFC Function Priority table; select proper control pin(s) to activate DFC function. ▪ Note the DFC function can also be controlled by I2C access. ©2017 Integrated Device Technology, Inc. 4 October 24, 2017 5L2503 Datasheet PPS – Proactive Power Saving Function PPS Proactive Power Saving is an IDT patented unique design for the clock generator that proactively detects end device power-down state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes < 5μA current. The system could save power when the device goes into power-down or sleep mode. The PPS function diagram is shown below. Figure 3. PPS Function Block Diagram PPS Control Logic I2C & Logic Power Down Control Low Power DCO Xtal Oscillator XOUT XIN PLL Xtal Oscillator Logic MHz / kHz Switching Figure 4. PPS Assertion/Deassertion Timing Chart 3rd cycle 2nd cycle 1st cycle PPS assertion MHz clock 32kHz clocks 2nd cycle 1st cycle PPS deassertion 32kHz clocks MHz clock PPS Function Programming ▪ Refer to OE_pin_function_table to have proper PPS function selected for OE pin(s); note that register default is set to Output Enable (OE) function for OE pins. ©2017 Integrated Device Technology, Inc. 5 October 24, 2017 5L2503 Datasheet Input Pin Function The input pins in 5L2503 have multiple functions. The OE1 pin can be configured as output enable control (OE) or chip power-down control (PD#) or Proactive Power Saving function (PPS). Furthermore, the OE1 pin can be configured as a single or two-pin Dynamic Frequency Control (DFC). SCL/SDA are also multiple function pins. The two pins can be configured as output enable control (OE), or I2C interface or Dynamic Frequency Control (DFC) functions by programming and hardware pin latch. Table 8. OE1 Pin Function Byte30 Function bit6 bit5 OUT1 output enable/disable 0 0 Global Power Down (PD#) 0 1 OUT1 Proactive Power Saving Input (OUT1 PPS) 1 0 DFC0 1 1 Table 9. SDA/SCL Function SEL_DFC (latched) Enable OE2/3 B36 DFC_EN B32 OE1 Funsel B30 Function of SCL/SDA 0 0 0 00, 01, 10 N/A 0 0 1 00, 01, 10 SCL = DFC1, SDA = DFC0 0 1 X 00, 01, 10 SCL = OE3, SDA = OE2 1 X X 00, 01, 10 SCL, SDA Spread Spectrum The 5L2503 supports spread spectrum clocks from PLL1. PLL1 has built-in analog spread spectrum; PLL2 and PLL3 use seed clock from PLL1. ORT – VCO Overshoot Reduction Technology The 5L2503 supports innovate the VCO overshoot reduction technology to prevent the output clock frequency spike when the device is change frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency change are under control instead of freerun to targeted frequency. PLL Features and Descriptions Table 10. Output Divider 1 Output Divider Bits Output Divider Bits 00 01 10 11 00 1 2 4 8 01 4 8 16 32 10 5 10 20 40 11 6 12 24 48 ©2017 Integrated Device Technology, Inc. 6 October 24, 2017 5L2503 Datasheet Table 11. Output Dividers 2, 3, and 5 Output Divider Bits Output Divider Bits 00 01 10 11 00 1 2 4 5 01 3 6 12 15 10 5 10 20 25 11 10 20 40 50 Table 12. Output Divider 4 Output Divider Bits Output Divider Bits 00 01 10 11 00 1 2 4 8 01 4 8 16 32 10 5 10 20 40 11 6 12 24 48 Output Clock Test Conditions LVCMOS Output Test Conditions 33ohm 50ohm 2 inches 2pF LVCMOS ©2017 Integrated Device Technology, Inc. 7 October 24, 2017 5L2503 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 5L2503 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 13: Absolute Maximum Ratings Item Rating Supply Voltage, VDD1_8, VDDOUTx 1.89V Inputs Other Inputs -0.5V to VDD1_8/VDDOUTx Outputs, VDDOUTx (LVCMOS) -0.5V to VDDOUTx + 0.5V Outputs, IO (SDA) 10mA Package Thermal Impedance, ΘJA 42°C/W (0 mps) Package Thermal Impedance, ΘJC 41.8°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C ESD Human Body Model 2000V Junction Temperature 125°C Recommended Operating Conditions Table 14: Recommended Operating Conditions Symbol Parameter Minimum Typical Maximum Units VDDOUTx Power supply voltage for supporting 1.8V output and all other outputs. 1.71 1.8 1.89 V Power supply voltage for core logic functions. 1.71 1.8 1.89 V Operating temperature, ambient. -40 85 °C VDD1_8 TA CLOAD_OUT tPU Maximum load capacitance (1.8V LVCMOS only). Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic). ©2017 Integrated Device Technology, Inc. 8 5 0.05 pF 3 ms October 24, 2017 5L2503 Datasheet Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Symbol Parameter Minimum Input Capacitance (OE, SDA, SCL) CIN Pull-down Resistor ROUT Typical Maximum Units 3 7 pF OE 150 LVCMOS Output Driver Impedance (VDDOUTx = 1.8V) 17 kΩ Recommended Crystal Characteristics Table 16: Crystal Characteristics Parameter Minimum Maximum Units 8 48 MHz -20 20 ppm Mode of Oscillation Typical Fundamental Frequency Frequency Tolerance Equivalent Series Resistance (ESR) 10 100 Ω Shunt Capacitance 2 7 pF 8 10 pF 100 μW Load Capacitance (CL) 6 Maximum Crystal Drive Level DC Electrical Characteristics Table 17: DC Electrical Characteristics Symbol IDD Parameter Operation Supply Current Conditions Minimum Typical Maximum Units VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 12MHz, OUT3 = 26MHz, OUT2 off, no load. 2.0 mA VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 12MHz, OUT3 = 26MHz, OUT2 off, with load. 3.5 mA VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 26MHz, OUT3 = 26MHz, OUT2 = 32kHz, no load. 1.8 mA VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 26MHz, OUT3 = 26MHz, OUT2 = 32kHz, with load. 3.8 mA μA IDDPD Power Down Current PD asserted with VDD1_8 and VDDO ON, I2C programming, 32k running. 390 IDDSUSPEND Power Suspend Current VDDOUT2 OFF and only VDDOUT1 and VDD1_8 ON, I2C programming, 32k running. 1.6 1 Single CMOS driver active. 2 OUT1–3 current measured with 0.5 inches transmission line and no load. ©2017 Integrated Device Technology, Inc. 9 2.0 μA October 24, 2017 5L2503 Datasheet DC Electrical Characteristics for 1.8V LVCMOS VDD = 1.8V ±5%, VDDOUTx = 1.8V ±5%, TA = -40°C to 85°C. Table 18: DC Electrical Characteristics for 1.8V LVCMOS Symbol Parameter Conditions Minimum Typical Maximum Units VDDOUTx V 0.25 × VDDOUTx V 3 μA VOH Output High Voltage IOH = -8mA. VOL Output Low Voltage IOL = 8mA. Output Leakage Current Tri-state outputs, VDDOUTx = 1.89V. VIH Input High Voltage Single-ended inputs – OE1, SDA, SCL. 0.65 × VDDOUTx VDDOUTx + 0.3 V VIL Input Low Voltage Single-ended inputs – OE1, SDA, SCL. GND - 0.3 0.35 × VDDOUTx V IIN Input Leakage Current OE1 -1 5 μA IOZDD 0.7 × VDDOUTx AC Electrical Characteristics VDD1_8 = 1.8V ±5%, VDDO = 1.8V ±5%, TA = -40°C to 85°C; spread spectrum = off. Table 19. AC Electrical Characteristics Symbol Parameter Conditions Minimum Typical Maximum Units Input frequency limit when using a crystal. 8 48 MHz Input Frequency Input frequency limit when using LVCMOS connected to XIN. 1 125 MHz fOUT Output Frequency Single-ended clock output limit (LVCMOS). 1 125 MHz t1 Output Duty Cycle LVCMOS clock < 120MHz. 45 55 % t2 Rise/Fall Time fIN 1 ©2017 Integrated Device Technology, Inc. Single-ended LVCMOS output clock rise and fall time, 20% to 80% of VDDO 1.8V. 10 1.0 ns October 24, 2017 5L2503 Datasheet Table 19. AC Electrical Characteristics (Cont.) Symbol Parameter Conditions Clock Jitter Cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, differential outputs (1.8V nominal output voltage). OUT1 = 25MHz. Minimum Typical Maximum Units 50 200 ps 50 200 ps 50 200 ps 20 ms OUT2 = 100MHz. OUT3 = 125MHz. t3 Clock Jitter Cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, differential outputs (1.8V nominal output voltage). OUT1 = 24MHz. OUT2 = 32.768kHz. OUT3 = 26MHz. Clock Jitter Cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, differential outputs (1.8V nominal output voltage). OUT1 = 32.768kHz. OUT2 = 26MHz. OUT3 = 26MHz. t5 2 Lock Time PLL lock time from power-up. t6 Lock Time 32.768kHz clock low-power, power-up time. 10 100 ms t6 3 Lock Time PLL lock time from shutdown mode. 0.1 2 ms 1 Practical lower frequency is determined by loop filter settings. 2 Includes loading the configuration bits from OTP to PLL registers. It does not include OTP programming/write time. 3 Actual PLL lock time depends on the loop configuration. ©2017 Integrated Device Technology, Inc. 11 October 24, 2017 5L2503 Datasheet I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Symbol Parameter VIH Input High Level VIL Input Low Level VHYS Conditions Input Leakage Current VOL Output Low Voltage Typical Maximum Units 0.7 × VDD1_8 V 0.3 × VDD1_8 Hysteresis of Inputs IIN Minimum V 0.05 × VDD1_8 V IOL = 3mA. ±1 μA 0.4 V Table 21. I2C Bus AC Characteristics Symbol FSCLK Parameter Conditions Minimum Serial Clock Frequency (SCL) Typical Maximum Units 100 400 kHz Bus Free-time between STOP and START 1.3 μs tSU:START Setup Time, START 0.6 μs tHD:START Hold Time, START 0.6 μs tSU:DATA Setup Time, Data Input (SDA) 100 μs tHD:DATA Hold Time, Data Input (SDA) 1 0 μs tOVD Output Data Valid from Clock 0.9 μs CB Capacitive Load for each Bus Line 400 pF tR Rise Time, Data and Clock (SDA, SCL) 20 + 0.1 × CB 300 ns tF Fall Time, Data and Clock (SDA, SCL) 20 + 0.1 × CB 300 ns tBUF tHIGH High Time, Clock (SCL) 0.6 μs tLOW Low Time, Clock (SCL) 1.3 μs Setup Time, STOP 0.6 μs tSU:STOP 1 A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications Symbol Parameter Description fOUT Output Frequency Output frequency range. fMOD Modulation Frequency Modulation frequency. Spread Value Amount of spread value (programmable) – down spread. Spread% Value Variation of spread range. fSPREAD % tolerance ©2017 Integrated Device Technology, Inc. 12 Minimum Typical 1 Maximum Units 125 MHz 30 to 63 kHz -0.5% to -2% %fOUT 15 % October 24, 2017 5L2503 Datasheet General I2C Serial Interface Information How to Write How to Read ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a stop bit Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T IDT (Slave/Receiver) starT bit Slave Address WR WRite Index Block Read Operation ACK Controller (Host) T starT bit Slave Address WR WRite Beginning Byte = N ACK Data Byte Count = X ACK IDT (Slave/Receiver) ACK Beginning Byte N Beginning Byte = N ACK X Byte O O O ACK RT O O O RD Repeat starT Slave Address ReaD Byte N + X - 1 ACK ACK P stoP bit Data Byte Count=X ACK Beginning Byte N O O O X Byte ACK O O O Byte N + X - 1 N P ©2017 Integrated Device Technology, Inc. 13 Not acknowledge stoP bit October 24, 2017 5L2503 Datasheet Byte 0: General Control Byte 00h Name Control Function Type 0 1 PWD Bit 7 OTP_Burned OTP memory programming indication R/W OTP memory non-programmed OTP memory programmed 0 Bit 6 I2C_addr[1] I2C address select bit 1 R/W Bit 5 I2C_addr[0] I2 R/W Bit 4 PLL1_SSEN Bit 3 Bit 2 PLL1 Spread Spectrum enable R/W disable 0 enable Reserved PLL3_refin_sel Bit 1 Bit 0 C address select bit 0 0 00: D0 / 01: D2 10: D4 / 11: D6 PLL3 source selection 0 R/W Xtal Seed (DIV2) Reserved OTP_protect 0 0 0 OTP memory protection R/W read/write write locked 0 Byte 1: Dash Code ID (optional) Byte 01h Name Control Function Type 0 1 PWD Bit 7 DashCode ID[7] Dash code ID R/W — — 0 Bit 6 DashCode ID[6] Dash code ID R/W — — 0 Bit 5 DashCode ID[5] Dash code ID R/W — — 0 Bit 4 DashCode ID[4] Dash code ID R/W — — 0 Bit 3 DashCode ID[3] Dash code ID R/W — — 0 Bit 2 DashCode ID[2] Dash code ID R/W — — 0 Bit 1 DashCode ID[1] Dash code ID R/W — — 0 Bit 0 DashCode ID[0] Dash code ID R/W — — 0 Control Function Type 0 1 PWD Byte 2: Crystal Cap Setting Byte 02h Name Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 1 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit 1 Reserved 0 Bit 0 Reserved 0 ©2017 Integrated Device Technology, Inc. 14 October 24, 2017 5L2503 Datasheet Byte 3: PLL3 M Divider Byte 03h Name Control Function Type 0 1 PWD Bit 7 PLL3_MDIV1 PLL3 source clock divider R/W disable M DIV1 bypadd divider (/1) 0 Bit 6 PLL3_MDIV2 PLL3 source clock divider R/W disable M DIV2 bypadd divider (/2) 0 Bit 5 PLL3 M_DIV[5] PLL3 reference integer divider R/W 0 Bit 4 PLL3 M_DIV[4] PLL3 reference integer divider R/W 1 Bit 3 PLL3 M_DIV[3] PLL3 reference integer divider R/W Bit 2 PLL3 M_DIV[2] PLL3 reference integer divider R/W Bit 1 PLL3 M_DIV[1] PLL3 reference integer divider R/W 1 Bit 0 PLL3 M_DIV[0] PLL3 reference integer divider R/W 0 1 3–64, default 26 0 Byte 4: PLL3 N Divider Byte 04h Name Control Function Type 0 1 Bit 7 PLL3 N_DIV[7] PLL3 VCO feedback integer divider bit7 R/W 1 Bit 6 PLL3 N_DIV[6] PLL3 VCO feedback integer divider bit6 R/W 1 Bit 5 PLL3 N_DIV[5] PLL3 VCO feedback integer divider bit5 R/W 1 Bit 4 PLL3 N_DIV[4] PLL3 VCO feedback integer divider bit4 R/W Bit 3 PLL3 N_DIV[3] PLL3 VCO feedback integer divider bit3 R/W Bit 2 PLL3 N_DIV[2] PLL3 VCO feedback integer divider bit2 R/W 0 Bit 1 PLL3 N_DIV[1] PLL3 VCO feedback integer divider bit1 R/W 0 Bit 0 PLL3 N_DIV[0] PLL3 VCO feedback integer divider bit0 R/W 0 12–2048, default VCO setting is 480MHz PWD 0 0 Byte 5: PLL3 Loop Filter Setting and N Divider 10:8 Byte 05h Name Control Function Type 0 1 PWD Bit 7 PLL3_R100K PLL3 Loop filter resister 100kohm R/W bypass plus 100kohm 0 Bit 6 PLL3_R50K PLL3 Loop filter resister 50kohm R/W bypass plus 50kohm 0 Bit 5 PLL3_R25K PLL3 Loop filter resister 25kohm R/W bypass plus 25kohm 0 Bit 4 PLL3_R12.5K PLL3 Loop filter resister 12.5kohm R/W bypass plus 12.5kohm 1 Bit 3 PLL3_R6K PLL3 Loop filter resister 6kohm R/W bypass only 6kohm applied 0 Bit 2 PLL3 N_DIV[10] PLL3 VCO feedback integer divider bit10 R/W Bit 1 PLL3 N_DIV[9] PLL3 VCO feedback integer divider bit9 R/W Bit 0 PLL3 N_DIV[8] PLL3 VCO feedback integer divider bit8 R/W ©2017 Integrated Device Technology, Inc. 15 0 12–2048, default VCO setting is 480MHz 0 1 October 24, 2017 5L2503 Datasheet Byte 6: PLL3 Charge Pump Control Byte 06h Name Control Function Type 0 1 PWD Bit 7 OUTDIV 3 Source Output divider 3 source clock selection R/W PLL2 PLL3 0 Bit 6 PLL3_CP_8X PLL3 charge pump control R/W — x8 1 Bit 5 PLL3_CP_4X PLL3 charge pump control R/W — x4 1 Bit 4 PLL3_CP_2X PLL3 charge pump control R/W — x2 0 Bit 3 PLL3_CP_1X PLL3 charge pump control R/W — x1 1 Bit 2 PLL3_CP_/24 PLL3 charge pump control R/W — /24 1 Bit 1 PLL3_CP_/3 PLL3 charge pump control R/W — /3 0 Bit 0 PLL3_SIREF PLL3 SiRef current selection R/W 10μA 20μA 0 Formula: (iRef (10μA) × (1 + SIREF) × (1 × 1X + 2 × 2X + 4 × 4X + 8 × 8X + 16 × 16X))/((24 × /24) + (3 × /3)) Byte 7: PLL1 Control and OUTDIV5 Divider Byte 07h Name Control Function Type 0 1 PWD Bit 7 PLL1_MDIV_Doubler PLL1 reference clock doubler R/W disable enable 0 Bit 6 PLL1_SIREF PLL1 SiRef current selection R/W 10.8μA 21.6μA 0 Bit 5 PLL1_EN_CH2 PLL1 output Channel 2 control R/W disable enable 1 Bit 4 PLL1_EN_3rdpole PLL1 3rd Pole control R/W disable enable 0 Bit 3 OUTDIV5[3] Output divider 5 control bit 3 R/W Bit 2 OUTDIV5[2] Output divider 5 control bit 2 R/W Bit 1 OUTDIV5[1] Output divider 5 control bit 1 R/W Bit 0 OUTDIV5[0] Output divider 5 control bit 0 R/W 0 DIV5[3:2] = 1,2,4,5; DIV5[1:0] = 1,3,5,10; Default Divider = 1 x 10 = 10 0 1 1 Byte 8: PLL1 M Divider Byte 08h Name Control Function Type 0 1 PWD Bit 7 PLL1_MDIV1 PLL3 VCO reference clock divider 1 R/W disable M DIV1 bypass divider (/1) 0 Bit 6 PLL1_MDIV2 PLL3 VCO reference clock divider 2 R/W disable M DIV2 bypass divider (/2) 0 Bit 5 PLL1 M_DIV[5] PLL1 reference clock divider control bit 5 R/W 0 Bit 4 PLL1 M_DIV[4] PLL1 reference clock divider control bit 4 R/W 1 Bit 3 PLL1 M_DIV[3] PLL1 reference clock divider control bit 3 R/W Bit 2 PLL1 M_DIV[2] PLL1 reference clock divider control bit 2 R/W Bit 1 PLL1 M_DIV[1] PLL1 reference clock divider control bit 1 R/W 1 Bit 0 PLL1 M_DIV[0] PLL1 reference clock divider control bit 0 R/W 0 ©2017 Integrated Device Technology, Inc. 16 3–64, default is 26 1 0 October 24, 2017 5L2503 Datasheet Byte 9: PLL1 VCO N Divider Byte 09h Name Control Function Type 0 1 PWD Bit 7 PLL1 N_DIV[7] PLL1 VCO feedback divider control bit 7 R/W 0 Bit 6 PLL1 N_DIV[6] PLL1 VCO feedback divider control bit 6 R/W 1 Bit 5 PLL1 N_DIV[5] PLL1 VCO feedback divider control bit 5 R/W 0 Bit 4 PLL1 N_DIV[4] PLL1 VCO feedback divider control bit 4 R/W Bit 3 PLL1 N_DIV[3] PLL1 VCO feedback divider control bit 3 R/W Bit 2 PLL1 N_DIV[2] PLL1 VCO feedback divider control bit 2 R/W 0 Bit 1 PLL1 N_DIV[1] PLL1 VCO feedback divider control bit 1 R/W 0 Bit 0 PLL1 N_DIV[0] PLL1 VCO feedback divider control bit 0 R/W 0 1 12–2048, default is 600 1 Byte 10: PLL Loop Filter and N Divider Byte 0Ah Name Control Function Type 0 1 PWD Bit 7 PLL1_R100K PLL1 Loop filter resister 100kohm R/W bypass plus 100kohm 1 Bit 6 PLL1_R50K PLL1 Loop filter resister 50kohm R/W bypass plus 50kohm 0 Bit 5 PLL1_R25K PLL1 Loop filter resister 25kohm R/W bypass plus 25kohm 1 Bit 4 PLL1_R12.5K PLL1 Loop filter resister 12.5kohm R/W bypass plus 12.5kohm 1 Bit 3 PLL1_R1.0K PLL1 Loop filter resister 1kohm R/W bypass only 1.0kohm applied 0 Bit 2 PLL1 N_DIV[10] PLL1 VCO feedback integer divider bit10 R/W Bit 1 PLL1 N_DIV[9] PLL1 VCO feedback integer divider bit9 R/W Bit 0 PLL1 N_DIV[8] PLL1 VCO feedback integer divider bit8 R/W 0 12–2048, default is 600 1 0 Byte 11: PLL1 Charge Pump Byte 0Bh Name Control Function Type 0 1 PWD Bit 7 PLL1_CP_32X PLL1 charge pump control R/W — x32 0 Bit 6 PLL1_CP_16X PLL1 charge pump control R/W — x16 0 Bit 5 PLL1_CP_8X PLL1 charge pump control R/W — x8 0 Bit 4 PLL1_CP_4X PLL1 charge pump control R/W — x4 0 Bit 3 PLL1_CP_2X PLL1 charge pump control R/W — x2 0 Bit 2 PLL1_CP_1X PLL1 charge pump control R/W — x1 1 Bit 1 PLL1_CP_/24 PLL1 charge pump control R/W — /24 1 Bit 0 PLL1_CP_/3 PLL1 charge pump control R/W — /3 0 ©2017 Integrated Device Technology, Inc. 17 October 24, 2017 5L2503 Datasheet Byte 12: PLL1 Spread Spectrum Control Byte 0Ch Name Control Function Type 0 1 PWD Bit 7 PLL1_SS_REFDIV23 PLL1 spread spectrum control - Ref divider 23 R/W — — 0 Bit 6 PLL1_SS_REFDIV[6] PLL1 spread spectrum control - Ref divider 6 R/W — — 0 Bit 5 PLL1_SS_REFDIV[5] PLL1 spread spectrum control - Ref divider 5 R/W — — 0 Bit 4 PLL1_SS_REFDIV[4] PLL1 spread spectrum control - Ref divider 4 R/W — — 0 Bit 3 PLL1_SS_REFDIV[3] PLL1 spread spectrum control - Ref divider 3 R/W — — 0 Bit 2 PLL1_SS_REFDIV[2] PLL1 spread spectrum control - Ref divider 2 R/W — — 0 Bit 1 PLL1_SS_REFDIV[1] PLL1 spread spectrum control - Ref divider 1 R/W — — 0 Bit 0 PLL1_SS_REFDIV[0] PLL1 spread spectrum control - Ref divider 0 R/W — — 0 Byte 13: PLL1 Spread Spectrum Control Byte 0Dh Name Control Function Type 0 1 PWD Bit 7 PLL1_SS_FBDIV[7] PLL1 spread spectrum - feedback divider 7 R/W — — 0 Bit 6 PLL1_SS_FBDIV[6] PLL1 spread spectrum - feedback divider 6 R/W — — 0 Bit 5 PLL1_SS_FBDIV[5] PLL1 spread spectrum - feedback divider 5 R/W — — 0 Bit 4 PLL1_SS_FBDIV[4] PLL1 spread spectrum - feedback divider 4 R/W — — 0 Bit 3 PLL1_SS_FBDIV[3] PLL1 spread spectrum - feedback divider 3 R/W — — 0 Bit 2 PLL1_SS_FBDIV[2] PLL1 spread spectrum - feedback divider 2 R/W — — 0 Bit 1 PLL1_SS_FBDIV[1] PLL1 spread spectrum - feedback divider 1 R/W — — 0 Bit 0 PLL1_SS_FBDIV[0] PLL1 spread spectrum - feedback divider 0 R/W — — 0 Byte 14: PLL1 Spread Spectrum Control Byte 0Eh Name Control Function Type 0 1 PWD Bit 7 PLL1_SS_FBDIV[15] PLL1 spread spectrum - feedback divider 15 R/W — — 0 Bit 6 PLL1_SS_FBDIV[14] PLL1 spread spectrum - feedback divider 14 R/W — — 0 Bit 5 PLL1_SS_FBDIV[13] PLL1 spread spectrum - feedback divider 13 R/W — — 0 Bit 4 PLL1_SS_FBDIV[12] PLL1 spread spectrum - feedback divider 12 R/W — — 0 Bit 3 PLL1_SS_FBDIV[11] PLL1 spread spectrum - feedback divider 11 R/W — — 0 Bit 2 PLL1_SS_FBDIV[10] PLL1 spread spectrum - feedback divider 10 R/W — — 0 Bit 1 PLL1_SS_FBDIV[09] PLL1 spread spectrum - feedback divider 9 R/W — — 0 Bit 0 PLL1_SS_FBDIV[08] PLL1 spread spectrum - feedback divider 8 R/W — — 0 ©2017 Integrated Device Technology, Inc. 18 October 24, 2017 5L2503 Datasheet Byte 15: Output Divider1 Control Byte 0Fh Name Control Function Type 0 1 PWD Bit 7 OUTDIV1[3] Output divider1 control bit 3 R/W Bit 6 OUTDIV1[2] Output divider1 control bit 2 R/W Bit 5 OUTDIV1[1] Output divider1 control bit 1 R/W Bit 4 OUTDIV1[0] Output divider1 control bit 0 R/W 0 Bit 3 OUTDIV2[3] Output divider2 control bit 3 R/W 0 Bit 2 OUTDIV2[2] Output divider2 control bit 2 R/W Bit 1 OUTDIV2[1] Output divider2 control bit 1 R/W Bit 0 OUTDIV2[0] Output divider2 control bit 0 R/W Control Function Type 0 DIV1[3:2] = 1,2,4,8; DIV1[1:0] = 1,4,5,6; Default Divider = 1 x 1 = 1 DIV2[3:2] = 1,2,4,5; DIV2[1:0] = 1,3,5,10; Default Divider = 1 x 10 = 10 0 0 0 1 1 Byte 16: PLL2 Integer Feedback Divide Byte 10h Name 0 1 PWD Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 PLL2_FB_INT[10] PLL2 feedback integer divider 10 R/W — — 0 Bit 1 PLL2_FB_INT[9] PLL2 feedback integer divider 9 R/W — — 0 Bit 0 PLL2_FB_INT[8] PLL2 feedback integer divider 8 R/W — — 0 Byte 17: PLL2 Integer Feedback Divider Byte 11h Name Control Function Type 0 1 PWD Bit 7 PLL2_FB_INT_DIV[7] PLL2 feedback integer divider 7 R/W — — 0 Bit 6 PLL2_FB_INT_DIV[6] PLL2 feedback integer divider 6 R/W — — 0 Bit 5 PLL2_FB_INT_DIV[5] PLL2 feedback integer divider 5 R/W — — 1 Bit 4 PLL2_FB_INT_DIV[4] PLL2 feedback integer divider 4 R/W — — 1 Bit 3 PLL2_FB_INT_DIV[3] PLL2 feedback integer divider 3 R/W — — 1 Bit 2 PLL2_FB_INT_DIV[2] PLL2 feedback integer divider 2 R/W — — 1 Bit 1 PLL2_FB_INT_DIV[1] PLL2 feedback integer divider 1 R/W — — 0 Bit 0 PLL2_FB_INT_DIV[0] PLL2 feedback integer divider 0 R/W — — 0 ©2017 Integrated Device Technology, Inc. 19 October 24, 2017 5L2503 Datasheet Byte 18: PLL2 Fractional Feedback Divider Byte 12h Name Control Function Type 0 1 PWD Bit 7 PLL2_FB_FRC_DIV[7] PLL2 feedback fractional divider 7 R/W — — 0 Bit 6 PLL2_FB_FRC_DIV[6] PLL2 feedback fractional divider 6 R/W — — 0 Bit 5 PLL2_FB_FRC_DIV[5] PLL2 feedback fractional divider 5 R/W — — 0 Bit 4 PLL2_FB_FRC_DIV[4] PLL2 feedback fractional divider 4 R/W — — 0 Bit 3 PLL2_FB_FRC_DIV[3] PLL2 feedback fractional divider 3 R/W — — 0 Bit 2 PLL2_FB_FRC_DIV[2] PLL2 feedback fractional divider 2 R/W — — 0 Bit 1 PLL2_FB_FRC_DIV[1] PLL2 feedback fractional divider 1 R/W — — 0 Bit 0 PLL2_FB_FRC_DIV[0] PLL2 feedback fractional divider 0 R/W — — 0 Byte 19: PLL2 Fractional Feedback Divider Byte 13h Name Control Function Type 0 1 PWD Bit 7 PLL2_FB_FRC_DIV[15] PLL2 feedback fractional divider 15 R/W — — 0 Bit 6 PLL2_FB_FRC_DIV[14] PLL2 feedback fractional divider 14 R/W — — 0 Bit 5 PLL2_FB_FRC_DIV[13] PLL2 feedback fractional divider 13 R/W — — 0 Bit 4 PLL2_FB_FRC_DIV[12] PLL2 feedback fractional divider 12 R/W — — 0 Bit 3 PLL2_FB_FRC_DIV[11] PLL2 feedback fractional divider 11 R/W — — 0 Bit 2 PLL2_FB_FRC_DIV[10] PLL2 feedback fractional divider 10 R/W — — 0 Bit 1 PLL2_FB_FRC_DIV[9] PLL2 feedback fractional divider 9 R/W — — 0 Bit 0 PLL2_FB_FRC_DIV[8] PLL2 feedback fractional divider 8 R/W — — 0 Byte 20: PLL2 Spread Spectrum Control Byte 14h Name Control Function Type 0 1 PWD Bit 7 PLL2_STEP[7] PLL2 spread step size control bit 7 R/W — — 0 Bit 6 PLL2_STEP[6] PLL2 spread step size control bit 6 R/W — — 0 Bit 5 PLL2_STEP[5] PLL2 spread step size control bit 5 R/W — — 0 Bit 4 PLL2_STEP[4] PLL2 spread step size control bit 4 R/W — — 0 Bit 3 PLL2_STEP[3] PLL2 spread step size control bit 3 R/W — — 0 Bit 2 PLL2_STEP[2] PLL2 spread step size control bit 2 R/W — — 0 Bit 1 PLL2_STEP[1] PLL2 spread step size control bit 1 R/W — — 0 Bit 0 PLL2_STEP[0] PLL2 spread step size control bit 0 R/W — — 0 ©2017 Integrated Device Technology, Inc. 20 October 24, 2017 5L2503 Datasheet Byte 21: PLL2 Spread Spectrum Control Byte 15h Name Control Function Type 0 1 PWD Bit 7 PLL2_STEP[15] PLL2 spread step size control bit 15 R/W — — 0 Bit 6 PLL2_STEP[14] PLL2 spread step size control bit 14 R/W — — 0 Bit 5 PLL2_STEP[13] PLL2 spread step size control bit 13 R/W — — 0 Bit 4 PLL2_STEP[12] PLL2 spread step size control bit 12 R/W — — 0 Bit 3 PLL2_STEP[11] PLL2 spread step size control bit 11 R/W — — 0 Bit 2 PLL2_STEP[10] PLL2 spread step size control bit 10 R/W — — 0 Bit 1 PLL2_STEP[9] PLL2 spread step size control bit 9 R/W — — 0 Bit 0 PLL2_STEP[8] PLL2 spread step size control bit 8 R/W — — 0 Type 0 1 PWD Byte 22: PLL2 Spread Spectrum Control Byte 16h Name Control Function Bit 7 PLL2_STEP_DELTA[7] PLL2 spread step size control delta bit 7 R/W — — 0 Bit 6 PLL2_STEP_DELTA[6] PLL2 spread step size control delta bit 6 R/W — — 0 Bit 5 PLL2_STEP_DELTA[5] PLL2 spread step size control delta bit 5 R/W — — 0 Bit 4 PLL2_STEP_DELTA[4] PLL2 spread step size control delta bit 4 R/W — — 0 Bit 3 PLL2_STEP_DELTA[3] PLL2 spread step size control delta bit 3 R/W — — 0 Bit 2 PLL2_STEP_DELTA[2] PLL2 spread step size control delta bit 2 R/W — — 0 Bit 1 PLL2_STEP_DELTA[1] PLL2 spread step size control delta bit 1 R/W — — 0 Bit 0 PLL2_STEP_DELTA[0] PLL2 spared step size control delta bit 0 R/W — — 0 Byte 23: PLL2 Period Control Byte 17h Name Control Function Type 0 1 PWD Bit 7 PLL2_PERIOD[7] PLL2 period control bit 7 R/W — — 0 Bit 6 PLL2_PERIOD[6] PLL2 period control bit 6 R/W — — 0 Bit 5 PLL2_PERIOD[5] PLL2 period control bit 5 R/W — — 0 Bit 4 PLL2_PERIOD[4] PLL2 period control bit 4 R/W — — 0 Bit 3 PLL2_PERIOD[3] PLL2 period control bit 3 R/W — — 0 Bit 2 PLL2_PERIOD[2] PLL2 period control bit 2 R/W — — 0 Bit 1 PLL2_PERIOD[1] PLL2 period control bit 1 R/W — — 0 Bit 0 PLL2_PERIOD[0] PLL2 period control bit 0 R/W — — 0 ©2017 Integrated Device Technology, Inc. 21 October 24, 2017 5L2503 Datasheet Byte 24: PLL2 Control Register Byte 18h Name Control Function Type 0 1 PWD Bit 7 PLL2_PERIOD[9] PLL2 period control bit 9 R/W — — 0 Bit 6 PLL2_PERIOD[8] PLL2 period control bit 8 R/W — — 0 Bit 5 PLL2_SSEN PLL2 spread spectrum enable R/W disable enable 0 Bit 4 PLL2_R100K PLL2 loop filter resister 100kohm — bypass plus 100kohm 0 Bit 3 PLL2_R50K PLL2 loop filter resister 50kohm — bypass plus 50kohm 1 Bit 2 PLL2_R25K PLL2 loop filter resister 25kohm — bypass plus 25kohm 1 Bit 1 PLL2_R12.5K PLL2 loop filter resister 12.5kohm — bypass plus 12.5kohm 1 Bit 0 PLL2_R6K PLL2 loop filter resister 6kohm — bypass only 6kohm applied 0 Byte 25: PLL2 Charge Pump Control Byte 19h Name Control Function Type 0 1 PWD Bit 7 PLL2_CP_16X PLL2 charge pump control R/W — x16 0 Bit 6 PLL2_CP_8X PLL2 charge pump control R/W — x8 0 Bit 5 PLL2_CP_4X PLL2 charge pump control R/W — x4 0 Bit 4 PLL2_CP_2X PLL2 charge pump control R/W — x2 1 Bit 3 PLL2_CP_1X PLL2 charge pump control R/W — x1 0 Bit 2 PLL2_CP_/24 PLL2 charge pump control R/W — /24 1 Bit 1 PLL2_CP_/3 PLL2 charge pump control R/W — /3 0 Bit 0 PLL2_SIREF PLL2 SiRef current selection R/W 10μA 20μA 0 Byte 26: PLL2 M Divider Setting Byte 1Ah Name Control Function Type 0 1 PWD Bit 7 PLL2_MDIV_Doubler PLL2 reference divider - doubler R/W disable enable 0 Bit 6 PLL2_MDIV1 PLL2 reference divider 1 R/W disable M DIV1 bypadd divider (/1) 0 Bit 5 PLL2_MDIV2 PLL2 reference divider 2 R/W disable M DIV2 bypadd divider (/2) 0 Bit 4 PLL2_MDIV[4] PLL2 reference divider control bit 4 R/W 1 Bit 3 PLL2_MDIV[3] PLL2 reference divider control bit 3 R/W 1 Bit 2 PLL2_MDIV[2] PLL2 reference divider control bit 2 R/W Bit 1 PLL2_MDIV[1] PLL2 reference divider control bit 1 R/W 1 Bit 0 PLL2_MDIV[0] PLL2 reference divider control bit 0 R/W 0 ©2017 Integrated Device Technology, Inc. 22 3–64, default is 26 0 October 24, 2017 5L2503 Datasheet Byte 27: Output Divider 4 Byte 1Bh Name Control Function Type 0 1 PWD Bit 7 OUTDIV3[3] Out divider 4 control bit 7 R/W Bit 6 OUTDIV3[2] Out divider 4 control bit 6 R/W Bit 5 OUTDIV3[1] Out divider 4 control bit 5 R/W Bit 4 OUTDIV3[0] Out divider 4 control bit 4 R/W 0 Bit 3 OUTDIV4[3] Out divider 4 control bit 3 R/W 0 Bit 2 OUTDIV4[2] Out divider 4 control bit 2 R/W Bit 1 OUTDIV4[1] Out divider 4 control bit 1 R/W Bit 0 OUTDIV4[0] Out divider 4 control bit 0 R/W 0 DIV3[3:2] = 1,2,4,5; DIV3[1:0] = 1,3,5,10; Default Divider = 1 x 5 = 5 DIV4[3:2] = 1,2,4,8; DIV4[1:0] = 1,3,5,10; Default Divider = 1 x 10 = 10 0 1 0 1 1 Byte 28: PLL Operation Control Register Byte 1Ch Name Control Function Type 0 1 PWD Bit 7 PLL2_HRS_EN PLL2 spread high resolution selection enable R/W normal enable (shift 4 bits) 0 Bit 6 PLL2_refin_sel PLL2 reference clock source select R/W Xtal DIV2 0 Bit 5 PLL3_PDB PLL3 power down R/W power down running 0 Bit 4 PLL3_LCKBYPSSB PLL3 lock bypass R/W bypass lock lock 0 Bit 3 PLL2_PDB PLL2 power down R/W power down running 1 Bit 2 PLL2_LCKBYPSSB PLL2 lock bypass R/W bypass lock lock 1 Bit 1 PLL1_PDB PLL1 power down R/W power down running 0 Bit 0 PLL1_LCKBYPSSB PLL1 lock bypass R/W bypass lock lock 0 0 1 PWD Byte 29: Output Control Byte 1Dh Name Control Function Type Bit 7 Reserved 0 Bit 6 Reserved 0 Bit 5 Reserved 1 Bit 4 Reserved 1 Bit 3 Reserved 0 Bit 2 VDD1_SEL VDD1_SEL R/W 1.8V 1.2V 0 Bit 1 Reserved 0 Bit 0 Reserved 0 ©2017 Integrated Device Technology, Inc. 23 October 24, 2017 5L2503 Datasheet Byte 30: OE and DFC Control Byte 1Eh Name Control Function Type 0 1 PWD Bit 7 OUT1_EN OUT1 output enable control R/W disable enable 1 Bit 6 OE1_fun_sel[1] OE1 pin function selection bit 1 R/W OE1_fun_sel[0] OE1 pin function selection bit 0 R/W 10: OUT_PPS 00: OUT1 OE 0 Bit 5 11:DFC0 01: PD# 0 Bit 4 Reserved 1 Bit 3 Reserved 1 Bit 2 Reserved 0 Bit 1 DFC_SW_Sel[1] DFC frequency select bit 1 R/W Bit 0 DFC_SW_Sel[0] DFC frequency select bit 0 R/W 00: N0 01: N1 10:N2 11:N3 0 0 Byte 31: Control Register Byte 1Fh Name Control Function Type 0 1 PWD Bit 7 OUT2 free run_b OUT2 free run_b R/W freerun stoppable 1 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 PLL2_3rd_EN_CFG PLL2 3rd order control R/W 1st order 3rd order 1 Bit 1 OUTDIV5 source OUTDIV5 source R/W PLL3 DIV4seed 0 Bit 0 PLL2_EN_3rdpole PLL2 3rd pole control R/W disable enable 0 Control Function Type 0 1 PWD Byte 32: Control Register Byte 20h Name Bit 7 Reserved Bit 6 OUT2_fun_sel Bit 5 Reserved Bit 4 DFC_EN OUT2 pin function selection 1 R/W OE1pin controlled OE1pin not controlled 1 0 DFC function control R/W disable enable 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit 1 Reserved 0 Bit 0 Reserved 0 ©2017 Integrated Device Technology, Inc. 24 October 24, 2017 5L2503 Datasheet Byte 33: OUT3 Control Register Byte 21h Name Control Function Type 0 1 PWD Bit 7 OUT3 free run_b OUT3 free run_b R/W freerun stoppable 1 Bit 6 Reserved 0 Bit 5 Reserved 0 Bit 4 Reserved 0 Bit 3 Reserved 0 Bit 2 Reserved 0 Bit 1 Reserved 0 Bit 0 Reserved 0 Byte 34: Control Register Byte 22h Name Control Function Type 0 1 PWD Bit 7 Reserved 1 Bit 6 Reserved 1 Bit 5 Reserved 1 Bit 4 Reserved 1 Bit 3 Reserved 0 Bit 2 Reserved 1 Bit 1 Reserved 0 Bit 0 Reserved 0 Byte 35: Control Register Byte 23h Name Control Function Type Bit 7 OUT3 muxsel1 OUT3 muxsel1 R/W Bit 6 OUT3 muxsel0 OUT3 muxsel0 R/W Bit 5 OUT2 muxsel1 OUT2 muxsel1 R/W Bit 4 OUT2 muxsel0 OUT2 muxsel0 R/W Bit 3 OUT1 muxsel1 OUT1 muxsel1 R/W Bit 2 OUT1 muxsel0 OUT1 muxsel0 R/W Bit 1 DIV1 muxsel1 DIV1 muxsel1 R/W Bit 0 DIV1 muxsel0 DIV1 muxsel0 R/W ©2017 Integrated Device Technology, Inc. 25 0 1 00: DIV3 01: DIV5 10: DIV1 11: CLK_32K 00: DIV3 01: DIV5 10: DIV1 11: CLK_32K 00: DIV3 01: DIV5 10: DIV1 11: CLK_32K 00: PLL1 01: REF 1x: DIV4outseed PWD 1 0 0 0 1 1 0 1 October 24, 2017 5L2503 Datasheet Byte 36: OUT1 and DIV4 control Byte 24h Name Control Function Type 0 1 PWD Bit 7 I2C_PDB Chip power down control bit R/W power down normal 1 Bit 6 Ref_free_run Reference clock output (OUT2/OUT3) R/W stop freerun 0 Bit 5 free_run_output_config clocks free run control R/W OUT2 free run OUT2/3 free run 0 Bit 4 Reserved 1 Bit 3 OUT1_Freerun_b OUT1 free run_b R/W freerun stoppable 1 Bit 2 Enable OE2/3 Enable OE2/OE3 function R/W disable enable 0 Bit 1 DIV4 muxsel1 DIV4 muxsel1 R/W Bit 0 DIV4 muxsel0 DIV4 muxsel0 R/W ©2017 Integrated Device Technology, Inc. 26 00: PLL2_CH2 01: PLL3_CH2 10: DIV3seed 11: DIV5seed 1 1 October 24, 2017 5L2503 Datasheet Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 ©2017 Integrated Device Technology, Inc. 27 October 24, 2017 5L2503 Datasheet Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 ©2017 Integrated Device Technology, Inc. 28 October 24, 2017 5L2503 Datasheet Marking Diagram 1. Line 1 is the truncated part number. 2. “000” denotes dash code. 3000 Y** 3. “Y” is the last digit of the year that the part was assembled. 4. “**” denotes sequential lot number. Ordering Information Orderable Part Number Package Shipping Packaging Temperature 5L2503-000NVGI 2.5 × 2.5 mm, 0.40mm pitch 12-DFN Tray -40° to +85°C 5L2503-000NVGI8 2.5 × 2.5 mm, 0.40mm pitch 12-DFN Reel -40° to +85°C Revision History Revision Date October 24, 2017 Description of Change Initial release. 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