Programmable Clock Generator
5P49V5944
DATASHEET
Description
Features
The 5P49V5944 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
• Generates up to two independent output frequencies
• High-performance, low phase noise PLL, < 0.7ps RMS
The frequencies are generated from a single reference clock.
The input reference can be either a crystal or an LVCMOS
reference clock.
• Two fractional output dividers (FODs)
• Independent spread spectrum capability on each output
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
• Four banks of internal non-volatile in-system
typical phase jitter on outputs:
– PCIe Gen1–3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
pair
programmable or factory programmable OTP memory
• I2C serial programming interface
• One reference LVCMOS output clock
• Two universal output pairs:
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
•
XOUT
XIN/REF
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
GND
VDDD
GND
• Input frequency ranges:
VDDO0
OUT0_SEL_I2CB
Pin Assignment
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O standards:
•
– LVCMOS reference clock input (XIN/REF): 1MHz to
200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
20 19 18 17 16
1
15
VDDO 1
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
2
14
OUT1
OUT1B
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
13
GND
GND
3
GND
4
12
SD/OE
5
11
10
EPAD
9
OUT2
8
VDDO2
7
SEL1/SDA
SEL0/SCL
6
each output pair
•
•
•
•
•
•
•
•
•
OUT2B
VDDA
3 × 3 mm 20-VFQFPN
5P49V5944 JULY 10, 2019
1
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
3 x 3 mm 20-VFQFPN package
-40° to +85°C industrial temperature operation
5P49V5944 DATASHEET
Functional Block Diagram
VDDO0
OUT0_SEL_I2CB
XIN/REF
XOUT
VDDO1
SD/OE
OUT1
PLL
FOD1
SEL1/SDA
SEL0/SCL
OUT1B
OTP
and
Control Logic
VDDO2
VDDA
OUT2
VDDD
FOD2
OUT2B
Applications
•
•
•
•
•
•
•
•
•
•
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber channel, SAN
Telecom line cards
1 GbE and 10 GbE
PROGRAMMABLE CLOCK GENERATOR
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JULY 10, 2019
5P49V5944 DATASHEET
Table 1: Pin Descriptions
Type
Number
1
Name
XOUT
Input
2
XIN/REF
Input
3
VDDA
Power
4
GND
Power
5
SD/OE
Input
Pull-down
6
SEL1/SDA
Input
Pull-down
7
SEL0/SCL
Input
Pull-down
8
VDDO2
Power
9
OUT2
Output
10
OUT2B
Output
11
12
GND
GND
Power
Power
13
OUT1B
Output
14
OUT1
Output
15
VDDO1
Power
16
GND
Power
17
VDDD
Power
18
GND
Power
19
VDDO0
Power
20
ePAD
JULY 10, 2019
OUT0_SELB_I2C Input/Output
Pull-down
Description
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Connect to ground.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the singleended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Output Clock 2. Please refer to the Output Drivers section for more details.
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
Connect to ground.
Connect to ground.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Connect to ground.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
Connect to ground.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output.
Connect to ground pad.
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PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
PLL Features and Descriptions
Spread Spectrum
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
To help reduce electromagnetic interference (EMI), the
5P49V5944 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5944 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The spread spectrum can be
applied to any output clock, any clock frequency, and any
spread amount from ±0.25% to ±2.5% center spread and
-0.5% to -5% down spread.
Table 2:
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Loop
Loop
Frequency–Fref Bandwidth Min Bandwidth Max
(MHz)
(kHz)
(kHz)
1
40
126
350
300
1000
Table 3:
Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
REG0:7 Config
OUT0_SEL_I2CB SEL1 SEL0
I 2C
Access
at POR
1
0
0
No
0
0
1
0
1
No
0
1
1
1
0
No
0
2
1
1
1
No
0
3
1
I2C
0
X
X
Yes
defaults
0
X
X
Yes
0
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7 = 0,
after the first 10ms of operation the levels of the SELx pins can
be changed, either to low or to the same level as
VDDD/VDDA. The SELx pins must be driven with a digital
signal of < 300ns Rise/Fall time and only a single pin can be
changed at a time.
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5P49V5944 DATASHEET
Reference Clock Input Pins
The 5P49V5944 supports one clock input. The clock input
(XIN/ REF) can be driven by either an external crystal or a
reference clock.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
You can write the following equations for the total capacitance
at each crystal pin:
CXIN = Ci1 + Cs1 + Ce1
CXOUT = Ci2 + Cs2 + Ce2
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
Ci1 and Ci2 are the internal, tunable capacitors. Cs1 and Cs2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce1 and Ce2 are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce1 and/or Ce2 to avoid
crystal startup issues. Ce1 and Ce2 can also be used to adjust
for unpredictable stray capacitance in the PCB.
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
Bits
Step (pF)
Min. (pF)
Max. (pF)
XTAL
6
0.5
9
25
The final load capacitance of the crystal:
CL = CXIN × CXOUT / (CXIN + CXOUT)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
CXIN = CXOUT = Cx → CL = Cx / 2
You can write the following equation for this capacitance:
The complete formula when the capacitance at both crystal
pins is the same:
Ci = 9pF + 0.5pF × XTAL[5:0]
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
Example 1: The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs = 1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →
0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)
Example 2: The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →
XTAL[5:0] = 20 (decimal)
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PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
OTP Interface
Table 4:
SH bit SP bit OSn bit OEn bit SD/OE
The 5P49V5944 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5944 will
not generate Acknowledge bits. The 5P49V5944 will
acknowledge the instructions after it has completed execution
of them. During that time, the I2C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49V5944, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5944 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
x
0
1
1
x
x
0
1
Tri-state2
Output active
Output active
Output driven High Low
0
0
0
0
1
1
1
1
0
1
1
1
x
0
1
1
x
x
0
1
Tri-state2
Output active
Output driven High Low
Output active
1
1
1
0
0
0
0
1
1
x
0
1
0
0
0
Tri-state2
Output active
Output active
1
1
1
1
1
1
1
x
0
1
1
x
x
0
1
x
0
0
0
1
Tri-state2
Output active
Output driven High Low
Output driven High Low 1
Besides the POR at power up, the same synchronization reset
is also triggered when switching between configurations with
the SEL0/1 pins. This ensures that the outputs remain aligned
in every configuration. This reset causes the outputs to
suspend for a few hundred microseconds so the switchover is
not glitch-less. The reset can be disabled for applications
where glitch-less switch over is required and alignment is not
critical.
When using I2C to reprogram an output divider during
operation, alignment can be lost. Alignment can be restored
by manually triggering the reset through I2C.
When alignment is required for outputs with different
frequencies, the outputs are actually aligned on the falling
edges of each output by default. Rising edge alignment can
also be achieved by utilizing the programmable skew feature
to delay the faster clock by 180 degrees. The programmable
skew feature also allows for fine tuning of the alignment.
OUTn
SD/OE Input
OSn
Global Shutdown
For details of register programming, please see VersaClock 5
Family Register Descriptions and Programming Guide for
details.
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
PROGRAMMABLE CLOCK GENERATOR
0
1
1
1
Each output divider block has a synchronizing POR pulse to
provide startup alignment between outputs. This allows
alignment of outputs for low skew performance. The phase
alignment works both for integer output divider values and for
fractional output divider values.
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD.
SH
0
0
0
0
Output Alignment
SD/OE Pin Function
OEn
OUTn
0
0
0
0
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
Availability of Primary and Secondary I2C addresses to allow
programming for multiple devices in a system. The I2C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
Programming Guide provides detailed I2C programming
guidelines and register map.
SP
SD/OE Pin Function Truth Table
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5P49V5944 DATASHEET
Output Divides
Device Hardware Configuration
Each of the four output divides are comprised of a 12-bit
integer counter, and a 24-bit fractional counter. The output
divide can operate in integer divide only mode for improved
performance, or utilize the fractional counters to generate any
frequency with a synthesis accuracy better than 50ppb.
The 5P49V5944 supports an internal One-Time
Programmable (OTP) memory that can be pre-programmed
at the factory with up to 4 complete device configuration.
These configurations can be over-written using the serial
interface once reset is complete. Any configuration written via
the programming interface needs to be re-written after any
power cycle or reset. Contact IDT if a specific
factory-programmed configuration is desired.
The output divide also has the capability to apply a spread
modulation to the output frequency. Independent of output
frequency, a triangle wave modulation between 30 and 63kHz
may be generated.
Device Start-up & Reset Behavior
Output Skew
The 5P49V5944 has an internal power-up reset (POR) circuit.
The POR circuit will remain active for a maximum of 10ms
after device power-up.
For outputs that share a common output divide value, there
will be the ability to skew outputs by quadrature values to
minimize interaction on the PCB. The skew on each output
can be adjusted from 0 to 360 degrees. Skew is adjusted in
units equal to 1/32 of the VCO period. So, for 100MHz output
and a 2800MHz VCO, you can select how many 11.161ps
units you want added to your skew (resulting in units of 0.402
degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so
on. The granularity of the skew adjustment is always
dependent on the VCO period and the output period.
Upon internal POR circuit expiring, the device will exit reset
and begin self-configuration.
The device will load internal registers according to Table 3.
Once the full configuration has been loaded, the device will
respond to accesses on the serial port and will attempt to lock
the PLL to the selected source and begin operation.
Power Up Ramp Sequence
Output Drivers
VDDA and VDDD must ramp up together. VDDO0–2 must
ramp up before, or concurrently with, VDDA and VDDD. All
power supply pins must be connected to a power rail even if
the output is unused. All power supplies must ramp in a linear
fashion and ramp monotonically.
The OUT1 to OUT2 clock outputs are provided with
register-controlled output drivers. By selecting the output drive
type in the appropriate register, any of these outputs can
support LVCMOS, LVPECL, HCSL or LVDS logic levels
The operating voltage ranges of each output is determined by
its independent output power pin (VDDO) and thus each can
have different output voltage levels. Output voltage levels of
2.5V or 3.3V are supported for differential HCSL, LVPECL
operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS
and differential LVDS operation.
VDDO0~2
Each output may be enabled or disabled by register bits.
When disabled an output will be in a logic 0 state as
determined by the programming bit table shown on page 6.
VDDA
VDDD
LVCMOS Operation
When a given output is configured to provide LVCMOS levels,
then both the OUTx and OUTxB outputs will toggle at the
selected output frequency. All the previously described
configuration and control apply equally to both outputs.
Frequency, phase alignment, voltage levels and enable /
disable status apply to both the OUTx and OUTxB pins. The
OUTx and OUTxB outputs can be selected to be
phase-aligned with each other or inverted relative to one
another by register programming bits. Selection of
phase-alignment may have negative effects on the phase
noise performance of any part of the device due to increased
simultaneous switching noise within the device.
JULY 10, 2019
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PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
I2C Mode Operation
The device acts as a slave device on the I2C bus using one of
the two I2C addresses (0xD0 or 0xD4) to allow multiple
devices to be used in the system. The interface accepts
byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest
byte (most significant bit first). Read and write block transfers
can be stopped after any complete byte transfer. During a
write operation, data will not be moved into the registers until
the STOP bit is received, at which point, all data received in
the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use
external pull-up resistors for SDATA and SCLK. The internal
pull-down resistors have a size of 100k typical.
Current Read
S
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
Abar
P
A
Data 1
Sequential Read
S
Dev Addr + W
A
Reg start Addr
A
A
Reg start Addr
A
Sr
Dev Addr + R
A
Data 0
Data 1
A
A
A
Data n
Abar
P
Sequential Write
S
Dev Addr + W
from master to slave
from slave to master
Data 0
A
A
Data n
A
P
S = start
Sr = repeated start
A = acknowledge
Abar= none acknowledge
P = stop
I2C Slave Read and Write Cycle Sequencing
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5P49V5944 DATASHEET
Table 5: I2C Bus DC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Level
For SEL1/SDA pin
and SEL0/SCL
pin.
0.7xVDDD
5.5 2
V
VIL
Input LOW Level
For SEL1/SDA pin
and SEL0/SCL
pin.
GND-0.3
0.3xVDDD
V
30
0.4
V
µA
V
VHYS
IIN
VOL
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
0.05xVDDD
-1
IOL = 3 mA
Table 6: I2C Bus AC Characteristics
Symbol
FSCLK
tBUF
tSU:START
tHD:START
tSU:DATA
tHD:DATA
tOVD
CB
tR
tF
tHIGH
tLOW
tSU:STOP
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Hold Time, START
Setup Time, data input (SDA)
Hold Time, data input (SDA) 1
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCL)
Fall Time, data and clock (SDA, SCL)
HIGH Time, clock (SCL)
LOW Time, clock (SCL)
Setup Time, STOP
Min
10
1.3
0.6
0.6
0.1
0
20 + 0.1 x CB
20 + 0.1 x CB
0.6
1.3
0.6
Typ
Max
400
0.9
400
300
300
Unit
kHz
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
µs
µs
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
Note 2: I2C inputs are 5V tolerant.
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PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Table 7: Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5P49V5944. These ratings, which are standard values for IDT
commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect
product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDDA, VDDD, VDDO
3.465V
Inputs
XIN/REF
Other inputs
0V to 1.2V voltage swing
-0.5V to VDDD
Outputs, VDDO (LVCMOS)
-0.5V to VDDO + 0.5V
Outputs, IO (SDA)
10mA
Package Thermal Impedance, JA
48.43C/W (0 mps)
Package Thermal Impedance, JC
41.8C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
ESD Human Body Model
2000V
Junction Temperature
125°C
Table 8: Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDOx
Power supply voltage for supporting 1.8V outputs
1.71
1.8
1.89
V
VDDOx
Power supply voltage for supporting 2.5V outputs
2.375
2.5
2.625
V
VDDOx
Power supply voltage for supporting 3.3V outputs
3.135
3.3
3.465
V
VDDD
Power supply voltage for core logic functions.
Analog power supply voltage. Use filtered analog power
supply if available.
1.71
3.465
V
1.71
3.465
V
-40
85
°C
15
pF
8
40
MHz
0.05
5
ms
VDDA
TA
CLOAD_OUT
FIN
tPU
Operating temperature, ambient
Maximum load capacitance (3.3V LVCMOS only)
External reference crystal
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
Note: VDDO1 and VDDO2 must be powered on either before or simultaneously with VDDD, VDDA and VDDO0.
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5P49V5944 DATASHEET
Table 9: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down
Resistance (TA = +25 °C)
Symbol
CIN
Parameter
Input Capacitance (SD/OE, SEL1/SDA, SEL0/SCL)
Min
Typ
3
Pull-down Resistor SD/OE, SEL1/SDA, SEL0/SCL, OUT0_SEL_I2CB
LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)
ROUT
100
Max
Unit
7
pF
300
kΩ
Ω
17
XIN/REF
Programmable capacitance at XIN/REF (X1 in parallel with X2)
0
8
pF
XOUT
Programmable capacitance at XOUT (X1 in parallel with X2)
0
8
pF
Table 10: Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance (CL) @ 25M to 40M
Maximum Crystal Drive Level
Test Conditions
Minimum
8
6
6
Typical Maximum
Fundamental
25
40
10
100
7
8
12
8
100
Units
MHz
Ω
pF
pF
pF
µW
Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.
Table 11: DC Electrical Characteristics
Symbol
Parameter
Iddcore3
Core Supply Current
Iddox
Output Buffer Supply Current
Test Conditions
100 MHz on all outputs, 25 MHz
REFCLK
Min
Typ
Max
Unit
30
34
mA
LVPECL, 350 MHz, 3.3V VDDOx
42
47
mA
LVPECL, 350 MHz, 2.5V VDDOx
37
42
mA
LVDS, 350 MHz, 3.3V VDDOx
18
21
mA
LVDS, 350 MHz, 2.5V VDDOx
17
20
mA
LVDS, 350 MHz, 1.8V VDDOx
16
19
mA
HCSL, 250 MHz, 3.3V VDDOx, 2 pF load
29
33
mA
HCSL, 250 MHz, 2.5V VDDOx, 2 pF load
LVCMOS, 50 MHz, 3.3V, VDDOx 1,2
28
33
mA
16
18
mA
LVCMOS, 50 MHz, 2.5V, VDDOx
1,2
14
16
mA
LVCMOS, 50 MHz, 1.8V, VDDOx
1,2
12
14
mA
LVCMOS, 200 MHz, 3.3V VDDOx
1
36
42
mA
27
32
mA
LVCMOS, 200 MHz, 2.5V VDDOx 1,2
LVCMOS, 200 MHz, 1.8V VDDOx
Iddpd
Power Down Current
SD asserted, I2C Programming
1,2
16
19
mA
10
14
mA
1. Single CMOS driver active.
2. Measured into a 5” 50 Ohm trace with 2 pF load.
3. Iddcore = IddA+ IddD, no loads.
JULY 10, 2019
11
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Table 12: DC Electrical Characteristics for 3.3V LVCMOS (VDDO = 3.3V ±5%, TA = -40°C to +85°C)1
Symbol
Parameter
VOH
Output HIGH Voltage
Test Conditions
IOH = -15mA
Min
VOL
Output LOW Voltage
IOL = 15mA
IOZDD
IOZDD
Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 3.465V
Tri-state outputs, VDDO = 3.465V
Output Leakage Current (OUT0)
VIH
Input HIGH Voltage
Single-ended inputs - SD/OE
0.7xVDDD
Typ
2.4
Max
Unit
VDDO
V
0.4
V
5
µA
30
µA
VDDD + 0.3
V
VIL
Input LOW Voltage
Single-ended inputs - SD/OE
GND - 0.3
0.3xVDDD
V
VIH
Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
2
VDDO0 + 0.3
V
VIL
Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
GND - 0.3
0.4
V
VIH
Input HIGH Voltage
Single-ended input - XIN/REF
0.8
1.2
V
VIL
Input LOW Voltage
Single-ended input - XIN/REF
GND - 0.3
TR/TF
Input Rise/Fall Time
SD/OE, SEL1/SDA, SEL0/SCL
0.4
V
300
ns
1. See “Recommended Operating Conditions” table.
Table 13: DC Electrical Characteristics for 2.5V LVCMOS (VDDO = 2.5V ±5%, TA = -40°C to +85°C)
Symbol
Parameter
VOH
Output HIGH Voltage
VOL
IOZDD
IOL = 12mA
Output LOW Voltage
Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 2.625V
Tri-state outputs, VDDO = 2.625V
Output Leakage Current (OUT0)
VIH
Input HIGH Voltage
IOZDD
Test Conditions
IOH = -12mA
Min
Typ
Max
Unit
0.7xVDDO
Single-ended inputs - SD/OE
0.7xVDDD
V
0.4
V
5
µA
30
µA
VDDD + 0.3
V
VIL
Input LOW Voltage
Single-ended inputs - SD/OE
GND - 0.3
0.3xVDDD
V
VIH
Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
1.7
VDDO0 + 0.3
V
VIL
Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
GND - 0.3
0.4
V
VIH
Input HIGH Voltage
Single-ended input - XIN/REF
0.8
1.2
V
VIL
TR/TF
Input LOW Voltage
Input Rise/Fall Time
Single-ended input - XIN/REF
SD/OE, SEL1/SDA, SEL0/SCL
GND - 0.3
0.4
300
V
ns
Table 14: DC Electrical Characteristics for 1.8V LVCMOS (VDDO = 1.8V ±5%, TA = -40°C to +85°C)
Symbol
Parameter
VOH
Output HIGH Voltage
VOL
Test Conditions
IOH = -8mA
Min
0.7 xVDDO
IOL = 8mA
IOZDD
Output LOW Voltage
Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 1.89V
Tri-state outputs, VDDO = 1.89V
Output Leakage Current (OUT0)
VIH
Input HIGH Voltage
IOZDD
Single-ended inputs - SD/OE
0.7 * VDDD
Typ
Max
Unit
VDDO
V
0.25 x VDDO
V
5
µA
30
µA
VDDD + 0.3
V
VIL
Input LOW Voltage
Single-ended inputs - SD/OE
GND - 0.3
0.3 * VDDD
V
VIH
Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
0.65 * VDDO0
VDDO0 + 0.3
V
GND - 0.3
0.4
V
0.8
1.2
V
GND - 0.3
0.4
300
V
ns
VIL
Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
VIH
Input HIGH Voltage
Single-ended input - XIN/REF
VIL
TR/TF
Input LOW Voltage
Input Rise/Fall Time
Single-ended input - XIN/REF
SD/OE, SEL1/SDA, SEL0/SCL
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5P49V5944 DATASHEET
Table 15: DC Electrical Characteristics for LVDS (VDDO = 3.3V +5% or 2.5V +5%, TA = -40°C to +85°C)
Symbol
Parameter
Min
Typ
Max
Unit
VOT (+)
Differential Output Voltage for the TRUE binary state
247
454
mV
VOT (-)
Differential Output Voltage for the FALSE binary state
-247
-454
mV
50
mV
1.375
V
50
mV
VOT
VOS
VOS
IOS
IOSD
Change in VOT between Complimentary Output States
1.125
Output Common Mode Voltage (Offset Voltage)
1.25
Change in VOS between Complimentary Output States
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO
9
24
mA
Differential Outputs Short Circuit Current, VOUT+ = VOUT -
6
12
mA
Table 16: DC Electrical Characteristics for LVDS (VDDO = 1.8V +5%, TA = -40°C to +85°C)
Symbol
Parameter
Min
Typ
Max
Unit
VOT (+)
Differential Output Voltage for the TRUE binary state
247
454
mV
VOT (-)
Differential Output Voltage for the FALSE binary state
-247
-454
mV
50
mV
0.95
V
50
mV
VOT
VOS
VOS
IOS
IOSD
JULY 10, 2019
Change in VOT between Complimentary Output States
0.8
Output Common Mode Voltage (Offset Voltage)
0.875
Change in VOS between Complimentary Output States
Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO
9
24
mA
Differential Outputs Short Circuit Current, VOUT+ = VOUT -
6
12
mA
13
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Table 17: DC Electrical Characteristics for LVPECL (VDDO = 3.3V +5% or 2.5V +5%, TA = -40°C to
+85°C)
Symbol
Parameter
Min
Typ
Max
Unit
VOH
Output Voltage HIGH, terminated through 50 tied to VDD - 2 V
VDDO - 1.19
VDDO - 0.69
V
VOL
Output Voltage LOW, terminated through 50 tied to VDD - 2 V
VDDO - 1.94
VDDO - 1.4
V
0.55
0.993
V
VSWING
Peak-to-Peak Output Voltage Swing
Table 18: Electrical Characteristics – DIF 0.7V Low Power HCSL Differential Outputs
(VDDO = 3.3V ±5%, 2.5V ±5%, TA = -40°C to +85°C)
Symbol
Parameter
Conditions
dV/dt
ΔdV/dt
Slew Rate
Scope averaging on
Slew Rate
VHIGH
Voltage High
VLOW
Voltage Low
Scope averaging on
Statistical measurement on single-ended
signal using oscilloscope math function
(Scope averaging ON)
VMAX
Maximum Voltage
VMIN
Minimum Voltage
VSWING
Voltage Swing
Min
1
Measurement on single-ended signal using
absolute value (Scope averaging off)
Scope averaging off
Scope averaging off
VCROSS Crossing Voltage Value
VCROSS
Crossing Voltage variation Scope averaging off
Δ
660
-150
Typ
Max
Units
Notes
4
V/ns
1,2,3
20
%
1,2,3
850
mV
1,6,7
150
mV
1,6
1150
mV
1
-300
mV
1
300
mV
1,2,6
550
mV
1,4,6
140
mV
1,5
250
1. Guaranteed by design and characterization. Not 100% tested in production.
2. Measured from differential waveform.
3. Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a ±150mV window around differential 0V.
4. VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
5. The total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute) allowed. The intent
is to limit VCROSS induced modulation by setting VCROSS to be smaller than VCROSS absolute.
6. Measured from single-ended waveform.
7. Measured with scope averaging off, using statistics function. Variation is difference between minimum and maximum.
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5P49V5944 DATASHEET
Table 19: AC Timing Electrical Characteristics
(VDDO = 3.3V +5% or 2.5V +5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread spectrum generation = OFF)
Symbol
fIN
1
Parameter
Input Frequency
Min.
Max.
Units
Input frequency limit (XIN)
1
40
MHz
1
200
1
350
2600
2900
Test Conditions
fOUT
Output Frequency
Single ended clock output limit (LVCMOS)
Differential cock output limit (LVPECL/
LVDS/HCSL)
fVCO
VCO Frequency
VCO operating frequency range
fPFD
PFD Frequency
PFD operating frequency range
fBW
Loop Bandwidth
Input frequency = 25MHz
t2
Input Duty Cycle
Duty Cycle
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX= 2.5V or
3.3V
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX=1.8V
Measured at VDD/2, Reference output
OUT0 (5MHz - 120MHz) with 50% duty
cycle input
Measured at VDD/2, Reference output
OUT0 (150.1MHz - 200MHz) with 50% duty
cycle input
t3 5
Output Duty Cycle
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Slew Rate, SLEW[1:0] = 00
t4 2
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
t5
JULY 10, 2019
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=3.3V
Single-ended 2.5V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=2.5V
Single-ended 1.8V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=1.8V
1
Typ.
1
0.06
MHz
150
MHz
0.9
MHz
45
50
55
%
45
50
55
%
40
50
60
%
40
50
60
%
30
50
70
%
1.0
2.2
1.2
2.3
1.3
2.4
1.7
2.7
0.6
1.3
0.7
1.4
0.6
1.4
1.0
1.7
0.3
0.7
0.4
0.8
0.4
0.9
0.7
1.2
Rise Times
LVDS, 20% to 80%
300
Fall Times
LVDS, 80% to 20%
300
Rise Times
LVPECL, 20% to 80%
400
Fall Times
LVPECL, 80% to 20%
400
15
MHz
V/ns
ps
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
t8 3
Lock Time
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
differential outputs (1.8V to 3.3V nominal
output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
LVCMOS outputs (1.8 to 3.3V nominal
output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
25 MHz LVCMOS outputs (1.8 to 3.3V
nominal output voltage).
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 20MHz
integration range) differential output, VDDO
= 3.465V, 25MHz crystal, 156.25MHz
output frequency
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
Skew between the same frequencies, with
outputs using the same driver format and
phase delay set to 0 ns.
PLL lock time from power-up
4
Lock Time
PLL lock time from shutdown mode
t6
t7
t9
Clock Jitter
Output Skew
46
ps
74
ps
0.5
ps
0.75
1.5
75
ps
ps
10
20
ms
3
4
ms
1. Practical lower frequency is determined by loop filter settings.
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
4. Actual PLL lock time depends on the loop configuration.
5. Duty Cycle is only guaranteed at max slew rate settings.
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Table 20: PCI Express Jitter Specifications (VDDO = 3.3V +5% or 2.5V +5%, TA = -40°C to +85°C)
Symbol
Parameter
tJ
(PCIe Gen1)
Conditions
Min
Typ
PCIe Industry
Specification
Units Notes
30
86
ps
1,4
ƒ = 100MHz, 25MHz Crystal Input
tREFCLK_HF_RMS
(PCIe Gen2)
Phase Jitter RMS High Band: 1.5MHz - Nyquist (clock
frequency/2)
2.56
3.10
ps
2,4
tREFCLK_LF_RMS
(PCIe Gen2)
tREFCLK_RMS
(PCIe Gen3)
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Max
Phase Jitter
Peak-to-Peak
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.27
3.0
ps
2,4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.8
1.0
ps
3,4
Phase Jitter RMS
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test
socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these
conditions.
1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.
2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results
for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low
Band).
3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010
specification, and is subject to change pending the final release version of the specification.
4. This parameter is guaranteed by characterization. Not tested in production.
Table 21: Jitter Specifications 1,2,3
(VDDx = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)
Parameter
Symbol
4
GbE Random Jitter (12 kHz–20 MHz)
GbE Random Jitter (1.875–20 MHz)
PCI Express 1.1 Common Clocked
PCI Express 2.1 Common Clocked
PCI Express 3.0 Common Clocked
Test Condition
Min
Typ
Max
Unit
JGbE
Crystal in = 25 MHz, All CLKn at 125 MHz
5
-
0.79
0.95
ps
RJGbE
Crystal in = 25 MHz, All CLKn at 125 MHz 5
-
0.32
0.5
ps
ps
6
Total Jitter
-
9.1
12
RMS Jitter6, 10 kHz to 1.5MHz
-
0.1
0.3
ps
RMS Jitter6, 1.5MHz to 50MHz
-
0.9
1.1
ps
RMS Jitter6
-
0.2
0.4
ps
Notes:
1
All measurements w ith Spread Spectrum Off.
2
For best jitter performance, keep the single ended clock input slew rates at more than 1.0 V/ns and the differential clock input slew rates more than 0.3 V/ns.
All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there is the potential that the output jitter may increase
due to the nature of single-ended outputs. If your configuration implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact
IDT for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS outputs have little to no effect upon jitter.
3
4
DJ for PCI and GbE is < 5 ps pp.
5
Output FOD in Integer mode.
All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter. Jitter is measured w ith the Intel Clock Jitter Tool,
Ver. 1.6.6.
6
JULY 10, 2019
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PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Table 22: Spread Spectrum Generation Specifications
Symbol
Parameter
Description
fOUT
Output Frequency
Output Frequency Range
fMOD
Mod Frequency
Modulation Frequency
Spread Value
fSPREAD
Min
Typ
5
Max
Unit
300
MHz
30 to 63
kHz
Amount of Spread Value (programmable) – center spread
±0.25% to ±2.5%
%fOUT
Amount of Spread Value (programmable) – down spread
-0.5% to -5%
Test Circuits and Loads
VDDOx
VDDD
VDDA
0.1µF
OUTx
0.1µF
0.1µF
CLKOUT
CL
GND
HCSL Differential Output Test Load
Zo=100ohm differential
33
33
HCSL Output
2pF
50
2pF
50
Test Circuits and Loads for Outputs
PROGRAMMABLE CLOCK GENERATOR
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JULY 10, 2019
5P49V5944 DATASHEET
Phase Noise Plots
NOTE: OUT1 = 100MHz HCSL, OUT2 = 156.25MHz; all phase noise plots with spurs on (3.3V, 25°C).
JULY 10, 2019
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PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
5P49V5944 Application Schematic
The following figure shows an example of 5P49V5944 application schematic. Input and output terminations shown are intended as examples
only and may not represent the exact user configuration. In this example, the device is operated at VDDD, VDDA = 3.3V. The decoupling
capacitors should be located as close as possible to the power pin. A 12pF parallel resonant 8MHz to 40MHz crystal is used in this example.
Different crystal frequencies may be used. The C1 = C2 = 5pF are recommended for frequency accuracy. If different crystal types are used,
please consult IDT for recommendations. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power
supply isolation is required. 5P49V5944 provides separate power supplies to isolate any high switching noise from coupling into the internal
PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1µf capacitor in each power pin filter should be placed on the device side. The
other components can be on the opposite side of the PCB.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter
performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be
adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests
adding bulk capacitance in the local area of all devices.
The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables
in the datasheet to ensure the logic control inputs are properly set.
PROGRAMMABLE CLOCK GENERATOR
20
JULY 10, 2019
A
B
C
1
V3P3
C6
NP
GND
R7
10K
25.000MHz
25.000
MHz
CL CL=8pF
= 8pF
2
3
FB1
2
C1
10uF
SD/OE
SEL1/SDA
SEL0/SCL
2
CLKIN
.1uF
1
2 CLKINB
C12
.1uF
5
SD/OE
1
C13
6
7
SDA
SCL
XOUT
XIN/REF
C11
.1uF
C5
.1uF
V1P8VC
C4
.1uF
VDDD
VDDA
VDD
5
1
2.2
C8
.1uF
R2
V1P8VC
OUTR1
OUTRB1
V1P8VC
OUTR2
OUTRB2
15
14
13
8
9
10
OUT_0_SEL-I2C
PULL-UP FOR
HARDWARE
CONFIGURATION
CONTROL
REMOVE FOR I2C
16
18
11
12
V1P8VC
OUTR0
V1P8VCA
19
20
17
3
4
4
R9
10K
V1P8VC
R6 1
2
C2
1uF
V1P8VCA
.1uF
C3
V1P8VCA
The following pins
have weak internal
pull-down resistors:
5,6,7 and 20
GND
GND
GND
GND
VDDO2
OUT2
OUT2B
VDDO1
OUT1
OUT1B
VDDO0
OUT0_SEL_I2CB
FOR LVDS, LVPECL AC COUPLE
USE TERMINATION ON RIGHT
SEE DATASHEET FOR BIAS NETWORK
C7 NP
FG_X1 1
FG_X2 2
6
U5
5P49V5944A
OUT_0_SEL-I2C
1
R10
1
R11
1
R12
R3
1
2
R5
49.9
1%
2
33
2
33
R4
49.9
1%
R15 1
LVCMOS TERMINATION
OUTR2
HCSL TERMINATION
1
R13
1
R14
2
2
50
2
50
2
50
100
2 33
3.3V LVPECL TERMINATION
LVDS TERMINATION
2 33
3
OUT_2
2
1
2
1
2
1
RECEIVER
U4
RECEIVER
U2
RECEIVER
U3
1
8
7
Revision history
0.1 03/05/2015 first publication
6
5
4
Thursday, March 05, 2015
Date:
3
Document Number
5P49V5944A_SCH
Size
A
2
Sheet
1
of
1
1
Re v
0.1
Layout notes:
1. Separate Xout and Xin Traces by 3 x the trace width
2. Do not share crystal load capacitor ground via with
other components.
3. Route power from bead through bulk capacitor pad
then through 0.1uF capacitor pad then to clock chip
NOTE:FERRITE BEAD FB1 =
Vdd pad.
Manufacture Part Number
Z@100MHz PkgSz DC res. Current(Ma) 4. Do not share ground vias. One ground pin one ground
Fair-Rite
2504021217Y0
120
0402
0.5
200
via.
muRata
BLM15AG221SN1 220
0402
0.35
300
300
muRata
BLM15BB121SN1 120
0402
0.35
Integrated Device Technology
TDK
MMZ1005S241A
240
0402
0.18
200
San Jose, CA
TECSTAR
TB4532153121
120
0402
0.3
300
SIGNAL_BEAD
1
VCC1P8
PLACE NEAR
I2C CONTROLLER
IF USED
SDA
SCL
R8
10K
2
GND
2
1
D
4
2
1
1
2
Y1
7
2
1
1
1
2
1
2
1
2
1
2
1
EPAD
EPAD
EPAD
EPAD
EPAD
21
22
23
24
25
2
1
2
1
2
1
21
2
2
JULY 10, 2019
1
8
A
B
C
D
5P49V5944 DATASHEET
5P49V5944 Reference Schematic
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Overdriving the XIN/REF Interface
LVCMOS Driver
This configuration has three properties; the total output
impedance of Ro and Rs matches the 50 transmission line
impedance, the Vrx voltage is generated at the CLKIN inputs
which maintains the LVCMOS driver voltage level across the
transmission line for best S/N and the R1–R2 voltage divider
values ensure that the clock level at XIN is less than the
maximum value of 1.2V.
The XIN/REF input can be overdriven by an LVCMOS driver
or by one side of a differential driver through an AC coupling
capacitor. The XOUT pin can be left floating. The amplitude of
the input signal should be between 500mV and 1.2V and the
slew rate should not be less than 0.2V/ns. Figure General
Diagram for LVCMOS Driver to XTAL Input Interface shows an
example of the interface diagram for a LVCMOS driver.
VDD
XOUT
Rs
Ro
Ro + Rs =
Zo = 50 Ohm
C3
R1
V_XIN
50 o hms
XIN / REF
0. 1 uF
LVCMOS
R2
General Diagram for LVCMOS Driver to XTAL Input Interface
adjusted to reduce the loading for slower and weaker
LVCMOS driver by increasing the voltage divider attenuation
as long as the minimum drive level is maintained over all
tolerances. To assist this assessment, the total load on the
driver is included in the table.
Table 23 Nominal Voltage Divider Values vs LVCMOS VDD for
XIN shows resistor values that ensure the maximum drive
level for the XIN/REF port is not exceeded for all combinations
of 5% tolerance on the driver VDD, the VersaClock VDDA and
5% resistor tolerances. The values of the resistors can be
Table 23: Nominal Voltage Divider Values vs LVCMOS VDD for XIN
LVCMOS Driver VDD
Ro + Rs
R1
R2
V_XIN (peak)
Ro + Rs + R1 + R2
3.3
50.0
130
75
0.97
255
2.5
50.0
100
100
1.00
250
1.8
50.0
62
130
0.97
242
PROGRAMMABLE CLOCK GENERATOR
22
JULY 10, 2019
5P49V5944 DATASHEET
LVPECL Driver
used, they can be utilized for debugging purposes. The
datasheet specifications are characterized and guaranteed by
using a quartz crystal as the input. If the driver is 2.5V
LVPECL, the only change necessary is to use the appropriate
value of R3.
Figure General Diagram for LVPECL Driver to XTAL Input
Interface shows an example of the interface diagram for a
+3.3V LVPECL driver. This is a standard LVPECL termination
with one side of the driver feeding the XIN/REF input. It is
recommended that all components in the schematics be
placed in the layout; though some components might not be
XOUT
C1
Z o = 50 Ohm
XIN / REF
0. 1 uF
Z o = 50 Ohm
+3.3V LVPECL Dr iv er
R1
50
R2
50
R3
50
General Diagram for +3.3V LVPECL Driver to XTAL Input Interface
JULY 10, 2019
23
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
LVDS Driver Termination
common mode noise. The capacitor value should be
approximately 50pF. In addition, since these outputs are LVDS
compatible, the input receiver's amplitude and common-mode
input range should be verified for compatibility with the IDT
LVDS output. If using a non-standard termination, it is
recommended to contact IDT and confirm that the termination
will function as intended. For example, the LVDS outputs
cannot be AC coupled by placing capacitors between the
LVDS outputs and the 100 shunt load. If AC coupling is
required, the coupling caps must be placed between the 100
shunt termination and the receiver. In this manner the
termination of the LVDS output remains DC coupled.
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90. and 132. The
actual value should be selected to match the differential
impedance (Zo) of your transmission line. A typical
point-to-point LVDS design uses a 100 parallel resistor at the
receiver and a 100. differential transmission-line
environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must
be placed as close to the receiver as possible. The standard
termination schematic as shown in figure Standard
Termination or the termination of figure Optional Termination
can be used, which uses a center tap capacitance to help filter
LVDS
Driver
ZO ZT
ZT
LVDS
Receiver
Standard Termination
LVDS
Driver
Z O ZT
C
ZT
2 LVDS
ZT Receiver
2
Optional Termination
PROGRAMMABLE CLOCK GENERATOR
24
JULY 10, 2019
5P49V5944 DATASHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs generate ECL/LVPECL compatible
outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality.
These outputs are designed to drive 50 transmission lines.
Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. The figure
below show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
3.3V
Zo=50ohm
+
Zo=50ohm
LVPECL
R1
50ohm
R2
50ohm
Input
RTT
50ohm
3.3V LVPECL Output Termination (1)
3.3V
3.3V
R3
125ohm
3.3V
R4
125ohm
Zo=50ohm
+
Zo=50ohm
LVPECL
Input
R1
84ohm
R2
84ohm
3.3V LVPECL Output Termination (2)
JULY 10, 2019
25
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
Termination for 2.5V LVPECL Outputs
Figures 2.5V LVPECL Driver Termination Example (1) and (2)
show examples of termination for 2.5V LVPECL driver. These
terminations are equivalent to terminating 50 to VDDO – 2V.
For VDDO = 2.5V, the VDDO – 2V is very close to ground level.
The R3 in Figure 2.5V LVPECL Driver Termination Example
(3) can be eliminated and the termination is shown in example
(2).
VDDO = 2.5V
2.5V
2.5V
VDDO = 2.5V
R1
250ohm
Zo=50ohm
2.5V
R3
250ohm
+
Zo=50ohm
Zo=50ohm
+
2.5V LVPECL
Driver
Zo=50ohm
2.5V LVPECL
Driver
R2
62.5ohm
R4
62.5ohm
R2
50ohm
R3
18ohm
2.5V LVPECL Driver Termination Example (3)
2.5V LVPECL Driver Termination Example (1)
VDDO = 2.5V
R1
50ohm
2.5V
Zo=50ohm
+
Zo=50ohm
2.5V LVPECL
Driver
R1
50ohm
R2
50ohm
2.5V LVPECL Driver Termination Example (2)
PROGRAMMABLE CLOCK GENERATOR
26
JULY 10, 2019
5P49V5944 DATASHEET
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below
shows the most frequently used Common Clock Architecture
in which a copy of the reference clock is provided to both ends
of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes
PLLs are modeled as well as the phase interpolator in the
receiver. These transfer functions are called H1, H2, and H3
respectively. The overall system transfer function at the
receiver is:
For PCI Express Gen2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in RMS. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of
applying this system transfer function to the clock spectrum
X(s) and is:
Y s = X s H3 s H1 s – H2 s
In order to generate time domain jitter numbers, an inverse
Fourier Transform is performed on X(s) × H3(s) × [H1(s) H2(s)].
PCIe Gen2A Magnitude of Transfer Function
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen1 Magnitude of Transfer Function
JULY 10, 2019
27
PROGRAMMABLE CLOCK GENERATOR
5P49V5944 DATASHEET
PCIe Gen3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
Marking Diagram
ddd
5944B
YW**$
• “ddd” denotes the dash code.
• Line 2: truncated part number.
• “YW” is the last digit of the year and week that the part was assembled.
• “**” denotes sequential lot number.
• “$” denotes mark code.
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/20-vfqfpn-package-outline-drawing-30-x-30-x-090-mm-040mm-pitch-165-x-165-mm-epad-ndg20p2
PROGRAMMABLE CLOCK GENERATOR
28
JULY 10, 2019
5P49V5944 DATASHEET
Ordering Information
Part / Order Number
Shipping Packaging
Package
Temperature
5P49V5944BdddNDGI
5P49V5944BdddNDGI8
Trays
Tape and Reel
3 × 3 mm 20-VFQFPN
3 × 3 mm 20-VFQFPN
-40° to +85C
-40° to +85C
Note: “ddd” denotes the dash code.
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Revision History
Date
July 10, 2019
Description of Change
• Updated Package Thermal Impedance Theta JA from 42° C/W to 48.43° C/W.
• Updated package outline drawings section.
October 30, 2017
March 3, 2017
February 24, 2017
JULY 10, 2019
Updated Phase Noise plot diagrams.
Updated package outline drawings and legal disclaimer.
1. Added “Output Alignment” section.
2. Update “Output Divides” section.
29
PROGRAMMABLE CLOCK GENERATOR
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Sales
Tech Support
6024 Silver Creek Valley Road
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www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
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www.idt.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
5P49V5944 JULY 10, 2019
30
©2019 Integrated Device Technology, Inc.
20-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.90 mm, 0.40mm Pitch, 1.65 x 1.65 mm Epad
NDG20P2, PSC-4179-02, Rev 01, Page 1
© Integrated Device Technology, Inc.
20-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.90 mm, 0.40mm Pitch, 1.65 x 1.65 mm Epad
NDG20P2, PSC-4179-02, Rev 01, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
Sept 13, 2018
Rev 01
Change QFN to VFQFPN
Mar 30, 2016
Rev 00
Initial Release
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