70V25L25J8

HIGH-SPEED 3.3V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access IDT70V35 – Commercial: 15ns (max.) – Industrial: 20ns IDT70V34 – Commercial: 15ns (max.) IDT70V25 – Commercial: 15/35ns (max.) – Industrial: 20/25ns IDT70V24 – Commercial: 15//35/55ns (max.) – Industrial: 15/20ns Low-power operation – IDT70V35/34L Active: 415mW (typ.) Standby: 660μW (typ.) ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 70V35/34S/L 70V25/24S/L – IDT70V25/24S – IDT70V25/24L Active: 400mW (typ.) Active: 380mW (typ.) Standby: 3.3mW (typ.) Standby: 660μW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility IDT70V35/34 (IDT70V25/24) easily expands data bus width to 36 bits (32 bits) or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (±0.3V) power supply Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24), and 84-pin PLCC (IDT70V24) Industrial temperature range (-40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL LBR CER OER , I/O9R-I/O17R(5) I/O9L-I/O17L(5) I/O Control I/O Control I/O0R-I/O8R(4) I/O0L-I/O8L(4) (2,3) BUSYR(2,3) BUSYL A12L(1) A0L Address Decoder MEMORY ARRAY 13 CEL OEL R/WL (3) A12R(1) A0R 13 ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR INTR(3) SEML INTL NOTES: 1. A12 is a NC for IDT70V34 and for IDT70V24. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. 4. I/O0x - I/O7x for IDT70V25/24. 5. I/O8x - I/O15x for IDT70V25/24. Address Decoder M/S 5624 drw 01 OCTOBER 2019 1 ©2019 Integrated Device Technology, Inc. DSC-5624/10 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Description Industrial and Commercial Temperature Ranges The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 430mW (IDT70V35/34) and 400mW (IDT70V25/24) of power. The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin Thin Quad Flatpack. The IDT70V24 is packaged in a 84-Pin PLCC. N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL Vss M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C Pin Configurations(1,2,3,4) A6L A7L A8L A9L A10L A11L 46 45 80 81 82 44 43 83 42 84 85 86 87 88 89 90 70V35/34 PNG100(5) 100-Pin TQFP Top View 41 40 39 38 37 36 91 92 35 34 93 94 95 96 97 33 32 31 30 29 98 28 99 27 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 N/C N/C I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L Vss I/O15L I/O16L VDD Vss I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R N/C N/C A12L(1) LBL UBL CEL SEML R/WL VDD OEL I/O0L I/O1L Vss I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O9L I/O10L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 49 77 48 78 47 79 NOTES: 1. A12 is a NC for IDT70V34. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. PNG100 package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6.42 2 A5R A6R A7R A8R A9R A10R A11R A12R(1) LBR UBR CER SEMR Vss R/WR OER I/O16R Vss I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O7R 5624 drw 02 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL VSS M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C Pin Configurations(1,2,3,4)(con't) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 81 45 44 82 83 84 43 42 85 86 87 70V25/24 PNG100(5) 88 89 100-Pin TQFP Top View 90 38 37 36 35 34 33 32 91 92 93 94 95 96 31 30 29 97 28 98 99 100 1 2 41 40 39 27 3 4 5 6 7 8 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L VSS I/O14L I/O15L VDD VSS I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C A6L A7L A8L A9L A10L A11L A12L(1) LBL UBL CEL SEML R/WL VDD OEL I/O0L I/O1L VSS I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L I/O9L NOTES: 1. A12 is a NC for IDT70V24. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. PNG100 package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6.42 3 A5R A6R A7R A8R A9R A10R A11R A12R(1) LBR UBR CER SEMR VSS R/WR OER I/O15R VSS I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O8R I/O7R 5624 drw 03 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. A12 is a NC for IDT70V24. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. PLG84 package body is approximately 1.15 in x 1.15 in x .17 in. 5. This package code is used to reference the package diagram. 6.42 4 I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L OEL VDD R/WL SEML CEL UBL LBL A12L(1) A11L A10L A9L A8L A0L A1L A2L A3L A4L A5L A6L A7L INTL A6R A9R A8R A7R BUSYL A12R(1) A11R A10R M/S VSS UBR LBR BUSYR R/WR VSS SEMR CER A0R INTR I/O15R OER A4R A3R A2R A1R I/O10R I/O11R I/O12R I/O13R I/O14R VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 33 11 34 10 35 9 36 8 37 7 38 6 39 5 40 4 41 3 42 70V24 2 PLG84(5) 43 1 44 84-Pin PLCC 84 Top View 45 83 46 82 47 81 48 80 49 79 50 78 51 77 52 76 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A5R I/O9R VSS I/O13L I/O12L I/O11L I/O10L I/O9L I/O8L I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VDD I/O2R I/O1R I/O0R VSS VDD I/O15L I/O14L Pin Configurations(1,2,3,4)(con't) 5624 drw 05 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL Output Enable OER (1) (1) A0L - A12L A0R - A12R (2) Address (2) I/O0L - I/O17L I/O0R - I/O17R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select(3) LBL LBR Lower Byte Select(4) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VDD Power (3.3V) VSS Ground (0V) NOTES: 1. A12 is a NC for IDT70V34 and for IDT70V24. 2. I/O0x - I/O15x for IDT70V25/24. 3. Upper Byte Select controls pins 9-17 for IDT70V35/34 and controls pins 8-15 for IDT70V25/24. 4. Lower Byte Select controls pins 0-8 for IDT70V35/34 and controls pins 0-7 for IDT70V25/24. 5624 tbl 01 Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs SEM I/O9-17(3) I/O0-8(2) X H High-Z High-Z Deselected: Power Down H H H High-Z High-Z Both Bytes Deselected X L H H DATAIN High-Z Write to Upper Byte Only L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATAOUT Read Lower Byte Only CE R/W OE UB LB H X X X X X X L L L Mode L H L L L H DATAOUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 5624 tbl 02 NOTES: 1. A0L-A12L ≠ A0R-A12R for IDT70V35/34 and A0L-A11L ≠ A0R-A11R for IDT70V25/24. 2. Outputs listed in the table are for IDT70V35/34. Outputs for IDT70V25/24 are I/O0x-I/O7x. 3. Outputs listed in the table are for IDT70V35/34. Outputs for IDT70V25/24 are I/O8x-I/O15x. Truth Table II: Semaphore Read/Write Control(1) Inputs Outputs CE R/W OE UB LB SEM I/O9-17(1) I/O0-8(1) H H L X X L DATAOUT DATA OUT Read Data in Semaphore Flag X H L H H L DATAOUT DATA OUT Read Data in Semaphore Flag H ↑ X X X L DATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ X H H L DATAIN DATAIN L X X L X L ____ ____ Not Allowed L X X X L L ____ ____ Not Allowed Mode Write I/O0 into Semaphore Flag 5624 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores are addressed by A0-A2. 6.42 5 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +4.6 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C TJN Junction Temperature +150 o C IOUT DC Output Current VTERM(2) Maximum Operating Temperature and Supply Voltage(1) Grade 50 Industrial COUT 0OC to +70OC 0V 3.3V + 0.3V -40OC to +85OC 0V 3.3V + 0.3V Parameter 5624 tbl 05 mA Capacitance(1) (TA = +25°C, f = 1.0MHz) (2) VDD NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. 5624 tbl 04 CIN GND Commercial NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. Symbol Ambient Temperature Conditions Max. Unit Input Capacitance VIN = 0V 9 pF Output Capacitance VOUT = 0V 10 pF Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V V VDD Supply Voltage VSS Ground VIH Input High Voltage 2.0 ____ VDD+0.3(2) VIL Input Low Voltage -0.3(1) ____ 0.8 V 5624 tbl 06 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VDD + 0.3V. 5624 tbl 07 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. COUT also references CI/O. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) Symbol |ILI| 70V35/34/25/24S 70V35/34/25/24L Min. Max. Min. Max. Unit VDD = 3.6V, VIN = 0V to VDD ___ 10 ___ 5 µA Parameter (1) Input Leakage Current (1) Test Conditions |ILO| Output Leakage Currentt CE = VIH, VOUT = 0V to VDD ___ 10 ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V 5624 tbl 08 NOTE: 1. At VDD < 2.0V leakages are undefined. 6.42 6 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34(1) (VDD = 3.3V ± 0.3V) 70V35/34X15 Com'l Only Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version 70V35/34X20 Com'l & Ind 70V35/34X25 Com'l Only Typ.(2) Max. Typ. (2) Max. Typ.(2) Max. Unit mA COM'L S L 150 140 215 185 140 130 200 175 130 125 190 165 IND S L ____ ____ 225 195 ____ ____ 140 130 ____ ____ ____ ____ COM'L S L 25 20 35 30 20 15 30 25 16 13 30 25 MIL & IND S L ____ ____ 45 40 ____ ____ 20 15 ____ ____ ____ ____ COM'L S L 85 80 120 110 80 75 110 100 75 72 110 95 MIL & IND S L ____ ____ 130 115 ____ ____ 80 75 ____ ____ ____ ____ Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VDD - 0.2V COM'L S L 1.0 0.2 5 2.5 1.0 0.2 5 2.5 1.0 0.2 5 2.5 MIL & IND S L ____ ____ 15 5 ____ ____ 1.0 0.2 ____ ____ ____ ____ CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) SEMR = SEML > VDD - 0.2V VIN > VDD - 0.2V or VIN < 0.2V Active Port Outputs Disabled, f = fMAX(3) COM'L S L 85 80 125 105 80 75 115 100 75 70 105 90 MIL & IND S L ____ ____ ____ ____ 80 75 130 115 ____ ____ ____ ____ CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CER and CEL = VIH SEMR = SEML = VIH f = fMAX(3) (5) CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH mA mA mA mA 5624 tbl 09 NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". AC Test Conditions Input Pulse Levels 3.3V 3.3V GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 590Ω 590Ω DATAOUT BUSY INT Figures 1 and 2 DATAOUT 435Ω 30pF 435Ω 5624 tbl 10 5624 drw 06 Figure 1. AC Output Test Load Figure 2. Output Test Load (For tLZ, tHZ, tWZ, tOW) *Including scope and jig. Timing of Power-Up Power-Down CE ICC 5pF* tPU tPD 50% 50% ISB 5624 drw 07 6.42 7 , 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V25/24(1) (VDD = 3.3V ± 0.3V) 70V24L15 Ind Only Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version CE = V IL, Outputs Open SEM = VIH f = fMAX(3) COM'L S L IND S L COM'L 70V25/24X15 Com'l Only 70V25/24X20 Com'l & Ind 70V25X25 Com'l & Ind 70V24X25 Com'l Only Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit ____ ____ ____ ____ 150 140 215 185 140 130 200 175 130 125 190 165 130 125 190 165 mA 140 130 225 195 ____ ____ ____ ____ 125 180 ____ ____ ____ ____ ____ ____ 140 205 ____ ____ S L ____ ____ ____ ____ 25 20 35 30 20 15 30 25 16 13 30 25 16 13 30 25 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 45 40 ____ 45 20 15 ____ 20 13 40 ____ ____ COM'L S L ____ ____ ____ ____ 85 80 120 110 80 75 110 100 75 72 110 95 75 72 110 95 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 130 115 ____ 125 80 75 ____ 80 72 110 ____ ____ Both Ports CEL and CER > V DD - 0.2V, VIN > V DD - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > V DD - 0.2V COM'L S L ____ ____ ____ ____ 1.0 0.2 5 2.5 1.0 0.2 5 2.5 1.0 0.2 5 2.5 1.0 0.2 5 2.5 MIL & IND S L 1.0 0.2 15 5 ____ ____ ____ ____ 0.2 5 ____ ____ CE"A" < 0.2V and CE"B" > V DD - 0.2V (5) SEMR = SEML > V DD - 0.2V VIN > V DD - 0.2V or V IN < 0.2V Active Port Outputs Open, f = fMAX(3) COM'L 105 90 75 70 105 90 MIL & IND CER and CEL = VIH SEMR = SEML = V IH f = fMAX(3) CE"A" = V IL and CE"B" = V IH Active Port Outputs Open, f=fMAX(3) SEMR = SEML = V IH (5) ____ ____ ____ ____ 0.2 5 ____ ____ S L ____ ____ ____ ____ 85 80 125 105 80 75 115 100 75 70 S L ____ ____ ____ ____ ____ ____ ____ ____ 130 115 ____ 120 80 75 ____ 80 70 105 ____ ____ mA mA mA mA 5624 tbl 09c 70V25/24X35 Com'l Only Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version 70V25/24X55 Com'l Only Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 120 115 180 155 120 115 180 155 IND S L ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 13 11 25 20 13 11 25 20 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Open, f=fMAX(3) SEMR = SEML = VIH COM'L S L 70 65 100 90 70 65 100 90 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VDD - 0.2V COM'L S L 1.0 0.2 5 2.5 1.0 0.2 5 2.5 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 65 60 100 85 65 60 100 85 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ CE = VIL, Outputs Open SEM = VIH f = fMAX(3) CER and CEL = VIH SEMR = SEML = VIH f = fMAX(3) CE"A" < 0.2V and CE"B" > VDD- 0.2V(5) SEMR = SEML > VDD - 0.2V VIN > VDD - 0.2V or VIN < 0.2V Active Port Outputs Open, f = fMAX(3) mA mA mA mA 5624 tbl 09b NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.42 8 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34(4) 70V35/34X15 Com'l Only Symbol Parameter 70V35/34X20 Com'l & Ind 70V35/34X25 Com'l Only Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 20 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tABE Byte Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns ____ 10 ____ 12 ____ 13 ns 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ ns ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ 0 ____ ns (3) tAOE Output Enable Access Time tOH Output Hold from Address Change (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) (1,2) tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time(1,2) ____ 15 ____ 20 ____ 25 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ 10 ____ ns tSAA Semaphore Address Access (3) ____ 15 ____ 20 ____ 25 ns 5624 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. 4. 'X' in part number indicates power rating (S or L). Waveform of Read Cycles(5) tRC ADDR (4) CE tAA (4) tACE tAOE (4) OE tABE (4) UB, LB R/W tLZ DATAOUT tOH (1) (4) VALID DATA tHZ (2) BUSYOUT tBDD (3,4) 5624 drw 08 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 6.42 9 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V25/24(4) 70V25/24X15 Com'l & Ind Symbol Parameter 70V25/24X20 Com'l & Ind 70V25X25 Com'l & Ind 70V24X25 Com'l Only Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ 25 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 20 ____ 25 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ____ 25 ____ 25 ns tABE Byte Enable Access Time(3) ____ 15 ____ 20 ____ 25 ____ 25 ns tAOE Output Enable Access Time(3) ____ 10 ____ 12 ____ 13 ____ 13 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 12 ____ 15 ____ 15 ns tPU Chip Enable to Power Up Time(1,2) 0 ____ 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(1,2) ____ 15 ____ 20 ____ 25 ____ 25 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ 10 ____ 10 ____ ns ____ 15 ____ 20 ____ 25 ____ 25 ns tSAA Semaphore Address Access (3) 5624 tbl 11d 70V25/24X35 Com'l Only Symbol Parameter 70V25/24X55 Com'l Only Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 ____ 55 ____ ns tAA Address Access Time ____ 35 ____ 55 ns tACE Chip Enable Access Time(3) ____ 35 ____ 55 ns tABE Byte Enable Access Time(3) ____ 35 ____ 55 ns tAOE Output Enable Access Time(3) ____ 20 ____ 30 ns tOH Output Hold from Address Change ns tLZ tHZ tPU Output Low-Z Time 3 ____ 3 ____ (1,2) 3 ____ 3 ____ ns (1,2) ____ 15 ____ 25 ns 0 ____ 0 ____ ns 35 ____ 50 ns 15 ____ ns ____ 55 ns Output High-Z Time Chip Enable to Power Up Time (1,2) (1,2) tPD Chip Disable to Power Down Time ____ tSOP Semaphore Flag Update Pulse (OE or SEM) 15 ____ ____ 35 tSAA Semaphore Address Access (3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. 4. 'X' in part number indicates power rating (S or L). 6.42 10 5624 tbl 11c 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage for 70V35/34 (5) 70V35/34X15 Com'l Only 70V35/34X20 Com'l & Ind 70V35/34X25 Com'l Only Min. Max. Min. Max. Min. Max. Unit 15 ____ 20 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns 0 ____ 0 ____ 0 ____ ns ns ns Symbol Parameter WRITE CYCLE tWC Write Cycle Time (3) tAS Address Set-up Time tWP Write Pulse Width 12 ____ 15 ____ 20 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ tDW Data Valid to End-of-Write 10 ____ 15 ____ 15 ____ ns tHZ Output High-Z Time (1,2) ____ 10 ____ 12 ____ 15 ns tDH Data Hold Time (4) 0 ____ 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1,2) ____ 10 ____ 12 ____ 15 ns tOW Output Active from End-of-Write (1,2,4) 0 ____ 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ 5 ____ ns 5624 tbl 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part number indicates power rating (S or L). 6.42 11 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage for 70V25/24 (5) 70V25/24X15 Com'l & Ind Symbol Parameter 70V25/24X20 Com'l & Ind 70V25X25 Com'l & Ind 70V24X25 Com'l Only Min. Max. Min. Max. Min. Max. Min. Max. Unit 15 ____ 20 ____ 25 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ 20 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ 20 ____ ns ns WRITE CYCLE Write Cycle Time tWC (3) tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ tWP Write Pulse Width 12 ____ 15 ____ 20 ____ 20 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ 15 ____ 15 ____ ns ____ 10 ____ 12 ____ 15 ____ 15 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 10 ____ 12 ____ 15 ____ 15 ns Output Active from End-of-Write 0 ____ 0 ____ 0 ____ 0 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ 5 ____ 5 ____ (1,2) Output High-Z Time tHZ Data Hold Time tDH (4) Write Enable to Output in High-Z tWZ (1,2) (1,2,4) tOW tSWRD tSPS ns 5624 tbl 12c 70V25/24X35 Com'l Only Symbol Parameter 70V25/24X55 Com'l Only Min. Max. Min. Max. Unit WRITE CYCLE 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ ns 0 ____ 0 ____ ns ns ns tWC Write Cycle Time (3) tAS Address Set-up Time tWP Write Pulse Width 25 ____ 40 ____ tWR Write Recovery Time 0 ____ 0 ____ tDW Data Valid to End-of-Write 15 ____ 30 ____ ns tHZ Output High-Z Time (1,2) ____ 15 ____ 25 ns tDH Data Hold Time (4) tWZ tOW tSWRD tSPS 0 ____ 0 ____ ns (1,2) ____ 15 ____ 25 ns (1,2,4) 0 ____ 0 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ Write Enable to Output in High-Z Output Active from End-of-Write ns 5624 tbl 12b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part number indicates power rating (S or L). 6.42 12 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM CE or SEM (9) (9) tAS (6) tWP (3) (2) tWR R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 5624 drw 09 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW (9) CE or SEM tAS (6) tWR (3) tEW (2) (9) UB or LB R/W tDW tDH DATAIN 5624 drw 10 NOTES: 1. R/W or CE or UB & LB must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. tEW must be met for either condition. 6.42 13 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tOH tSAA A0-A2 VALID ADDRESS tAW VALID ADDRESS tWR tACE tEW SEM tSOP tDW DATAIN VALID I/O0 tAS tWP DATAOUT VALID (2) tDH R/W tAOE tSWRD OE Write Cycle Read Cycle NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 5624 drw 12 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH. 2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. 6.42 14 5624 drw 11 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34(6) 70V35/34X15 Com'l Ony Symbol Parameter 70V35/34X25 Com'l Only 70V35/34X20 Com'l & Ind Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ns BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ns BUSY Access Time from Chip Enable LOW ____ 15 ____ 20 ____ 20 ns BUSY Disable Time from Chip Enable HIGH ____ 15 ____ 17 ____ 17 ns 5 ____ 5 ____ 5 ____ ns ____ 18 ____ 30 ____ 30 ns 12 ____ 15 ____ 17 ____ ns BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH Arbitration Priority Set-up Time (2) (3) BUSY Disable to Valid Data (5) Write Hold After BUSY BUSY TIMING (M/S = VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ 17 ____ ns ____ 30 ____ 45 ____ 50 ns ____ 25 ____ 35 ____ 35 ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) 5624 tbl 13 NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. 'X' in part number indicates power rating (S or L). Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH) tWC ADDR"A" MATCH tWP R/W"A" tDH tDW DATAIN "A" VALID tAPS (1) ADDR"B" MATCH tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID (3) tDDD NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”. 6.42 15 5624 drw 13 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V25/24(6) 70V25/24X15 Com'l & Ind Symbol Parameter 70V25/24X20 Com'l & Ind 70V25X25 Com'l & Ind 70V24X25 Com'l Only Min. Max. Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ____ 20 ns BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ____ 20 ns BUSY Access Time from Chip Enable LOW ____ 15 ____ 20 ____ 20 ____ 20 ns BUSY Disable Time from Chip Enable HIGH ____ 15 ____ 17 ____ 17 ____ 17 ns 5 ____ 5 ____ 5 ____ 5 ____ ns ____ 18 ____ 30 ____ 30 ____ 30 ns 12 ____ 15 ____ 17 ____ 17 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 12 ____ 15 ____ 17 ____ 17 ____ ns BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS Arbitration Priority Set-up Time tBDD BUSY Disable to Valid Data tWH Write Hold After BUSY(5) (2) (3) BUSY TIMING (M/S = VIL) BUSY Input to Write(4) tWB tWH Write Hold After BUSY (5) PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 30 ____ 45 ____ 50 ____ 50 ns tDDD Write Data Valid to Read Data Delay(1) ____ 25 ____ 35 ____ 35 ____ 35 ns 5624 tbl 13c 70V25/24X35 Com'l Only Symbol Parameter 70V25/24X55 Com'l Only Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 20 ____ 45 ns BUSY Disable Time from Address Not Matched ____ 20 ____ 40 ns BUSY Access Time from Chip Enable LOW ____ 20 ____ 40 ns tBDC BUSY Disable Time from Chip Enable HIGH ____ 20 ____ 35 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 35 ____ 40 ns 25 ____ 25 ____ ns 0 ____ 0 ____ ns 25 ____ 25 ____ ns ____ 60 ____ 80 ns ____ 45 ____ 65 BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tWH Write Hold After BUSY (5) BUSY TIMING (M/S = VIL) tWB tWH BUSY Input to Write (4) Write Hold After BUSY (5) PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ns 5624 tbl 13b NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. 'X' in part number indicates power rating (S or L). 6.42 16 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY tWP R/W"A" (3) tWB BUSY"B" tWH R/W"B" (1) (2) 5624 drw 14 , NOTES: 1. tWH must be met for both master BUSY input (slave) and output (master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the slave version. Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 5624 drw 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 5624 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 6.42 17 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V35/34(1) 70V35/34X15 Com'l Only Symbol Parameter 70V35/34X25 Com'l Only 70V35/34X20 Com'l & Ind Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 20 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 20 ____ 20 ns 5624 tbl 14 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range for 70V25/24(1) 70V25/24X15 Com'l & Ind Symbol Parameter 70V25/24X20 Com'l & Ind 70V25X25 Com'l & Ind 70V24X25 Com'l Only Min. Max. Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 20 ____ 20 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 20 ____ 20 ____ 20 ns 5624 tbl 14c 70V25/24X35 Com'l Only Symbol Parameter 70V25/24X55 Com'l Only Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 40 ns tINR Interrupt Reset Time ____ 25 ____ 40 ns 5624 tbl 14b NOTES: 1. 'X' in part number indicates power rating (S or L). 6.42 18 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing (1) tWC ADDR"A" INTERRUPT SET ADDRESS (2) (3) tAS tWR (4) CE"A" R/W"A" tINS (3) INT"B" 5624 drw 17 tRC INTERRUPT CLEAR ADDRESS ADDR"B" (2) tAS(3) CE"B" OE"B" tINR (3) INT"B" 5624 drw 18 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Flag Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 6.42 19 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table III — Interrupt Flag(1) Left Port R/WL CEL OEL L L X X X X A12L-A0L R/WR CER OER A12R-A0R(4) X X X X X X X L INTL 1FFF(4) X X X Right Port (4) X X L 1FFE X L L(2) Set Right INTR Flag (3) H Reset Right INTR Flag (4) X Set Left INTL Flag X Reset Left INTL Flag 1FFF L L X 1FFE (2) X X X X H Function (4) (3) L (4) L INTR 5624 tbl 15 NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. A12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE. Truth Table IV — Address BUSY Arbitration Inputs Outputs (4) CEL CER A12L-A0L A12R-A0R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H L L MATCH Note H (2) Note Normal (2) Write Inhibit(3) 5624 tbl 16 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A0 - A11. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) D0 - D17 Left(2) D0 - D17 Right(2) No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Functions Status 5624 tbl 17 NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24). 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables. 6.42 20 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM BUSYL CE SLAVE CE Dual Port SRAM BUSYR BUSYL BUSYR MASTER CE Dual Port SRAM BUSYR BUSYL SLAVE CE Dual Port SRAM BUSYR BUSYL DECODER MASTER Dual Port SRAM BUSYL Industrial and Commercial Temperature Ranges BUSYR 5624 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs. Functional Description The IDT70V35/34 (IDT70V25/24) provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V35/34 (IDT70V25/24) has an automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX) (FFE for IDT70V34 and IDT70V24), where a write is defined as the CER = R/WR = VIL per Truth Table III. The left port clears the interrupt on the IDT70V35 and IDT70V25 by an address location 1FFE (FFE for IDT70V34 and IDT70V24) access when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port interrupt flag (INTR) is set when the left port writes to memory location 1FFF for IDT70V35 and IDT70V25 (HEX) (FFF for IDT70V34 and IDT70V24) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF for IDT70V35 and IDT70V25 (FFF for IDT70V34 and IDT70V24). The message (16 bits) at 1FFE or 1FFF for IDT70V35 and IDT70V25 (FFE or FFF for IDT70V34 and IDT70V24) is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF for IDT70V35 and IDT70V25 (FFE and FFF for IDT70V34 and IDT70V24) are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70V35/34 (IDT70V25/24) SRAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these SRAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70V35/34 (IDT70V25/24) SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT70V35/34 (IDT70V25/24) SRAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT70V35/34 (IDT70V25/24) is an extremely fast Dual-Port 8/ 4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designer’s 6.42 21 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be accessed at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the nonsemaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT70V35/34 (IDT70V25/24) contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V35/ 34 (IDT70V25/24)'s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V35/34 (IDT70V25/24) does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V35/34 (IDT70V25/ 24) in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that 6.42 22 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V35/34 (IDT70V25/24)’s Dual-Port SRAM. Say the 8K x 18 SRAM was to be divided into two 4K x 18 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port SRAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port SRAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D SEMAPHORE REQUEST FLIP FLOP Q Q D WRITE D0 WRITE SEMAPHORE READ SEMAPHORE READ , 5624 drw 20 Figure 4. IDT70V35/34 (IDT70V25/24) Semaphore Logic 6.42 23 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Type Power Speed Package A A Industrial and Commercial Temperature Ranges A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green PF J 100-pin TQFP (PNG100) 70V35/34/25/24 84-Pin PLCC (PLG84) 70V24 15 15 20 25 35 55 Commercial Only - 70V35/34/25 Commercial & Industrial - 70V24 Industrial Only - 70V35/25/24 Industrial Only - 70V25 Commercial Only - 70V25/24 Commercial Only - 70V24 S L Standard Power Low Power , Speed in Nanoseconds 70V35 144K (8K x 18-Bit) 3.3V Dual-Port RAM 72K (4K x 18-Bit) 3.3V Dual-Port RAM 70V34 70V25 128K (8K x 16-Bit) 3.3V Dual-Port RAM 64K (4K x 16-Bit) 3.3V Dual-Port RAM 70V24 5624 drw 21 NOTES: 1. Contact your local sales office for Industrial temp range for other speeds, packages and powers. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 15 20 Speed (ns) Orderable Part ID Pkg. Code Pkg. Type Temp. Grade Speed (ns) 15 C PNG100 TQFP C 70V24L15JG PLG84 PLCC TQFP C 70V24L15JG8 PLG84 PLCC C 70V35L20PFGI PNG100 TQFP I 70V24L15PFG PNG100 TQFP C 70V35L20PFGI8 PNG100 TQFP I 70V24L15PFG8 PNG100 TQFP C 70V24L15PFGI PNG100 TQFP I 70V24L15PFGI8 70V34L15PFG PNG100 TQFP C 70V34L15PFG8 PNG100 TQFP C Pkg. Code Pkg. Type Temp. Grade 70V25L15PFG PNG100 TQFP C 70V25L15PFG8 PNG100 TQFP C 20 70V25L20PFGI PNG100 TQFP I 70V25L20PFGI8 PNG100 TQFP I 25 70V25L25PFGI PNG100 TQFP I 70V25L25PFGI8 PNG100 TQFP I Pkg. Code Pkg. Type Temp. Grade PNG100 TQFP I Speed (ns) Temp. Grade PNG100 Temp. Grade 15 Pkg. Type 70V35L15PFG8 Pkg. Type Speed (ns) Pkg. Code 70V35L15PFG Pkg. Code 15 Orderable Part ID Orderable Part ID Orderable Part ID Orderable Part ID 25 70V25S25PFGI 70V25S25PFGI8 PNG100 TQFP I 35 70V25S35PFG PNG100 TQFP C 20 35 Speed (ns) 55 6.42 24 PNG100 TQFP I 70V24L20JGI PLG84 PLCC I 70V24L20JGI8 PLG84 PLCC I 70V24L20PFGI PNG100 TQFP I 70V24L20PFGI8 PNG100 TQFP I 70V24L35PFG PNG100 TQFP C 70V24L35PFG8 PNG100 TQFP C Pkg. Code Pkg. Type Temp. Grade 70V24S55PFG PNG100 TQFP C 70V24S55PFG8 PNG100 TQFP C Orderable Part ID 70V35/34S/L (70V25/24S/L) High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 06/08/00: 08/09/01: 07/02/02: 06/22/04: 10/28/04: 04/05/05: 10/23/08: 08/26/15: 11/13/17: 11/13/17: 10/23/19: Initial Public Offering Page 1 Corrected I/O numbering Page 5-7, 10 & 12 Removed Industrial temperature range offering for 25ns from DC & AC Electrical Characteristics Page 17 Removed Industrial temperature range offering for 25ns speed from the ordering information Added Industrial temperature offering footnote Page 2 Added date revision for pin configuration Added 70V34 to datasheet (4K x 18) Consolidated 70V25/24 datasheets (8/4K x 16) into 70V35/34 (8/4K x 18) datasheet Removed Preliminary status from datasheet Page 2 & 3 Changed naming convention from VCC to VDD and from GND to VSS for PN100 packages Page 7 Updated Conditions in Capacitance table Page 7 Added Junction Temperature to Absolute Maximum Ratings table Page 9, 11, 13, 17 &, 19 Added DC and AC Electrical Characteristics tables for 70V25/24 data Page 21 & 22 Changed Interrupt flag table, footnotes and Interrupts text to reflect 70V25/24 data Page 1 & 15 Replaced old ® logo with new TM logo Page 25 Added stepping indicator to ordering information Page 1 Added green availability to features Page 25 Added green indicator to ordering information Page 25 Removed "IDT" from orderable part number Page 1 Updated the 70V25 & 70V24 high speed access offerings in Features, removed 70V24X25 industrial temp Page 2 Removed the IDT in reference to fabrication Pages 2, 3, 4 & 5 Removed the date from the PN100, G84 & J84 pin configurations Page 6 Updated footnotes 2 & 3 for Truth Table I: Non-Contention Read/Write Control Pages 9,11,13,17 & 19 Removed 25ns Industrial temp offering from the DC Chars and AC Chars tables for the 70V24 Page 25 Added Tape & Reel indicator and removed the stepping indicator from the ordering information Page 25 The package code for PN100-1 changed to PN100, G84-3 changed to G84 and J84-1 changed to J84 respectively in the ordering information to match the standard package codes Page 1, 2 & 4 G84 is no longer offered and it has been removed completely from the entire datasheet and specifically from the features, description and pin configuration Page 8 Added 70V24L15 Ind Only column and added the Typ. & Max data to this Ind speed grade offering only in the 70V25/24 DC Electrical Characteristics Table Page 8,10,12,16 & 18 Specifically updated all of the AC Electrical Characteristics Tables pertaining to 70V25/24X15 speed grade which includes both the Com'l and Ind temps for the READ CYCLE, WRITE CYCLE, and TIMING FOR BUSY, PORT-TO-PORT DELAY & INTERRUPT respectively Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Pages 1 & 24 Updated speed grade offerings Pages 2,3 & 4 Rotated PNG100 TQFP and PLG84 PLCC pin configurations to accurately reflect pin 1 orientation Page 24 Added Orderable Part Information table CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 25 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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