70V9199L9PFI

70V9199/099L HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9ns (max.) – Industrial: 9ns (max.) Low-power operation – IDT70V9199/099L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Dual chip enables allow for depth expansion without additional logic ◆ ◆ ◆ ◆ ◆ Counter enable and reset features Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9 ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66 MHz operation in Pipelined output mode LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) Green parts available, see ordering information Functional Block Diagram R/WR OER R/WL OEL CE0L CE1L FT/PIPEL 0/1 1 0 0 1 0/1 FT/PIPER . I/O0R - I/O8R(1) I/O0L - I/O8L(1) I/O Control I/O Control A16L A0L CLKL ADSL CNTENL CNTRSTL CE0R CE1R 1 0 0/1 1 0 0/1 A16R Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 4859 drw 01 NOTE: 1. I/O0X - I/O7X for IDT70V9099. JULY 2019 1 ©2019 Integrated Device Technology, Inc. DSC-4859/9 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Description: The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Industrial and Commercial Temperature Ranges With an input data register, the IDT70V9199/099 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 500mW of power. NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R VSS NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC Pin Configuration(1,2,3) 7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150 76 49 77 48 47 78 79 82 46 45 44 83 84 43 42 80 81 41 85 86 87 88 89 90 70V9199 PNG100(4) 100-Pin TQFP Top View 91 92 40 39 38 37 36 35 34 33 32 93 94 95 31 96 30 97 98 29 28 27 99 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L A16L VDD NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR VSS VSS ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.42 2 NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VDD I/O2R I/O1R I/O0R VSS VDD I/O0L I/O1L VSS I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L VSS 4859 drw 02 . 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R VSS NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER VSS NC Pin Configuration(1,2,3)(con't.) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 45 80 81 82 83 84 85 86 87 88 89 90 91 44 43 42 70V9099 PNG100(4) 41 40 39 38 100-Pin TQFP Top View 37 36 35 34 92 93 94 95 96 33 32 31 30 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L A16L VDD NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC NC NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR VSS ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.42 3 NC NC NC I/O7R I/O6R I/O5R I/O4R I/O3R VDD I/O2R I/O1R I/O0R VSS VDD I/O0L I/OIL VSS I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L NC VSS 4859 drw 02a 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A16L A0R - A16R (1) Address (1) I/O0L - I/O8L I/O0R - I/O8R Data Input/Output CLKL CLKR Clock ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through / Pipeline VDD Power (3.3V) VSS Ground (0V) NOTE: 1. I/O0X - I/O7X for IDT70V9099. 4859 tbl 01 Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 R/W I/O0-8(4) X ↑ H X X High-Z Deselected–Power Down X ↑ X L X High-Z Deselected–Power Down X ↑ L H L DATAIN Write L ↑ L H H DATAOUT Read H X L H X High-Z MODE Outputs Disabled 4859 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4. I/O0 - I/O7 for IDT70V9099. Truth Table II—Address Counter Control(1,2) External Address Previous Internal Address Internal Address Used CLK ADS CNTEN CNTRST I/O(3) X X 0 ↑ X X L(4) DI/O(0) Counter Reset to Address 0 MODE (4) An X An ↑ L X H DI/O(n) External Address Loaded into Counter An Ap Ap ↑ H H H DI/O(p) External Address Blocked—Counter disabled (Ap reused) H DI/O(p+1) X Ap Ap + 1 ↑ H (5) L Counter Enabled—Internal Address generation 4859 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. 6.42 4 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage(1) Grade Industrial Symbol Ambient Temperature(2) GND VDD 0OC to +70OC 0V 3.3V + 0.3V -40OC to +85OC 0V 3.3V + 0.3V Commercial NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 4859 tbl 04 VTERM(2) TBIAS(3) Parameter VDD Supply Voltage VSS Ground VIH Input High Voltage VIL Input Low Voltage Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +4.6 V Temperature Under Bias -55 to +125 TJN Junction Temperature IOUT DC Output Current o Symbol COUT(3) C -65 to +150 o C +150 o C 50 Max. Unit 3.0 3.3 3.6 V 0 0 0 2.0 ____ (1) -0.3 V VDD+0.3V ____ (2) V 0.8 V 4859 tbl 05 (TA = +25°C, f = 1.0MHZ) CIN Storage Temperature Typ. Capacitance(1) Rating TSTG Min. NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD +0.3V. Absolute Maximum Ratings(1) Symbol Industrial and Commercial Temperature Ranges Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 4859 tbl 07 mA 4859 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. 3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) 70V9199/099L Symbol Parameter Test Conditions (1) Min. Max. Unit 5 µA |ILI| Input Leakage Current VDD = 3.6V, VIN = 0V to VDD ___ |ILO| Output Leakage Current CE = VIH or CE1 = VIL, VOUT = 0V to VDD ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ V 4859 tbl 08 NOTE: 1. At VDD < 2.0V input leakages are undefined. 6.42 5 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V) 70V9199/099L9 Com'l & Ind Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Version 70V9199/099L12 Com'l Only Typ.(4) Max. Typ.(4) Max. Unit mA Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L L 175 230 150 200 IND L 180 240 ____ ____ Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH f = fMAX(1) COM'L L 40 65 30 50 IND L 50 70 ____ ____ Standby Current (One Port - TTL Level Inputs) COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) L 110 145 95 130 110 155 ____ ____ Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) COM'L L 0.4 2 0.4 2 IND L 0.4 2 ____ ____ Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L L 100 140 90 125 IND L 100 155 ____ ____ L mA mA mA mA 4859 tbl 09 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6.42 6 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1, 2, and 3 4859 tbl 10 3.3V 3.3V 590Ω 590Ω DATAOUT DATAOUT 30pF 435Ω 5pF* 435Ω 4859 drw 03 4859 drw 04 Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. Figure 1. AC Output Test load. 8 7 - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 4859 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 7 . 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V) 70V9199/099L9 Com'l & Ind Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 Parameter (2) Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined) (2) (2) Clock High Time (Flow-Through) (2) Clock Low Time (Flow-Through) (2) Clock High Time (Pipelined) (2) 70V9199/099L12 Com'l Only Min. Max. Min. Max. Unit 25 ____ 30 ____ ns 15 ____ 20 ____ ns 12 ____ 12 ____ ns 12 ____ 12 ____ ns 6 ____ 8 ____ ns 6 ____ 8 ____ ns tCL2 Clock Low Time (Pipelined) tR Clock Rise Time ____ 3 ____ 3 ns tF Clock Fall Time ____ 3 ____ 3 ns tSA Address Setup Time 4 ____ 4 ____ ns tHA Address Hold Time 1 ____ 1 ____ ns tSC Chip Enable Setup Time 4 ____ 4 ____ ns tHC Chip Enable Hold Time 1 ____ 1 ____ ns tSW R/W Setup Time 4 ____ 4 ____ ns tHW R/W Hold Time 1 ____ 1 ____ ns tSD Input Data Setup Time 4 ____ 4 ____ ns tHD Input Data Hold Time 1 ____ 1 ____ ns ADS Setup Time 4 ____ 4 ____ ns ADS Hold Time 1 ____ 1 ____ ns CNTEN Setup Time 4 ____ 4 ____ ns tHCN CNTEN Hold Time 1 ____ 1 ____ ns tSRST CNTRST Setup Time 4 ____ 4 ____ ns tHRST CNTRST Hold Time 1 ____ 1 ____ ns tOE Output Enable to Data Valid ____ 9 ____ 12 ns 2 ____ 2 ____ ns tSAD tHAD tSCN tOLZ tOHZ tCD1 (1) Output Enable to Output Low-Z (1) Output Enable to Output High-Z Clock to Data Valid (Flow-Through) (2) (2) 1 7 1 7 ns ____ 20 ____ 25 ns ____ 9 ____ 12 ns ns tCD2 Clock to Data Valid (Pipelined) tDC Data Output Hold After Clock High 2 ____ 2 ____ tCKHZ Clock High to Output High-Z(1) 2 9 2 9 ns tCKLZ Clock High to Output Low-Z(1) 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 35 ____ 40 ns tCCS Clock-to-Clock Setup Time ____ 15 ____ 15 ns 4859 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL. 6.42 8 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,6) tCYC1 tCH1 tCL1 CLK CE0 tSC tSC tHC tHC CE1 R/W tSW tHW tSA ADDRESS (5) tHA An An + 1 tCD1 DATAOUT An + 3 tCKHZ (1) Qn tCKLZ OE An + 2 tDC Qn + 1 Qn + 2 (1) (1) tOHZ tDC tOLZ (1) (2) .. tOE 4859 drw 06 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,6) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC (4) CE1 R/W (5) ADDRESS tSW tHW tSA tHA An An + 1 (1 Latency) An + 2 tDC tCD2 DATAOUT Qn tCKLZ(1) OE An + 3 Qn + 2(6) Qn + 1 tOHZ(1) tOLZ(1) (2) tOE 4859 drw 07 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. 'X' here denotes Left or Right port. The diagram is with respect to that port. 6.42 9 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA tHA A0 ADDRESS(B1) tSC tHC CE0(B1) tSC tHC Q0 DATAOUT(B1) tDC tCD2 Q3 Q1 tDC tCKLZ (3) tCKHZ (3) tHA A0 ADDRESS(B2) tCKHZ(3) tCD2 tCD2 tSA A6 A5 A4 A3 A2 A1 A6 A5 A4 A3 A2 A1 tSC tHC CE0(B2) tSC tHC tCD2 DATAOUT(B2) tCKHZ (3) Q2 tCKLZ(3) tCD2 tCKLZ (3) Q4 4859 drw 08 Timing Waveform with Port-to-Port Flow-Through Read(4,5,7) CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" NO MATCH MATCH tSD DATAIN "A" tHA tHD VALID tCCS (6) CLK "B" tCD1 R/W "B" ADDRESS "B" tSW tHW tSA tHA NO MATCH MATCH tCWDD (6) tCD1 DATAOUT "B" VALID VALID tDC tDC 4859 drw 09 NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9199/099 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0 and ADS = VIL; CE1 and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". 6.42 10 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD2 (2) tCKHZ (1) (1) tCD2 tCKLZ Qn + 3 Qn DATAOUT READ NOP (5) WRITE READ 4859 drw 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W ADDRESS (4) tSW tHW An tSA tHA An +1 An + 2 An + 3 An + 4 An + 5 tSD tHD DATAIN Dn + 3 Dn + 2 tCD2 (2) tCKLZ(1) tCD2 Qn DATAOUT Qn + 4 tOHZ(1) OE READ WRITE READ 4859 drw 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity. 6.42 11 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (2) tCD1 Qn DATAOUT tCD1 tCD1 Qn + 1 tDC tCKHZ READ NOP (1) (5) tCKLZ Qn + 3 tDC (1) READ WRITE 4859 drw 12 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW tSW tHW R/W (4) An tSA tHA ADDRESS An +1 DATAIN (2) DATAOUT An + 2 tSD tHD An + 3 Dn + 2 Dn + 3 tDC tCD1 Qn An + 4 tOE tCD1 (1) tOHZ (1) An + 5 tCKLZ tCD1 Qn + 4 tDC OE READ WRITE READ 4859 drw 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity. 6.42 12 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qn + 2(2) Qn + 1 Qn Qx Qn + 3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 4859 drw 14 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 tCYC1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 4859 drw 15 NOTES: 1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 13 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSAD tHAD ADS CNTEN(7) tSD tHD Dn + 1 Dn DATAIN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 4856 drw 16 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS(4) INTERNAL(3) ADDRESS Ax (6) 0 1 An + 2 An + 1 An An + 1 tSW tHW R/W ADS tSAD tHAD CNTEN tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 DATAIN DATAOUT(5) COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Qn Q1 Q0 (6) READ ADDRESS n READ ADDRESS n+1 4856 drw 17 NOTES: 1. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0 = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. 6.42 14 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Functional Description Depth and Width Expansion The IDT70V9199/099 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. CE0 = VIL and CE1 = VIH for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V9199/099's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIH or CE1 = VIL to reactivate the outputs. The IDT70V9199/099 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the varioius chip enables in order to expand two devices in depth. The IDT70V9199/099 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 18/16-bit or wider applications. A17 IDT70V9199/099 CE0 CE1 Control Inputs IDT70V9199/099 IDT70V9199/099 CE1 VDD VDD Control Inputs CE1 IDT70V9199/099 CE1 CE0 CE0 Control Inputs CE0 Control Inputs 4859 drw 18 Figure 4. Depth and Width Expansion with IDT70V9199/099 6.42 15 CNTRST CLK ADS CNTEN R/W OE 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX A 99 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank I (1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green PF 100-pin TQFP (PNG100) 9 Commercial & Industrial L Low Power Speed in nanoseconds 70V9199 1152K (128K x 9-Bit) Synchronous Dual-Port RAM 70V9099 1024K (128K x 8-Bit) Synchronous Dual-Port RAM 4859 drw 19 NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. IDT Clock Solution for IDT70V9199/099 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number 70V9199/099 Voltage 3.3 Dual-Port Clock Specifications Input Capacitance I/O LVTTL Input Duty Cycle Requirement 9pF 40% Maximum Frequency Jitter Tolerance 100 150ps IDT PLL Clock Devices IDT Non-PLL Clock Devices IDT2305 IDT2308 IDT2309 FCT3805 FCT3805D/E FCT3807 FCT3807D/E 4859 tbl12 Orderable Part Information Speed (ns) 9 Orderable Part ID 70V9199L9PFGI 70V9199L9PFGI8 Pkg. Code Pkg. Type Temp. Grade Speed (ns) PNG100 TQFP I 9 PNG100 TQFP I 6.42 16 Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 70V9099L9PFG PNG100 TQFP C 70V9099L9PFG8 PNG100 TQFP C 70V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 09/30/99: 11/12/99: 01/10/01: Page 3 Page 4 Page 5 04/09/03: Pages 2 & 3 Page 5 Pages 1, 6 & 16 Page 6 Page 8 01/10/06: 02/22/07: 01/19/09: 07/26/10: Page 16 Page 1 Page 16 Page 1 Page 6 Page 8 Page 16 Page 16 Page 8 Pages 9-12 03/01/18: 07/25/19: Page 1 & 16 Page 2 & 3 Page 2 & 3 Page 16 Initial Public Release Replaced IDT logo Changed information in Truth Table II Increased storage temperature parameters Clarified TA parameter DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Removed Preliminary status Consolidate multiple devices into one datasheet Changed naming conventions from VCC to VDD and from GND to VSS Added date revision to pin configurations Added junction temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Added 6ns speed grade Added updated DC power numbers to the DC Electrical Characteristics Table Added 6ns speed AC timing numbers and changed tOE to be equal to tCD2 in the AC Electrical CharacteristicsTable Added IDT Clock Solution Table Added green availability to features Added green indicator to ordering information Removed 6ns & 7ns speed grades from features Removed 6ns & 7ns speed grade values from the DC Electrical Characteristics Table Removed 6ns & 7ns speed grade values from the AC Electrical Characteristics Table Removed 6ns & 7ns speed grades from ordering information Removed "IDT" from orderable part number In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range values located in the table, the commercial TA header note has been removed In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the footnotes with the CNTEN logic definition found in Truth Table II - Address Counter Control Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Deleted obsolete Commercial speed grade12ns inFeatures and Ordering Information Rotated PNG100 TQFP pin configurations to accurately reflect pin 1 orientation Updated package code PN100-1 to PNG100 Added Orderable Part Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 17 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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