7134SA/LA
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
Features
◆
◆
◆
High-speed access
– Commercial: 20/55ns (max.)
– Industrial: 25ns (max.)
– Military: 35/45/55/70ns (max.)
Low-power operation
– IDT7134SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆
◆
◆
◆
◆
◆
Fully asynchronous operation from either port
Battery backup operation—2V data retention (LA only)
TTL-compatible; single 5V (±10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/WL
CEL
R/WR
CER
OEL
OER
I/O
CONTROL
I/O0L- I/O7L
A0L- A11L
ADDRESS
DECODER
I/O
CONTROL
MEMORY
ARRAY
I/O0R- I/O7R
ADDRESS
DECODER
A0R- A11R
2720 drw 01
1
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port arbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
The IDT7134 provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. It is the user’s responsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
Fabricated using CMOS high-performance technology, these DualPorts typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.
The IDT7134 is packaged in either a sidebraze or plastic 48-pin DIP,
48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade product is
manufactured in compliance with MIL-PRF-38535 QML, making it ideally
suited to military temperature applications demanding the highest level of
performance and reliability.
I/O4L
I/O5L
I/O6L
I/O7L
N/C
GND
A2L
A1L
A4L
A3L
A5L
A7L
A6L
A8L
I/O0L
A9L
7134
PLG52(4)
26
2
1
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
27
I/O5R
I/O6R
48
33
47
34 35 36 37 38 39 40 41 42 43 44 45 46
2
52-Pin PLCC
28
29
52
51
Top View
30
50
49
OER
31
32
A1R
A0R
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. PDG48 package body is approximately .55 in x 2.43 in x .18 in.
SB48 package body is approximately .62 in x 2.43 in x .15 in.
PLG52 package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of actual part-marking.
May.10. 21
24
25
A3R
A2R
2720 drw 02a
4
3
A5R
A4R
,
20 19 18 17 16 15 14 13 12 11 10 9 8
7
21
6
22
5
23
A7R
A6R
VCC
CER
R/WR
A11R
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
A9R
A8R
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I/O3L
1
2
3
4
5
7134
6
7
PDG48(4)
8
or
9
SB48(4)
10
11
12
13 48-Pin DIP
(5)
14 Top View
15
16
17
18
19
20
21
22
23
24
I/O7R
N/C
CEL
R/WL
A11L
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O 0L
I/O 1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
GND
I/O2L
I/O1L
Pin Configurations(1,2,3)
A0L
OEL
A10L
A11L
N/C
R/WL
CEL
VCC
CER
R/WR
N/C
A11R
A10R
2720 drw 03
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
I/O6R
5
6
21
20
19
7 8 9 10 11 12 13 14 15 16 17 18
I/O6L
I/O5L
I/O4L
I/O3L
2720 drw 04F
I/O3L
I/O4L
18 17 16 15 14 13 12 11 10 9 8 7
6
19
5
20
I/O5L
21
I/O6L
22
23
7134
LC48(4)
GND
I/O0R
I/O1R
I/O2R
24
25
48-Pin LCC
Top View
26
27
47
46
I/O3R
28
29
45
44
I/O7L
I/O4R
I/O5R
3
4
3
A0L
OEL
A10L
A11L
2
R/WL
CEL
48
VCC
CER
1
43
30
31 32 33 34 35 36 37 38 39 40 41 42
I/O6R
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. LC48 package body is approximately .57 in x .57 in x .68 in.
FP48 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
May.10. 21
A2L
A1L
3
4
A4L
A3L
23
22
A4R
A3R
A2R
A1R
A0R
1
I/O2R
I/O1R
I/O0R
GND
I/O7L
A9L
A8L
A7L
A6L
A5L
A6R
A7R
A8R
A9R
I/O7R
25
24
I/O3R
I/O2L
I/O1L
I/O0L
INDEX
48-Pin Flatpack
Top View
2
A1L
A2L
A3L
A0L
48
I/O5R
I/O4R
I/O7R
A9R
A8R
A7R
A6R
A5R
A11L
A10L
OEL
27
26
I/O1L
I/O2L
CEL
R/WL
7134
FP48(4)
46
47
I/O0L
CER
VCC
A8L
A9L
R/WR
29
28
44
45
A6L
A7L
A11R
42 41 40 39 38 37 36 35 34 33 32 31
30
43
A4L
A5L
OER
A10R
A2R
A3R
A4R
A5R
A0R
A1R
Pin Configurations (1,2,3)(con't.)
R/WR
A11R
A10R
OER
2720 drw 04L
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage(1,2)
Absolute Maximum Ratings(1)
Symbol
Commercial
& Industrial
Military
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
o
C
TSTG
Storage
Temperature
-65 to +150
-65 to +150
o
C
PT(3)
Power
Dissipation
1.5
1.5
W
IOUT
DC Output
Current
50
50
mA
VTERM(2)
Rating
Grade
Military
Ambient
Temperature
GND
Vcc
-55OC to +125OC
0V
5.0V + 10%
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
Commercial
Industrial
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2720 tbl 03
2720 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
3. VTERM = 5.5V.
Recommended DC Operating
Conditions
Symbol
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
11
pF
VOUT = 3dV
11
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
VIL
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
6.0(2)
V
____
0.8
(1)
Input Low Voltage
-0.5
V
2720 tbl 04
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
pF
2720 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5V ± 10%)
7134SA
Symbol
Parameter
(1)
Test Conditions
7134LA
Min.
Max.
Min.
Max.
Unit
10
___
5
µA
|ILI|
Input Leakage Current
VCC = 5.5V, VIN = 0V to V CC
___
|ILO|
Output Leakage Current
CE - VIH, VOUT = 0V to V CC
___
10
___
5
µA
VOL
Output Low Voltage
IOL = 6mA
___
0.4
___
0.4
V
IOL = 8mA
___
0.5
___
0.5
V
IOH = -4mA
2.4
___
2.4
___
V
VOH
Output High Voltage
2720 tbl 05
NOTES:
1. At Vcc < 2.0V input leakages are undefined.
4
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2) (VCC = 5.0V ± 10%)
7134X20
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = VIL
Outputs Disabled
f = fMAX(3)
CEL and CER = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(3)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
One Port CE"A" or
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
7134X25
Com'l & Ind
7134X35
Com'l
& Military
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
mA
COM'L
SA
LA
170
170
280
240
160
160
280
220
150
150
260
210
MIL &
IND
SA
LA
____
____
____
____
160
160
310
260
150
150
300
250
COM'L
SA
LA
25
25
100
80
25
25
80
50
25
25
75
45
MIL &
IND
SA
LA
____
____
____
____
25
25
100
80
25
25
75
55
COM'L
SA
LA
105
105
180
150
95
95
180
140
85
85
170
130
MIL &
IND
SA
LA
____
____
____
____
95
95
210
170
85
85
200
160
COM'L
SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
MIL &
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
SA
LA
105
105
170
130
95
95
170
120
85
85
160
110
MIL &
IND
SA
LA
____
____
____
____
95
95
210
150
85
85
190
130
mA
mA
mA
mA
2720 tbl 06a
7134X45
Com'l &
Military
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Version
7134X70
Com'l &
Military
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
CE = VIL
Outputs Disabled
f = fMAX(3)
COM'L
SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
MIL &
IND
SA
LA
140
140
280
240
140
140
270
220
140
140
270
220
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
COM'L
SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
MIL &
IND
SA
LA
25
25
70
50
25
25
70
50
25
25
70
50
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(3)
COM'L
SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
MIL &
IND
SA
LA
75
75
190
150
75
75
180
150
75
75
180
150
Full Standby Current
(Both Ports CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L
SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
Full Standby Current
(One Port CMOS Level Inputs)
One Port CE"A" or
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
MIL &
IND
SA
LA
75
75
180
120
75
75
170
120
75
75
170
120
Dynamic Operating
Current
(Both Ports Active)
Test Condition
7134X55
Com'l, Ind
& Military
mA
mA
mA
mA
2720 tbl 06b
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
5
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
___
___
V
µA
VDR
VCC for Data Retention
VCC = 2V
ICCDR
Data Retention Current
CE > VHC
MIL. & IND.
___
100
4000
VIN > VHC or < VLC
COM'L.
___
100
1500
0
___
___
ns
tRC(2)
___
___
ns
tCDR(3)
Chip Deselect to Data Retention Time
tR(3)
Operation Recovery Time
2720 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Data Retention Waveform
DATA RETENTION MODE
4.5V
VCC
4.5V
VDR ≥ 2V
tCDR
CE
tR
VDR
VIH
VIH
2720 drw 05
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1 and 2
2720 tbl 08
+5V
+5V
1250Ω
1250Ω
DATAOUT
775Ω
DATAOUT
30pF
775Ω
2720 drw 06 ,
2720 drw 07
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
6
May.10. 21
5pF *
,
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3)
7134X20
Com'l Only
Symbol
Parameter
7134X25
Com'l & Ind
7134X35
Com'l
& Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
ns
tAA
Address Access Time
____
20
____
25
____
35
ns
tACE
Chip Enable Access Time
____
20
____
25
____
35
ns
tAOE
Output Enable Access Time
____
15
____
15
____
20
ns
tOH
Output Hold from Address Change
0
____
0
____
0
____
ns
0
____
0
____
0
____
ns
____
15
____
15
____
20
ns
0
____
0
____
0
____
ns
____
20
____
25
____
35
ns
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time (1,2)
tPU
Chip Enable to Power Up Time (2)
Chip Disable to Power Down Time
tPD
(2)
2720 tbl 09a
Symbol
Parameter
7134X70
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X45
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
45
____
55
____
70
____
ns
tAA
Address Access Time
____
45
____
55
____
70
ns
tACE
Chip Enable Access Time
____
45
____
55
____
70
ns
tAOE
Output Enable Access Time
____
25
____
30
____
40
ns
tOH
Output Hold from Address Change
0
____
0
____
0
____
ns
tLZ
Output Low-Z Time (1,2)
5
____
5
____
5
____
ns
tHZ
(1,2)
____
20
____
25
____
30
ns
0
____
0
____
0
____
ns
____
45
____
50
____
50
ns
tPU
tPD
Output High-Z Time
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
7
May.10. 21
2720 tbl 09b
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
tAA(5)
tOH
tOH
PREVIOUS DATA VALID
DATAOUT
DATA VALID
2720 drw 08
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
tACE
CE
tHZ(2)
tAOE(4)
OE
tHZ(2)
tLZ(1)
VALID DATA(4)
DATAOUT
tLZ(1)
ICC
CURRENT
ISB
tPU
tPD
50%
50%
2720 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
8
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
7134X20
Com'l Only
Symbol
Parameter
7134X25
Com'l & Ind
7134X35
Com'l
& Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
20
____
25
____
35
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
30
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
15
____
20
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time
(1,2)
(3)
tDH
Data Hold Time
tWZ
Write Enable to Output in High-Z(1,2)
tOW
Output Active from End-of-Write (1,2,3)
tWDD
tDDD
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4)
15
____
15
____
20
____
ns
____
15
____
15
____
20
ns
0
____
0
____
3
____
ns
____
15
____
15
____
20
ns
3
____
3
____
3
____
ns
____
40
____
50
____
60
ns
____
30
____
30
____
35
ns
2720 tbl 10a
7134X45
Com'l &
Military
Symbol
Parameter
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
45
____
55
____
70
____
ns
tEW
Chip Enable to End-of-Write
40
____
50
____
60
____
ns
tAW
Address Valid to End-of-Write
40
____
50
____
60
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
40
____
50
____
60
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
25
____
30
____
ns
tHZ
Output High-Z Time (1,2)
____
20
____
25
____
30
ns
tDH
Data Hold Time (3)
tWZ
tOW
3
____
3
____
3
____
ns
(1,2)
____
20
____
25
____
30
ns
(1,2,3)
3
____
3
____
3
____
ns
____
70
____
80
____
90
ns
____
45
____
55
____
70
ns
Write Enable to Output in High-Z
Output Active from End-of-Write
(4)
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Delay (4)
2720 tbl 10b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
9
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read(1,2,3)
tWC
ADDR "A"
MATCH
tWP
tAW
(1)
R/W "A"
tDW
DATAIN "A"
VALID
MATCH
ADDR "B"
tWDD
VALID
DATAOUT "B"
tDDD
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2720 drw 10
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
OE
tAS(6)
tWR(3)
tAW
CE
tHZ (7)
(2)
tWP
R/W
(7)
tWZ
(7)
tLZ
DATAOUT
tOW
(4)
tHZ(7)
(4)
tDW
tDH
DATAIN
2720 drw 11
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
10
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4)
tWC
ADDRESS
tAW
CE
tAS(5)
tEW(2)
tWR(3)
R/W
tDW
tDH
DATAIN
2720 drw 12
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (CE or R/W) is asserted last.
Truth Table I – Read/Write Control
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (OE). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
inTruth Table I.
Left or Right Port(1)
R/W
CE
OE
D0-7
Function
X
H
X
Z
Port Deselected and in Power-Down
Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = H, Power Down
Mode ISB1 or ISB3
L
L
X
DATAIN
H
L
L
DATAOUT
X
X
H
Z
Data on port written into memory
Data in memory output on port
High impedance outputs
NOTE:
1. A0L - A11L ≠ A0R - A11R
"H" = VIH, "L" = VIL, "X" = Don’t Care, and "Z" = High Impedance
11
May.10. 21
2720 tbl 11
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
Device
Type
A
999
A
Power Speed Package
A
A
A
Process/
Temperature
Range
Blank
8
Tube
Tape and Reel
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
(2)
G
Green
P
C
J
L
F
48-pin Plastic DIP (PDG48)
48-pin Ceramic DIP (SB48)
52-pin PLCC (PLG52)
48-pin LCC (LC48)
48-pin Ceramic Flatpack (FP48)
20
25
35
45
55
70
Commercial Only
Industrial Only
Military Only
Military Only
Commercial & Military
Military Only
LA
SA
Low Power
Standard Power
7134
32K (4K x 8-Bit) Dual-Port RAM
Speed in nanoseconds
2720 drw 13
NOTES:
1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
LEAD FINISH (SnPb) parts are Obsolete excluding FP48, LC48 & SB48. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience.
Orderable Part Information
Speed
(ns)
20
25
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
7134LA20JG
PLG52
PLCC
C
35
7134LA20JG8
PLG52
PLCC
C
7134LA20PDG
PDG48
PDIP
C
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
7134SA35CB
SB48
SB
M
7134SA35L48B
LC48
LCC
M
45
7134SA45CB
SB48
SB
M
55
Orderable Part ID
7134LA25JGI
PLG52
PLCC
I
7134SA55CB
SB48
SB
M
7134LA25JGI8
PLG52
PLCC
I
7134SA55JG
PLG52
PLCC
C
7134LA25PDGI
PDG48
PDIP
I
7134SA55JG8
PLG52
PLCC
C
SB48
SB
M
7134SA55L48B
LC48
LCC
M
7134LA35FB
FP48
FPACK
M
7134SA70CB
SB48
SB
M
7134LA35L48B
LC48
LCC
M
7134SA70L48B
LC48
LCC
M
45
7134LA45CB
SB48
SB
M
55
7134LA55CB
SB48
SB
M
7134LA55L48B
LC48
LCC
M
7134LA70CB
SB48
SB
M
7134LA70L48B
LC48
LCC
M
35
70
7134LA35CB
70
12
May.10. 21
7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Datasheet Document History
03/25/99:
Pages 2
060/9/99:
10/01/99:
11/10/99:
12/22/99:
03/03/00:
01/12/00:
01/17/06:
08/12/08:
10/21/08:
01/16/13:
Page 1
Pages 1 2
Page 1
Page 2
Page 3
Page 4
Page 10
Page 1
Page 11
Page 1 & 11
Page 11
Page 11
Page 1, 4, 6 & 8
Page 11
10/21/08:
02/04/13:
Page 11
Page 1, 4, 6 & 8
Page 11
01/11/18:
05/10/21:
Page 2
Pages 1 - 14
Page 2 & 3
Page 2, 3 & 12
Page 12
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
Added Industrial Temperature Ranges and removed corresponding notes
Replaced IDT logo
Made corrections to drawing
Corrected block diagram and pin configurations
Changed ±500mV to 0mV
Moved "Description to page 2 and adjusted page layout
Added "LA only)" to paragraph
Fixed P48-1 package description
Increased storage temperature parameters
Clarified TA parameter
DC Electrical parameters–changed wording from "open" to "disabled"
Fixed Truth Table specification in "Functional Description" paragraph
Added green availability to features
Added green indicator to ordering information
Replaced old IDTTM with new IDTTM logo
Corrected typo in the ordering information
Removed "IDT" from orderable part number
Removed Military 25ns & Industrial 35ns speed grades from Features and corrected
the headers of the DC Chars and AC Chars tables to indicate this change
Added T& R indicator to and removed Military 25ns & Industrial 35ns speed grades from the
ordering information
Removed "IDT" from orderable part number
Removed Military 25ns & Industrial 35ns speed grades from Features and corrected
the headers of the DC Chars and AC Chars tables to indicate this change
Added T& R indicator to and removed Military 25ns & Industrial 35ns speed grades from the
ordering information
Typo/correction
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Rebranded as Renesas datasheet
Rotated LC48 LCC, FP48 Flatpack & PLG52 PLCC to accurately reflect pin 1 orientation
Updated package codes
Added Orderable Part Information tables
13
May.10. 21
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
工商网监
湘ICP备2023018690号
