74ALVCH162244PAG8

IDT74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH162244 DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V μ W typ. static) • CMOS power levels (0.4μ • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package This 16-bit buffer/driver is built using advanced dual metal CMOS technology. The ALVCH162244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. The ALVCH162244 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162244 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Low switching noise APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 25 1OE 1 1A1 47 2 1Y1 3A1 36 13 1A2 46 3 1Y2 3A2 35 14 3Y2 1A3 44 5 1Y3 3 A3 33 16 3Y3 43 6 1Y4 3A4 32 17 3Y4 30 19 4Y1 29 20 4Y2 1A4 3OE 3Y1 24 2OE 48 2A1 41 8 2Y1 4A1 2A2 40 9 2Y2 4A2 2A3 38 11 2Y3 4A3 27 22 4Y3 2A4 37 12 2Y4 4A4 26 23 4Y4 4OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2016 1 © 2016 Integrated Device Technology, Inc. DSC-4562/6 IDT74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit VTERM(3) Terminal Voltage with Respect to GND –0.5 to +4.6 V Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V 1OE 1 48 2OE TSTG Storage Temperature –65 to +150 °C 1Y1 2 47 1A1 IOUT DC Output Current –50 to +50 mA 1Y2 3 46 1A2 IIK ±50 mA GND 4 45 Continuous Clamp Current, VI < 0 or VI > VCC GND IOK Continuous Clamp Current, VO < 0 –50 mA 1Y3 5 44 1A3 mA 6 43 1A4 Continuous Current through each VCC or GND ±100 1Y4 ICC ISS VCC 7 42 VCC 2Y1 8 41 2A1 2Y2 9 40 2A2 GND 10 39 GND 2Y3 11 38 2A3 2Y4 12 37 2A4 3Y1 13 36 3A1 Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF 3Y2 14 35 3A2 GND 15 34 GND 3Y3 16 33 3A3 3Y4 17 32 3A4 VCC 18 31 VCC 4Y1 19 30 4A1 4Y2 20 29 4A2 GND 21 28 GND 4Y3 22 27 4A3 4Y4 23 26 4A4 4OE 24 25 3OE NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description xOE 3-State Output Enable Inputs (Active LOW) xAx Data Inputs(1) xYx 3-State Outputs NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH 4-BIT BUFFER)(1) TSSOP TOP VIEW Inputs xOE xAx xYx L H H L L L H X Z NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2 Outputs IDT74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 μA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 μA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 μA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV μA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 μA Min. Typ.(2) Max. Unit – 75 — — μA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V VI = 2V VI = 0.8V 75 — — Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 — — VI = 0.7V 45 — — Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 IBHL IBHH IBHL IBHHO IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 μA μA IDT74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.7V IOH = – 8mA 2 — VCC = 3V IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 VCC = 2.7V IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 VCC = 3V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 16 19 pF 4 5 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter tPLH Propagation Delay tPHL xAx to xYx tPZH Output Enable Time tPZL xOE to xYx tPHZ Output Disable Time tPLZ xOE to xYx tSK(o) Output Skew(2) VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 1 4.9 — 4.7 1 4.2 ns 1 6.8 — 6.7 1 5.6 ns 1 6.3 — 5.7 1 5.5 ns — — — — — 500 ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) VIN VIH VT 0V ALVC Link DISABLE ENABLE GND tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL ALVC Link Test Circuit for All Outputs tPHL CONTROL INPUT D.U.T. RT tPLH Propagation Delay VOUT Pulse Generator tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VIH VT 0V VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Switch Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open OUTPUT 1 tPLH1 tSU tH Set-up, Hold, and Release Times VIH VT 0V VOH VT VOL tSK (x) LOW-HIGH-LOW PULSE OUTPUT 2 VT tW VOH VT VOL tPLH2 tREM ALVC Link tPHL1 tSK (x) tH TIMING INPUT Test INPUT tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX ALVC X Bus-Hold Temp. Range XX Family XXX XX Device Type Package X Blank 8 Tube Tape and Reel PAG Thin Shrink Small Outline Package - Green 244 16-Bit Buffer/Driver with 3-State Outputs 162 Double-Density with Resistors, ±12mA H Bus-Hold 74 -40°C to +85°C Datasheet Document History 09/19/2016 Pgs. 1,2, and 6 Updated the ordering information by removing SSOP package and adding Tape and Reel. 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