74ALVC162244PAG

IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V μ W typ. static) • CMOS power levels (0.4μ • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package This 16-bit buffer/driver is built using advanced dual metal CMOS technology. The ALVC162244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. The ALVC162244 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. DRIVE FEATURES: APPLICATIONS: • Balanced Output Drivers: ±12mA • Low switching noise • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 25 1OE 1 1A1 47 2 1Y1 3A1 36 13 1A2 46 3 1Y2 3A2 35 14 3Y2 1A3 44 5 1Y3 3A3 33 16 3 Y3 43 6 1Y4 3A4 32 17 3Y4 1A4 3OE 2OE 48 2A1 41 8 2A2 40 9 2A3 38 11 2A4 37 12 3Y1 4OE 24 2Y1 4A1 30 19 4Y1 2Y2 4A2 29 20 4Y 2 2Y3 4A3 27 22 4Y3 2Y4 4A4 26 23 4Y4 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2009 1 © 2009 Integrated Device Technology, Inc. DSC-4560/6 IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit VTERM(3) Terminal Voltage with Respect to GND –0.5 to +4.6 V Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA 1OE 1 48 2OE 1Y1 2 47 1A1 1Y2 3 46 1A2 GND 4 45 GND 1Y3 5 44 1A3 1Y4 6 43 1A4 VCC 7 42 VCC 2Y1 8 41 2A1 2Y2 9 40 2A2 GND 10 39 GND 2Y3 11 38 2A3 2Y4 12 37 2A4 3Y1 13 36 3A1 Symbol Conditions Typ. Max. Unit 3Y2 14 35 3A2 CIN Input Capacitance VIN = 0V 5 7 pF GND 15 34 GND COUT Output Capacitance VOUT = 0V 7 9 pF COUT I/O Port Capacitance VIN = 0V 7 9 pF 3Y3 16 33 3A3 3Y4 17 32 3A4 VCC 18 VCC 4Y1 19 3 1 30 4Y2 20 29 4A2 GND 21 28 GND 4Y3 22 27 4A3 4Y4 23 26 4A4 4OE 24 25 3OE NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) NOTE: 1. As applicable to the device type. PIN DESCRIPTION 4A1 Pin Names Description xOE 3-State Output Enable Inputs (Active LOW) xAx Data Inputs xYx 3-State Outputs FUNCTION TABLE (EACH 4-BIT BUFFER)(1) TSSOP TOP VIEW Inputs xOE xAx xYx L H H L L L H X Z NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2 Outputs IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — IOH = – 8mA 2 — IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 VCC = 2.7V VCC = 3V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 16 19 pF 4 5 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter tPLH Propagation Delay tPHL xAx to xYx tPZH Output Enable Time tPZL xOE to xYx tPHZ Output Disable Time tPLZ xOE to xYx tSK(o) Output Skew(2) VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 1 4.9 — 4.7 1 4.2 ns 1 6.8 — 6.7 1 5.6 ns 1 6.3 — 5.7 1 5.5 ns — — — — — 500 ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF tPLH tPHL tPLH tPHL OUTPUT VIH VT 0V OPPOSITE PHASE INPUT TRANSITION ALVC Link Propagation Delay VLOAD VCC Open (1, 2) Pulse Generator VIN DISABLE ENABLE GND 500Ω CONTROL INPUT VOUT D.U.T. tPZL VLOAD/2 OUTPUT SWITCH VT NORMALLY CLOSED LOW tPHZ tPZH OUTPUT SWITCH NORMALLY VT OPEN HIGH 0V 500Ω RT tPLZ CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. VIH VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V ALVC Link Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test Switch TIMING INPUT Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH tREM tSU tH ALVC Link INPUT OUTPUT 1 tPLH1 VIH VT 0V tPHL1 tSK (x) tSK (x) OUTPUT 2 tPLH2 Set-up, Hold, and Release Times VOH VT VOL LOW-HIGH-LOW PULSE VOH VT VOL HIGH-LOW-HIGH PULSE tW tPHL2 VT ALVC Link Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) VT ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVC162244 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX ALVC X Bus-Hold Temp. Range XX Family XXX XX Device Type Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 PAG Thin Shrink Small Outline Package - Green 244 16-Bit Buffer/Driver with 3-State Outputs 162 Double-Density with Resistors, ±12mA Blank No Bus-Hold 74 – 40°C to +85°C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 6 for Tech Support: logichelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.