74LVCH162245APAG8

IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD IDT74LVCH162245A DESCRIPTION: FEATURES: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit transceivers or one 16-bit transceiver. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH162245A (B port) has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH162245 (A port) has series resistors in the device output structure which will significantly reduce line noise when used with light loads. The driver has been designed to drive ±12mA at the designated threshold levels. The LVCH162245A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • All inputs, outputs, and I/O are 5V tolerant • Available in TSSOP package DRIVE FEATURES: • Balanced Output Drivers: ±12mA (A port) • High Output Drivers: ±24mA (B port) APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1DIR 24 1 2DIR 25 48 1OE 1A1 2OE 47 2A1 2 36 13 1B1 1A2 2A2 3 14 1B2 1A3 44 2A3 16 1B3 2B3 32 43 2A4 6 17 1B4 1A5 2B4 41 2A5 30 8 19 1B5 1A6 40 2A6 20 1B6 38 2A7 22 1B7 2B7 37 2A8 12 2B6 27 11 1A8 2B5 29 9 1A7 2B2 33 5 1A4 2B1 35 46 26 23 1B8 2B8 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 © 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. OCTOBER 2015 DSC-4597/5 IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C 1DIR 1 48 1OE IOUT DC Output Current –50 to +50 mA 1B1 2 47 1A1 mA 3 46 Continuous Clamp Current, VI < 0 or VO < 0 –50 1B2 IIK IOK 1A2 GND GND Continuous Current through each VCC or GND mA 45 ICC ISS ±100 4 1B3 5 44 1A3 43 1A4 1B4 6 VCC 7 42 VCC 1B5 8 41 1A5 1B6 9 40 1A6 GND 10 39 GND 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 14 35 2A2 GND 15 34 GND 2B3 16 33 2A3 2B4 17 32 2A4 VCC 18 31 VCC 2B5 19 30 2A5 2B6 20 29 2A6 GND 21 28 GND 2B7 22 27 2A7 2B8 23 26 2A8 2DIR 24 25 2OE NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. CIN Input Capacitance VIN = 0V 4.5 6 Unit pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description xOE Output Enable Input (Active LOW) xDIR Direction Control Output xAx Side A Inputs or 3-State Outputs(1) xBx Side B Inputs or 3-State Outputs(1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH 8-BIT SECTION)(1) Inputs TSSOP TOP VIEW xOE xDIR L L B Data to A Bus L H A Data to B Bus H X High Z State NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2 Outputs IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 μA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 μA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 μA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV μA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 μA Min. Typ.(2) Max. Unit – 75 — — μA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V VI = 2V VI = 0.8V 75 — — Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V — — — VI = 0.7V — — — VI = 0 to 3.6V — — ±500 IBHL IBHH IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 μA μA IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS (A PORT) Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — VCC = 2.7V IOH = – 4mA 2.2 — IOH = – 8mA 2 — IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 VCC = 3V VOL Min. VCC = 2.7V VCC = 3V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OUTPUT DRIVE CHARACTERISTICS (B PORT) Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA VCC = 2.3V IOH = – 12mA VCC = 2.7V VCC = 3V VOL Output LOW Voltage Min. Max. Unit VCC – 0.2 — V 2 — 1.7 — 2.2 — 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 4 IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Transceiver Outputs enabled CPD Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 39 pF 4 SWITCHING CHARACTERISTICS (A PORT)(1) Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xBx to xAx Output Enable Time xOE to xAx Output Disable Time xOE to xAx Output Skew(2) Min. 1.5 VCC = 2.7V Max. 5.7 VCC = 3.3V ± 0.3V Min. Max. 1.5 4.8 Unit ns 1.5 7.9 1.5 6.3 ns 1.5 8.3 2.2 7.4 ns — — — 500 ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. SWITCHING CHARACTERISTICS (B PORT)(1) Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xBx Output Enable Time xOE to xBx Output Disable Time xOE to xBx Output Skew(2) Min. 1.5 NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 5 VCC = 2.7V Max. 4.7 VCC = 3.3V ± 0.3V Min. Max. 1 4 Unit ns 1.5 6.7 1.5 5.5 ns 1.5 7.1 1.5 6.6 ns — — — 500 ps IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500 CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500 tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74LVCH162245A 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package X Blank 8 Tube or Tray Tape and Reel PAG PFG Thin Shrink Small Outline Package - Green Thin Very Small Outline Package - Green 245A 16-Bit Bus Transceiver 162 Double-Density with Resistors, ±24mA (B Port) ±12mA (A Port) H Bus-hold 74 -40°C to +85°C DATASHEET DOCUMENT HISTORY 10/06/2015 Pg. 1 ,2, 7 Updated the ordering information by removing IDT notation, non RoHS parts and adding Tape and Reel information. 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