Jitter Attenuator & FemtoClock NG® Multiplier
810N322I-02
Datasheet
General Description
Features
The 810N322I-02 device uses IDT's fourth generation FemtoClock®
NG technology for optimal high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The 810N322I-02 is a PLL based
synchronous multiplier that is optimized for Ethernet to SONET/PDH
clock jitter attenuation and frequency translation.
•
•
•
Fourth generation FemtoClock® NG technology
•
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
The 810N322I-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 9Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports commercial temperature range.
•
Accepts input frequencies from 8kHz to 156.25MHz including
8kHz,19.44MHz, 25MHz, 62.5MHz, 77.76MHz, 125MHz,
155.52MHz and 156.25MHz
•
•
Crystal interface designed for a 27MHz, 10pF crystal
•
Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
•
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
•
•
•
•
Absolute pull range: ±50ppm
•
•
•
3.3V supply voltage
Pin Assignment
27 26
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
Power supply noise rejection (PSNR): -55 (typical)
FemtoClock NG VCXO frequency: 2488.32MHz
RMS phase jitter @ 155.52MHz, using a 27MHz crystal
(12kHz – 20MHz):0.624ps (typical)
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
25
LF1
1
24
GND
LF0
2
23
nc
ISET
3
22
QB
GND
4
21
V DDO
CLK_ SEL
5
20
nc
17
ODASEL_0
9
10
11
12 13
14
15
16
ODASEL_1
8
ODBSEL_0
GND
ODBSEL_1
GND
VDD
QA
18
PDSEL_1
19
7
PDSEL_0
6
PDSEL_2
V DD
RESERVED
VDDA
Each output supports independent frequency selection at
19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz
nCLK1
VDD
29 28
CLK1
CLK0
30
nCLK0
XTAL_IN
31
XTAL_OUT
VDDX
32
Two LVCMOS outputs
810N322I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Block Diagram
27MHz
Pulldown
DIGITAL
VCXO
Xtal
Osc.
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
PD
+
LF
Pulldown
0
Pullup/
Pulldown
÷P
Pulldown
1
Pullup/
Pulldown
Phase
Detector
+
Charge
Pump
ODASEL_[1:0]
÷NA
QA
÷NB
QB
FemtoClockÒ NG
VCO
Fractional
Feedback
Divider
Pulldown
2
2
Pulldown
ODBSEL_[1:0]
A/D Control
Block
÷M
LF1
3
LF0
Pullup
ISET
PDSEL_[2:0]
CP
RSET
RS
CS
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins. LF0 is the output. LF1 is the input.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4, 8, 18, 24
GND
Power
5
CLK_SEL
Input
6, 12, 27
VDD
Power
7
RESERVED
Reserve
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input
13
VDDA
Power
14,
15
ODBSEL_1,
ODBSEL_0
Input
Pulldown
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input
Pulldown
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
19
QA
Output
Single-ended Bank A clock output. LVCMOS/LVTTL interface levels.
20, 23
nc
Unused
No connect.
21
VDDO
Power
Output supply pin.
22
QB
Output
Single-ended Bank B clock output. LVCMOS/LVTTL interface levels.
25
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 bias voltage when left floating.
26
CLK1
Input
Pulldown
Non-inverting differential clock input.
28
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 bias voltage when left floating.
29
CLK0
Input
Pulldown
Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32
VDDX
Power
Power supply pin for VCXO charge pump.
Power supply ground
Pulldown
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Reserved pin.
Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Analog supply pin. When LOW bypass the PLL (for testing purposes only).
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
3.5
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
CPD
Power Dissipation Capacitance
(per output)
8
pF
ROUT
Output Impedance
8
©2016 Integrated Device Technology, Inc.
Test Conditions
VDD, VDDO = 3.465V
3
Minimum
Typical
Maximum
Units
Revision B, February 25, 2016
810N322I-02 Datasheet
Function Tables
Table 3A. Pre-Divider Selection Function Table
Inputs
PDSEL_2
PDSEL_1
PDSEL_0
Pre-Divider Value
0
0
0
1
0
0
1
1944
0
1
0
2500
0
1
1
6250
1
0
0
7776
1
0
1
12500
1
1
0
15552
1
1
1
15625 (default)
Table 3B. Output Divider Function Table
Inputs
ODxSEL_1
ODxSEL_0
Output Divider Value
0
0
128 (default)
0
1
32
1
0
16
1
1
4
NOTE: ODxSEL denotes ODASEL or ODBSEL.
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Table 3C. Example Configurations for Selected Output and Input Frequencies
User Configuration and Frequencies
Input
Frequency
(MHz)
Output
Frequency
(MHz)
PDSEL
[2:0]
ODxSEL
[1:0]
622.08
Pre
Divider
P
Feedback
Divider
M
Fractional
Feedback
Divider
FemtoClock
NG
FemtoClock NG
VCO Frequency
(MHz)
11
155.52
0.008
Internal Divider Values and Frequencies
4
10
16
1
000
Output
Divider Nx
128
2430
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
19.44
10
16
1944
001
128
1944
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
25
10
16
2500
010
128
1944
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
62.5
10
011
16
6250
128
1944
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
77.76
10
16
7776
100
128
1944
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
125
10
16
12500
101
128
1944
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
155.52
10
16
15552
110
128
1944
2488.32
77.76
01
32
19.44
11
128
622.08
11
4
155.52
156.25
10
16
15625
111
128
1944
2488.32
77.76
01
32
19.44
11
128
NOTE: ODxSEL denotes ODASEL or ODBSEL.
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VDD+ 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, JA
33.1C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.30
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
VDDX
Charge Pump Supply Voltage
3.135
3.3
3.465
V
IDD +
IDDX
Power Supply Current
220
mA
IDDA
Analog Supply Current
VDDA = High
30
mA
IDDO
Output Supply Current
VDDA = Low
PDSEL [2:0] = 0, ODxSEL[1:0] = 1
12
mA
Maximum
Units
PLL Mode
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
VDD = VIN = 3.465V
150
µA
PDSEL_[2:0]
VDD = VIN = 3.465V
5
µA
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
PDSEL_[2:0]
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
©2016 Integrated Device Technology, Inc.
VDD = 3.465V, VIN = 0V
-5
µA
VDD = 3.465, VIN = 0V
-150
µA
2.6
V
0.5
6
V
Revision B, February 25, 2016
810N322I-02 Datasheet
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagram.
Table 4C. Differential DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND
VDD – 0.85
V
Maximum
Units
CLK0, nCLK0,
CLK1, nCLK1
Minimum
Typical
VDD = VIN = 3.465V
Maximum
Units
150
µA
CLK0, CLK1
VDD = 3.465V, VIN = 0V
-5
µA
nCLK0, nCLK1
VDD = 3.465V, VIN = 0V
-150
µA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2. Common mode voltage is defined at the crosspoint.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fIN
Input Frequency
0.008
156.25
MHz
fOUT
Output Frequency
19.44
622.08
MHz
tjit(Ø)
RMS Phase Jitter, (Random),
NOTE 1
155.52MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.624
ps
PSNR
Power Supply Noise Rejection
1kHz - 10MHz
-55
dB
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
Output-to-Input Phase
Lock Time; NOTE 4
Test Conditions
Minimum
Typical
80
ps
20% to 80%
185
665
ps
fOUT 155.52MHz
47
53
ps
fOUT 622.08MHz
40
60
ps
Reference Clock Input is ±50ppm
from Nominal Frequency
6.5
s
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth.
Refer to Jitter Attenuator Loop Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Lock Time measured from power-up to stable output frequency.
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Noise Power dBc
Hz
Typical Phase Noise at 155.52MHz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Parameter Measurement Information
1.65V ±5%
1.65V ±5%
VDD,
VDDO,
VDDX
VDD
SCOPE
nCLK[0:1]
VDDA
Qx
V
Cross Points
PP
CLK[0:1]
V
CMR
GND
GND
-1.65 ±5%
Output Load AC Test Circuit
Differential Input Level
Output-to-Input Phase Lock Time
RMS Phase Jitter
V
DDOX
Qx
2
V
Qy
QA, QB
DDOX
80%
80%
tR
tF
2
tsk(o)
Output Skew
20%
20%
Output Rise/Fall Time
V
DDO
2
QA, QB
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
Jitter Attenuator External Components
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation of
the Jitter Attenuator. In choosing a crystal, special precaution must
be taken with load capacitance (CL), frequency accuracy and
temperature range.
the PCB parasitics or if using a crystal with a higher CL specification.
In addition, the frequency accuracy specification in the crystal
characteristics table are used to calculate the APR (Absolute Pull
Range).
LF0
LF1
ISET
The crystal’s CL characteristic determines its resonating frequency
and is closely related to the center tuning of the crystal. The total
external capacitance seen by the crystal when installed on a PCB is
the sum of the stray board capacitance, IC package lead
capacitance, internal device capacitance and any installed tuning
capacitors (CTUNE). The recommended CLin the Crystal Parameter
Table balances the tuning range by centering the tuning curve for a
typical PCB. If the crystal CL is greater than the total external
capacitance, the crystal will oscillate at a higher frequency than the
specification. If the crystal CL is lower than the total external
capacitance, the crystal will oscillate at a lower frequency than the
specification. Tuning adjustments might be required depending on
RS
CP
RSET
CS
XTAL_IN
CTUNE
3.3pF
27MHz
XTAL_OUT
CTUNE
3.3pF
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
fN
Frequency
fT
Frequency Tolerance
±20
ppm
fS
Frequency Stability
±20
ppm
+85
0C
Mode of Oscillation
Typical
Maximum
Units
Fundamental
27
Operating Temperature Range
MHz
-40
CL
Load Capacitance
10
pF
CO
Shunt Capacitance
4
pF
ESR
Equivalent Series Resistance
Aging @ 25
0C
First Year
40
±3
ppm
Jitter Attenuator Characteristics Table
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP
and RSET values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. In addition, the digital VCXO gain (KVCXO) has been
provided for additional loop filter requirements.
Symbol
Parameter
Typical
Units
kVCXO
VCXO Gain
2.78
kHz/V
Jitter Attenuator Loop Bandwidth Selection Table (2ND Order Loop Filter)
Bandwidth
Crystal Frequency
RS (k)
CS (µF)
CP (µF)
R3 (k)
C3 (µF)
RSET (k)
15Hz (Low)
27MHz
215
10
0.022
0
DEPOP
2.74
30Hz (Mid)
27MHz
365
2.2
0.0047
0
DEPOP
2.74
60Hz (High)
27MHz
470
1
0.0022
0
DEPOP
1.5
NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET.
©2016 Integrated Device Technology, Inc.
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Revision B, February 25, 2016
810N322I-02 Datasheet
For applications in which there is substantial low frequency jitter in
the input reference and the phase detector frequency of 8kHz or
10kHz lies in or near a jitter mask, a three pole filter is recommended.
Suggested part values are in the table below. Note that the option of
a three pole filter can be left open by laying out the three pole filter
but setting R3 to 0 ohms and not populating C3. Refer to the
application schematic for a specific example.
Jitter Attenuator Loop Bandwidth Selection Table (3RD Order Loop Filter)
Bandwidth
Crystal Frequency
RS (k)
CS (µF)
CP (µF)
R3 (k)
C3 (k)
RSET (k)
15Hz (Low)
27MHz
196
10
0.022
82.5
0.010
2.74
30Hz (Mid)
27MHz
392
2.2
0.0047
165
0.0022
2.74
60Hz (High)
27MHz
432
1
0.0022
182
0.001
1.5
NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from each other. Other signal traces
©2016 Integrated Device Technology, Inc.
should be kept separate and not run underneath the device, loop filter
or crystal components.
14
Revision B, February 25, 2016
810N322I-02 Datasheet
Schematic Layout
Figure 4 (next page) shows an example of 810N322I-02 application
schematic. In this example, the device is operated at VDD = VDDA =
VDDX = VDDO = 3.3V. The inputs are driven by a 3.3V LVPECL driver
and an LVDS driver.
that the 0.1uF capacitors on the device side of the ferrite beads be
placed on the device side of the PCB as close to the power pins as
possible. This is represented by the placement of these capacitors in
the schematic. If space is limited, the ferrite beads, 10uf and 0.1uF
capacitor connected to 3.3V can be placed on the opposite side of
the PCB. If space permits, place all filter components on the device
side of the board.
A three pole loop filter is used for the greater reduction of 10 kHz
phase detector spurs relative to that afforded by a two pole loop filter.
It is recommended that the loop filter components be laid out for the
3-pole option, which will also allow a 2-pole filter to be used. The loop
filter components are to be laid out on the 810N322I-02 side of the
PCB directly adjacent to the LF0 and LF1 pins.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10 kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 810N322I-02 provides
separate VDD, VDDA, VDDX and VDDO power supplies for each jitter
attenuator to isolate any high switching noise from coupling into In
order to achieve the best possible filtering, it is highly recommended
©2016 Integrated Device Technology, Inc.
15
Revision B, February 25, 2016
810N322I-02 Datasheet
Logic Control Input Examples
Set Logic
Input to '1'
VDD
VDD
Set Logic
Input to '0'
VDD
3.3V
R25 10
RU1
1K
RU2
Not Ins tall
FB1
2
VDDA
C45
10uF
C8
1
BLM18BB221SN1
C7
0.1uF
10uF
To Logic
Input
pins
R26 10
To Logic
Input
pins
RD1
Not Ins tall
VDDX
C47
10uF
RD2
1K
3.3V
FB2
2
VDDO
C10
1
BLM18BB221SN1
C9
0.1uF
10uF
U1
C1 and C2 Values set by c enter
frequency tune procedure
PDSEL_2
PDSEL_1
PDSEL_0
9
10
11
X1
C1
TUNE
27MHz (10pf )
C2
TUNE
ODASEL_1
ODASEL_0
16
17
ODBSEL_1
ODBSEL_0
14
15
CLK_SEL
PDSEL_2
PDSEL_1
PDSEL_0
ODASEL_1
ODASEL_0
ODBSEL_1
ODBSEL_0
VDD
VDD
VDD
VDDA
VDDX
21
VDDO
XTAL_IN
XTAL_OUT
29
28
100
VDDX
VDDO
C12
0. 1uF
R1
QA
R33
VDDA
C17
0.1uF
CLK_SEL
Zo = 50 Ohm
VDD
VDD
VDD
13
32
5
31
30
Zo = 50 Ohm
6
12
27
19
C15
0. 1uF
C46
0.1uF
C30
0.1uF
C14
0.1uF
Place each 0.1uF bypass
cap directly adjacent
to its corresponding
VDD, VDDA, VDDX or VDDO
pin.
36
CLK0
nCLK0
22
LVDS Driver
R2
Z o = 50
QB
Zo = 50 Ohm
36
R8 50
26
25
Zo = 50 Ohm
CLK1
nCLK1
LVCMOS Receiv er
nc
nc
nc
R4 50
1
LF1
R5
50
Z o = 50
2
4
8
18
24
LF1
ISET
LVCMOS Receiv er
33
3
ePAD
LF0
GND
GND
GND
GND
PECL Driv er
7
23
20
LF0
R3 165k
C3
2.2nF
Cp
4.7nF
Rs
392k
Rs et
2.74K
Cs
2.2uF
Loop fil ter and Rset - Mid LBW S etti ng
Figure 4. 810N322I-02 Application Schematic
©2016 Integrated Device Technology, Inc.
16
Revision B, February 25, 2016
810N322I-02 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 810N322I-02.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 810N322I-02 is the sum of the core power plus the analog power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core Output Power Dissipation
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(220mA + 30mA) = 866.25mW
•
Power (output)MAX = VDDO_MAX * IDDO = 3.465V *12mA = 41.58mW
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 8)] = 29.871mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 8 * (29.871mA)2 = 7.138mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 7.138mW * 2 = 14.276mW
•
Dynamic Power Dissipation at 622.08MHz
Power (25MHz) = CPD * Frequency * (VDDO)2 = 8pF * 622.08MHz * (3.465V)2 = 59.75mW per output
Total Power (622.08MHz) = 59.75mW * 2 = 119.5mW
Total Power Dissipation
•
Total Power
= Power (core) + Power (output) + Total Power (622.08MH)
= 866.25mW + 41.58mW + 14.276mW + 119.5mW
= 1041.61mW
©2016 Integrated Device Technology, Inc.
17
Revision B, February 25, 2016
810N322I-02 Datasheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.042W * 33.1°C/W = 119.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
18
Revision B, February 25, 2016
810N322I-02 Datasheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
33.1°C/W
28.1°C/W
25.4°C/W
Transistor Count
The transistor count for 810N322I-02 is: 51,877
©2016 Integrated Device Technology, Inc.
19
Revision B, February 25, 2016
810N322I-02 Datasheet
32 Lead VFQFN Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
L
A3
N
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
Bottom View w/Type A ID
4
Th er mal
Ba se
D2
C
Bottom View w/Type C ID
2
1
2
1
CHAMFER
D2
2
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 8. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin out are shown on the front page. The
package dimensions are in Table 8.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
©2016 Integrated Device Technology, Inc.
20
Revision B, February 25, 2016
810N322I-02 Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
810N322BKI-02LF
ICS322BI02L
“Lead-Free” 32 Lead VFQFN
Tray
-40°C to 85°C
810N322BKI-02LFT
ICS322BI02L
“Lead-Free” 32 Lead VFQFN
Tape & Reel
-40°C to 85°C
©2016 Integrated Device Technology, Inc.
21
Revision B, February 25, 2016
810N322I-02 Datasheet
Revision History Sheet
Rev
B
Table
Page
Description of Change
Date
Deleted “ICS” prefix from part number.
Updated datasheet header/footer.
©2016 Integrated Device Technology, Inc.
22
2/25/16
Revision B, February 25, 2016
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