Frequency Generator/Jitter Attenuation Device
813076
OBSOLETE
For Wireless Infrastructure Applications
DATASHEET
GENERAL DESCRIPTION
FEATURES
The ICS813076I is a member of the HiperClocks family of high
performance clock solutions from IDT. The ICS813076I a PLL
based synchronous clock solution that is optimized for wireless
infrastructure equipment where frequency translation and jitter
attenuation is needed.
• Two operation modes: input frequency multiplier and VCXO
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage attenuates the reference clock
jitter by using an internal or external VCXO circuit. The internal
VCXO requires the connection of an external inexpensive pullable
crystal (XTAL) to the ICS813076I. This first PLL stage (VCXO
PLL) uses external passive loop filter components which are used
to optimize the PLL loop bandwidth and damping characteristics
for the given application. The output of the first stage VCXO
PLL is a stable and jitter-tolerant reference input for the second
PLL stage of 30.72MHz. The second PLL stage provides
frequency translation by multiplying the output of the first stage
up to 614.4MHz. The low phase noise characteristics of the clock
signal is maintained by the internal FemtoClock™ PLL, which
requires no external components or configuration. Two independently
configurable frequency dividers translate the 491.52MHz or
614.4MHz internal VCO signal to the desired output frequencies.
All frequency translation ratios are set by device configuration pins.
Alternative to the clock frequency multiplication functionality, the
ICS813076I can work as a VCXO. Enabling the VCXO mode allows
the output frequency of 614.4MHz/N or 491.52MHz/N to be pulled
by the input voltage of the VC pin.
• Maximum output frequency: 614.4MHz
• Two selectable differential input clocks can accept the following
differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• FemtoClock VCO frequency: 491.52MHz or 614.4MHz (typical)
• Frequency generation optimized for wireless infrastructure equipment
• Attenuates the phase jitter of the input clock signal by using a
low-cost pullable fundamental mode crystal (XTAL)
• Multiplies the input clock frequency by 1, 4, 5, 16 or 20
• LVCMOS/LVTTL levels for all input/output controls
• PLL fast-lock control
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference frequency tracking using external loop filter
components
• Absolute pull range: ±50ppm
• RMS phase jitter (12kHz – 20MHz): 0.97ps (typical)
• Full 3.3V supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement device use 8T49N286-dddNLGI
PIN ASSIGNMENT
• Supported output clock frequencies:
30.72MHz
122.88MHz
153.6MHz
491.52MHz
614.4MHz
LF1
LF0
ISET
VC
FLM
VCC
VCC
CLK1
nCLK1
nMR
CLK0
nCLK0
VEE
LOCK
VCCO
NA_SEL1
nQA0
QA0
VCCO
nQC
QC
VCCO
VEE
nc
nc
MF_SEL
MV_SEL
VC_SEL
VCC
XTAL_OUT
XTAL_IN
VEE
• Supported input reference clock frequencies:
15.36MHz,
30.72MHz
61.44MHz
• Nine differential LVPECL outputs, organized in three independent output banks
64 63 62 6160 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
64-Lead TQFP, E-Pad
8
10mm x 10mm x 1.0mm
9
package body
10
Y package
11
Top View
12
13
14
15
16
813076I
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nQA1
QA1
VCCO
nQA2
QA2
VEE
nQA3
QA3
VCCO
nQA4
QA4
VCC
VEE
nQB0
QB0
VCCO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nQB1
QB1
VCCO
nQB2
QB2
VCCA
nc
REF_SEL
nSTOP
nBYPASS
P
NC_SEL0
NC_SEL1
NB_SEL0
NB_SEL1
NA_SEL0
813076 REVISION B 7/29/16
1
©2016 Integrated Device Technology, Inc.
813076 DATA SHEET
BLOCK DIAGRAM
30.72MHz
LOCK
XTAL_IN
XTAL_OUT
QA0
ISET
÷NA
LF1
nQA0
LF0
QA4
nQA4
0
CLK0
nCLK0
CLK1
nCLK1
P_SEL
Pulldown
Pullup/Pulldown
0
÷P
fPD PD
0
CP
1
QB0
÷NB
VCXO
fVCXO Femto fVCO
PLL
1
QB1
Pulldown
Pullup/Pulldown
nQB0
nQB1
1
QB2
÷MF
Pulldown
nQB2
VC
VC_SEL
QC
Multiplier / Divider
Pulldown
÷NC
÷MV
nQC
Internal VCXO
MV_SEL
Pulldown
MF_SEL
Pulldown
REF_SEL
Pulldown
nBYPASS
Pullup
NA_SEL[1:0]
Pulldown
NB_SEL[1:0]
Pulldown
NC_SEL[1:0]
Pulldown
FLM
Pulldown
nMR
Pullup
nSTOP
Pullup
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
2
REVISION B 7/29/16
813076 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input
Analog
Output
Description
1
LF1
Input from external loop filter. VCXO control voltage input.
2
LF0
3
ISET
Analog
Charge pump current setting pin.
4
VC
Analog
Control voltage to the VCXO.
Output to external loop filter. Charge pump output.
5
FLM
Input
6, 7, 37, 61
VCC
Power
Pulldown
VCXO-PLL fast lock mode. LVCMOS/LVTTL interface levels. See Table 3H.
8
CLK1
Input
Pulldown
Non-inverting differential reference clock input.
Inverting differential clock input. VCC/2 bias voltage when left floating.
Core power supply pins.
9
nCLK1
Input
Pullup/
Pulldown
10
nMR
Input
Pullup
11
CLK0
Input
Pulldown
Non-inverting differential reference clock input.
Pullup/
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
Master reset pin. LVCMOS/LVTTL interface levels. See Table 3I.
12
nCLK0
Input
13, 36, 43, 55,
64
VEE
Power
Negative supply pins.
14
LOCK
Output
VCXO-PLL lock state. In VCXO-PLL mode (VC_SEL = 0), logic HIGH at the
LOCK output indicates frequency lock of the VCXO-PLL. In VCXO-PLL mode
(VC_SEL = 1), the state of LOCK is always 0. LVCMOS/LVTTL interface levels.
VCCO
Power
Output supply pins.
15, 30, 33, 40,
46, 51, 54
16,
17
18,
19
20,
21
NA_SEL1,
NA_SEL0
NB_SEL1,
NB_SEL0
NC_SEL1,
NC_SEL0
22
Input
Pulldown
Input
Pulldown
Input
Pulldown
P_SEL
Input
Pulldown
23
nBYPASS
Input
Pullup
24
nSTOP
Input
Pullup
Pulldown
FemtoPLL output-divider for QA outputs. LVCMOS/LVTTL interface levels.
See Table 3F.
FemtoPLL output-divider for QB outputs. LVCMOS/LVTTL interface levels.
See Table 3F.
FemtoPLL output-divider for QC outputs. LVCMOS/LVTTL interface levels.
See Table 3F.
VCXO pre-divider selection. LVCMOS/LVTTL interface levels. See Table 3B.
PLL mode selection. LVCMOS/LVTTL interface levels. See Table 3G.
Ouput clock stop pin. LVCMOS/LVTTL interface levels. See Table 3J.
Selects the input reference clock. LVCMOS/LVTTL interface levels.
See Table 3E.
25
REF_SEL
Input
26, 56, 57
nc
Unused
Power
Analog supply pin.
Output
Differential Bank B clock outputs. LVPECL interface levels.
Output
Differential Bank A clock outputs. LVPECL interface levels.
Differential Bank C clock outputs. LVPECL interface levels.
No connect.
27
VCCA
28, 29
31, 32
34, 35
38, 39
41, 42
44, 45
47, 48
49, 50
QB2, nQB2
QB1, nQB1
QB0, nQB0
QA4, nQA4
QA3, nQA3
QA2, nQA2
QA1, nQA1
nQA0, QA0
52, 53
nQC, QC
Output
58
MF_SEL
Input
Pulldown
Femto-PLL feedback divider selection. LVCMOS/LVTTL interface levels.
See Table 3D.
59
MV_SEL
Input
Pulldown
VCXO M-divider selection. LVCMOS/LVTTL interface levels. See Table 3C.
60
VC_SEL
Input
Pulldown
62,
63
XTAL_OUT,
XTAL_IN
Input
Controls the mode of operation. LVCMOS/LVTTL interface levels.
See Table 3K.
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 7/29/16
3
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
DEVICE CONFIGURATION
The ICS813076I is a two stage device, a VCXO PLL stage followed
by a low phase noise FemtoClock PLL multiplier stage. The VCXO
PLL stage uses a pullable crystal to lock to the reference clock. The
low phase noise FemtoClock multiplies the VCXO PLL output clock
up to 614.4MHz and three independent output dividers scale the
frequency down to the desired output frequencies. With a given input
and VCXO frequency, the output frequency is a function of the P, MV,
MF and NA, NB, NC dividers, and can be set by pulling configuration
pins high or low. See “ICS813076I Examples Frequency Configuration (fVCXO= 30.72MHz)” for typical device configurations. Note
that for correct operation, the input frequency times the MV-divider
must be 30.72MHz ± 50ppm. The ICS813076I supports up to three
output frequencies fOUT independently.
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES TABLE (fVCXO = 30.72MHZ)
fIN (MHz)
fOUT (MHz)
Ratio
30.72
30.72
30.72
122.8
30.72
30.72
Configuration
P
MV
MF
NA, NB, NC
1
1
1
20
20
4
1
1
20
5
153.6
5
1
1
20
4
614.4
20
1
1
20
1
30.72
24.576
4/5
1
1
16
20
30.72
98.304
16/5
1
1
16
5
30.72
122.8
4
1
1
16
4
30.72
491.52
16
1
1
16
1
NOTE: The example frequency configuration table is intended to show the most common frequency translations. The following example will illustrate the configuration process.
30.72MHz
XTALIN
CLK
P=1
30.72MHz
VCXO
MV = 1
XTALOUT
FemtoClock PLL
VCO = 614.4MHz
MF = 20
Qn
N=4
153.6MHz
ICS813076I
FIGURE 1. APPLICATION EXAMPLE (153.6MHZ CLOCK GENERATION AND JITTER ATTENUATION)
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
4
REVISION B 7/29/16
813076 DATA SHEET
The VCXO pre-divider (P) down-scales the input reference
frequency fREF and enables the use of the ICS813076I at a variety
of input frequencies. P_SEL and MV_SEL must be set to match the
VCXO frequency: fREF ÷ P = fVCXO ÷ MV. For instance, at the nominal
VCXO frequency of 30.72MHz and if MV equals two, the input
frequency must be an integer multiple of 15.36MHz.
TABLE 3B. VCXO PRE-DIVIDER (P) CONFIGURATION TABLE
TABLE 3C. VCXO MULTIPLIER (MV-DIVIDER) CONFIGURATION TABLE
Input
Input
P_SEL
Pre-Divider Function
Operation
MV_SEL
0
÷1
fPD = fREF ÷ 1
0
1
fVCXO = fPD
1
÷2
fPD = fREF ÷ 2
1
2
fVCXO = fPD * 2
TABLE 3D. FEMTOCLOCK FEEDBACK DIVIDER (MF)
CONFIGURATION TABLE
TABLE 3E. INPUT REFERENCE CLOCK MULTIPLEXER
CONFIGURATION TABLE
Input
MF_SEL
Multiplier MV Function Operation
Input
Multiplier MF Function Operation
REF_SEL
Operation
0
20
fVCO = fVCXO * 20
0 (default)
Selects CLK0, nCLK0 as PLL reference signal
1
16
fVCO = fVCXO * 16
1
Selects CLK1, nCLK1 as PLL reference signal
TABLE 3F. PLL OUTPUT-DIVIDER (NA, NB, NC) CONFIGURATION TABLE
Inputs
Nx_SEL1
Nx_SEL0
Output Dividers
NA, NB, NC
0
0
÷1
fOUT = fVCO
0
1
÷4
fOUT = fVCO ÷ 4
1
0
÷5
fOUT = fVCO ÷ 5
1
1
÷20
fOUT = fVCO ÷ 20
Operation
The FemtoClock PLL stage multiplies the VCXO frequency (30.72MHz) to
491.52MHz or 614.4MHz. The output frequency equals:
[(fREF ÷ P) * MV * MF] ÷ N. The NA, NB and NC dividers operate independently.
TABLE 3G. PLL BYPASS CONFIGURATION TABLE
Input
nBYPASS
0
1 (default)
Operation
fOUT = fREF ÷ N
VCXO and PLL bypassed, no jitter attenuation and frequency multiplication. AC specifications do not apply.
((fREF ÷ P) * MV * MF) ÷ N
VCXO and PLL operation, jitter attenuation and frequency multiplication enabled.
The nBYPASS control should be set to logic HIGH for normal operation. nBYPASS = 0 enables the PLL bypass mode for factory test.
REVISION B 7/29/16
5
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
TABLE 3I. RESET AND OUTPUT CONFIGURATION TABLE
TABLE 3H. FAST LOCK MODE CONFIGURATION TABLE
Input
Input
FLM
nMR
Operation
0 (default)
0
Normal operation.
Fast PLL lock operation. Use this mode only
during start-up to decrease PLL lock time.
1
Operation
The Femto-PLL is reset.
1 (default)
Normal operation and outputs are enabled.
VCC = 3.3V
0V
tLOCK
VCXO-PLL Acquires Lock
VCXO-PLL Locked
LOCK
Fast Lock Mode
(High VCXO-PLL Bandwidth)
FLM
Nominal VCXO-PLL Bandwidth
FIGURE 2. RECOMMENDED START-UP TIMING DIAGRAM
TABLE 3J. RESET AND OUTPUT CONFIGURATION TABLE
Input
nSTOP
0
1 (default)
Operation
QA[4:0], QB[2:0] and QC outputs are stopped in logic LOW state. nQA[4:0], nQB[2:0] and nQC outputs are stopped
in logic HIGH state (QX = LOW, nQX = HIGH). The assertion of nSTOP is asynchronous to the internal clock signal
and may cause an output runt pulse.
Normal operation and outputs enabled.
TABLE 3K. VC_SEL CONFIGURATION TABLE
Input
Mode of
VC_SEL Operation
VC Function
Frequency multi- VC input has no function
plier: the reference clock signal
0
is jitter attenuated
(default)
and frequencymultiplied
1
VCXO: the output VC controls the VCXO
frequency directly
frequency is a
fVCXO = 30.72MHz±50ppm
function of an
input voltage. The
device can be
used as a integrated oscillator
in an external
PLL
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
CLKx Input Function
Enabled, the device
locks to CLK0 or
CLK1
Disabled
6
LF0, LF1, ISET
Function
Output Frequency
Enabled
fOUT = ((fREF / P)*MV*MF)/N
fXTAL = 30.72MHz
The PLL locks to the selected
CLKx input
Disabled
fOUT = (30.72MHz ± 50ppm)*MF/N
fOUT is pulled by the control voltage
on the VC pin
REVISION B 7/29/16
813076 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
31.8°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
VCO
Output Supply Voltage
3.135
IEE
Power Supply Current
ICCA
Analog Supply Current
Units
3.135
3.3
3.465
V
VCC – 0.09
3.3
VCC
V
3.3
3.465
V
250
mA
17
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
IIH
IIL
Input
High Current
Input
Low Current
REVISION B 7/29/16
NA_SEL[0:1],
NB_SEL[0:1], NC_
SEL[0:1],
MF_SEL, FLM,
P_SEL, MV_SEL,
REF_SEL, VC_SEL
nMR, nSTOP,
nBYPASS
NA_SEL[0:1],
NB_SEL[0:1], NC_
SEL[0:1],
MF_SEL, FLM,
P_SEL, MV_SEL,
REF_SEL, VC_SEL
nMR, nSTOP,
nBYPASS
VCC = 3.465V, VIN = 0V
-5
µA
VCC = 3.465V, VIN = 0V
-150
µA
7
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VC
VCXO Control Voltage
VPP
Peak-to-Peak Input Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
CLK0, CLK1
nCLK0, nCLK1
Minimum
Typical
VIN = VCC = 3.465V
Maximum
Units
150
µA
CLK0, CLK1
VIN = 0V, VCC = 3.465V
-5
µA
nCLK0, nCLK1
VIN = 0V, VCC = 3.465V
-150
µA
0
VCC
V
0.15
1.3
V
VEE + 0.5
VEE - 0.85
V
Maximum
Units
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
8
REVISION B 7/29/16
813076 DATA SHEET
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C (VC = 0, FREQUENCY MULTIPLIER)
Symbol
Parameter
fREF
Input Frequency;
NOTE 1
fosc
XTAL Frequency
fOUT
tjit(Ø)
Φn
Output Frequency;
NOTE 2
CLK0/nCLK0 or
CLK1/nCLK1
Minimum
nBYPASS = 1
15.36MHz - 50ppm
61.44MHz + 50ppm
MHz
153.6
MHz
122.88
MHz
30.72
MHz
491.52
MHz
122.88
MHz
98.304
MHz
24.576
MHz
0.97
ps
10Hz offset
-59.4
dBc/Hz
100Hz offset
-60.4
dBc/Hz
QAx, QBx, QC
1kHz offset
XTAL = 30.72MHz
10kHz offset
100kHz offset
tsk(o)
Output Skew; NOTE 3 fQA = fQB = fQC
tR / tF
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
Units
614.4
nBYPASS = 1,
MF = 20, N = 1
nBYPASS = 1,
MF = 20, N = 4
nBYPASS = 1,
MF = 20, N = 5
nBYPASS = 1,
MF = 20, N = 20
nBYPASS = 1,
MF = 16, N = 1
nBYPASS = 1,
MF = 16, N = 4
nBYPASS = 1,
MF = 16, N = 5
nBYPASS = 1,
MF = 16, N = 20
fOUT = 61.44MHz,
XTAL = 30.72MHz
Does not include
harmonic spurs
sub harmonics
tLOCK
Maximum
MHz
spurious
odc
Typical
30.72
RMS Phase Jitter;
Integration Range: 12kHz - 20MHz
Single-Side Band
Phase Noise at
fOUT = 614MHz
Test Conditions
-79.4
dBc/Hz
-106.7
dBc/Hz
-112.9
dBc/Hz
-42
dB
-19
dB
240
ps
20% to 80%
160
700
ps
N≠1
45
55
%
N=1
40
60
%
FLM = 1
360
600
ms
FLM = 0
2.5
5.0
s
NOTE 1: fREF depends on P and M. In all applications, fREF = (30.72MHz ÷ MV * P) ± 50ppm.
NOTE 2: fOUT = ((fREF ÷ P) * MV * MF) ÷ N.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
REVISION B 7/29/16
9
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
TABLE 5B. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C (VC = 1, VCXO MODE)
Symbol
Parameter
fosc
XTAL Frequency
fOUT
Output Frequency;
NOTE 1
Test Conditions
QAx, QBx, QC
Minimum
Absolute Pull Range
BW
Modulation Bandwidth of VCXO
LVC
Tuning Linearity
tjit(Ø)
RMS Phase Jitter;
Integration Range: 12kHz - 20MHz
Fn
Single-Side Band
Phase Noise at
fOUT = 122.88MHz
Units
MHz
nBYPASS = 1, MF = 20, N = 1
614.4
MHz
nBYPASS = 1, MF = 20, N = 4
153.6
MHz
nBYPASS = 1, MF = 20, N = 5
122.88
MHz
nBYPASS = 1, MF = 20, N = 20
30.72
MHz
nBYPASS = 1, MF = 16, N = 1
491.52
MHz
nBYPASS = 1, MF = 16, N = 4
122.88
MHz
nBYPASS = 1, MF = 16, N = 5
98.304
MHz
24.576
-50
MHz
50
ppm
200
kHz
VC = 0.6V to 1.4V
±6.5
%
fOUT = 122.88MHz,
XTAL = 30.72MHz
0.88
ps/rms
10Hz offset
-41.18
dBc/Hz
100Hz offset
-72.82
dBc/Hz
1kHz offset
-104.19
dBc/Hz
10kHz offset
-126.63
dBc/Hz
100kHz offset
-128.57
dBc/Hz
spurious
XTAL = 30.72MHz
Does not include harmonic spurs
sub harmonics
tsk(o)
Output Skew;
NOTE 2
tR / tF
Output Rise/Fall Time
odc
Maximum
30.72
nBYPASS = 1, MF = 16, N = 20
APR
Typical
fQA = fQB = fQC
Output Duty Cycle
-51
dB
-11
dB
240
ps
20% to 80%
160
700
ps
N≠1
45
55
%
N=1
40
60
%
NOTE 1: fOUT = ((30.72MHz) * MF) ÷ N ± 50ppm.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
10
REVISION B 7/29/16
813076 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
2V
2V
VCC,
VCCO
SCOPE
Qx
VCCA
LVPECL
nQx
VEE
-1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Sub-harmonic
Spectral Power
Spurious
nQAx,
nQBx, nQC
QAx,
QBx, QC
-3 fOUT
-2 fOUT
fOUT
2 fOUT
3 fOUT
Frequency
OUTPUT RISE/FALL TIME
REVISION B 7/29/16
SPURIOUS/SUB-HARMONICS
11
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813076I
provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and
V CCO should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 3 illustrates this for a generic VCC pin
and also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10 μF
FIGURE 3. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 4. SINGLE-ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
12
REVISION B 7/29/16
813076 DATA SHEET
DIFFERENTIAL CLOCK INPUT INTERFACE
Please consult with the vendor of the driver component to confirm
the driver termination requirements. For example in Figure 5A, the
input termination applies for IDT HiPerClockS open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 5A to 5F show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples only.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
R2
84
FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
FIGURE 5E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 5F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
REVISION B 7/29/16
Receiv er
Zo = 50 Ohm
13
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK INPUTS
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 6A
and 6B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
FIGURE 6B. LVPECL OUTPUT TERMINATION
FIGURE 6A. LVPECL OUTPUT TERMINATION
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
14
REVISION B 7/29/16
813076 DATA SHEET
EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on
the package, as shown in Figure 7. The solderable area on the PCB,
as defined by the solder mask, should be at least the same size/
shape as the exposed pad/slug area on the package to maximize
the thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
specific and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern.
It is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern
must be connected to ground through these vias. The vias act as
“heat pipes”. The number of vias (i.e. “heat pipes”) are application
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
FIGURE 7. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
REVISION B 7/29/16
15
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
SCHEMATIC LAYOUT
Figure 8 shows an example of the ICS813076I application schematic.
In this example, the device is operated at VCC = VCCO = 3.3V. The
decoupling capacitors should be located as close as possible to
the power pin. The input is driven by a 3.3V LVPECL driver. An
optional 3-pole filter can also be used for additional spur reduction.
It is recommended that the loop filter components be laid out for
the 3-pole option. This will also allow the 2-pole filter to be used.
3.3V
R1
133
X1
30.72MHz, CL=10pF
R2
133
Zo = 50 Ohm
QA0
C21
SPARE
TL1
+
Zo = 50 Ohm
nQA0
820k
VCC
Cp
0.01uF
VEE
XTAL_IN
XTAL_OUT
VCC
VC_SEL
MV
MF
nc
nc
VEE
VCCO
QC0
nQC0
VCCO
QA0
nQA0
2-pole loop filter with Mid LBW Setting
LF1
LF1
LF0
R19
TBDk
Cp
0.01uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ISET
VC
FLM
Rs
0.64k
VCC
nMR
R11
125
R13
125
LOCK
NA1
LF1
LF0
ISET
VC
FLM
VCC
VCC
CLK1
nCLK1
nMR
CLK0
nCLK0
VEE
LOCK
VCCO
NA1
LVPECL Termination
VCC=3.3V
nQA1
QA1
VCCO
nQA2
QA2
VEE
nQA3
QA3
VCCO
nQA4
QA4
VCC
VEE
nQB0
QB0
VCCO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCCO=3.3V
3.3V
R1
133
VCC
TL1
+
nQB0
QB0
Zo = 50 Ohm
nQB0
nCLK1
R14
84
R4
82.5
ICS813076I
NA0
NB1
NB0
NC1
NC0
P
nBYPASS
nSTOP
REF_SEL
4.75K
J30
VCC
R11
125
R3
82.5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
R39
R12
84
-
TL2
NA0
NB1
NB0
NC1
NC0
P
nBYPASS
nSTOP
REF_SEL
nc
VCCA
QB2
nQB2
VCCO
QB1
nQB1
Zo = 50
R2
133
Zo = 50 Ohm
QB0
CLK1
Zo = 50
LVPECL Driv er
R4
82.5
C3
220pF
U1
Cs
10uF
R3
82.5
R13
125
QB2
nQB2
Cs
10uF
-
TL2
VCCO
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Rs
0.64k
VC_SEL
MV
MF
C22
SPARE
LF1
XTAL_IN
XTAL_OUT
R3
LF0
QA0
nQA0
3-pole loop filter example - (optional)
LVPECL Termination
LD1
VCC
R37
10
VCCA
CLK0
Zo = 50
C23
0.01u
C24
Zo = 50 Ohm
QB2
+
10u
Zo = 50
nCLK0
Zo = 50 Ohm
nQB2
-
nSTOP
R12
84
LVPECL Driv er
R14
84
R6
50
Logic Control Input Examples
Set Logic
Input to
'1'
VCC
RU1
1K
Set Logic
Input to
'0'
VCC
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
VCCO
(U1, 15) VCCO
C35
0.1u
Optional
LVPECL
Y-Termination
VCC
(U1, 30)
C36
0.1u
(U1, 33)
(U1, 40)
C37
0.1u
(U1, 46)
C38
0.1u
(U1, 51)
C39
0.1u
(U1, 54)
C40
0.1u
(U1, 6)
C40
0.1u
VCC
C30
0.1u
(U1, 7)
(U1, 37)
C31
0.1u
R7
50
R8
50
(U1, 61)
C32
0.1u
C33
0.1u
To Logic
Input
pins
RD2
1K
FIGURE 8. ICS813076I APPLICATION SCHEMATIC
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
16
REVISION B 7/29/16
813076 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813076I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813076I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE = 3.465V * 250mA = 866.25mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30mW = 270mW
Total Power_MAX (3.465V, with all outputs switching) = 866.25mW + 270mW = 1136.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 31.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.136W * 31.8°C/W = 121.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 64 LEAD TQFP, E-PAD FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
REVISION B 7/29/16
31.8°C/W
17
1
2.5
25.8°C/W
24.2°C/W
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCCO– 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V - (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
REVISION B 7/29/16
18
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load capacitance
(CL). In addition, frequency, accuracy and temperature range
must also be considered. Since the pulling range of a crystal also
varies with the package, it is recommended that a metal-canned
package like HC49 be used. Generally, a metal-canned package
has a larger pulling range than a surface mounted device (SMD).
For crystal selection information, refer to the VCXO Crystal
Selection Application Note.
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of CL is dependant on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows RS,
CS and CP values for recommended high, mid and low loop
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to
the Loop Filter Component Selection for VCXO Based PLLs
Application Note.
The crystal’s load capacitance CL characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short
and separated from each other.
Other signal traces should
be kept separate and not run
underneath the device, loop
filter or crystal components.
If the crystal CL is greater than the total external capacitance,
the VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal CL is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than
VCXO CHARACTERISTICS TABLE
Symbol
Parameter
Typical
Unit
kVCXO
VCXO Gain
11
kHz/V
CV_LOW
Low Varactor Capacitance
10
pF
CV_HIGH
High Varactor Capacitance
25
pF
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
RS (kΩ)
CS (µF)
2
1.5
10
0.1
20
1
0.64
10
0.01
4.75
1
1
4.7
0.001
2.21
Bandwidth
Crystal Frequency (MHz)
MV
72Hz (Low)
30.72MHz
259Hz (Mid)
30.72MHz
871Hz (High)
30.72MHz
CP (µF)
RSET (kΩ)
CRYSTAL CHARACTERISTICS
Symbol
Parameter
Minimum
Mode of Operation
Fundamental
Typical
Maximum
fN
Frequency
fT
Frequency Tolerance
±20
ppm
fS
Frequency Stability
±20
ppm
85
°C
Operating Temperature Range
30.72
Units
-40
MHz
CL
Load Capacitance
10
pF
CO
Shunt Capacitance
4
pF
CO/C1
Pullability Ratio
220
ESR
Equivalent Series Resistance
20
Drive Level
1
mW
Aging @ 25°C
±3 per year
ppm
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
240
19
REVISION B 7/29/16
813076 DATA SHEET
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD
θJA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
31.8°C/W
1
2.5
25.8°C/W
24.2°C/W
TRANSISTOR COUNT
The transistor count for ICS813076I is: 4709
REVISION B 7/29/16
20
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, E-PAD
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
ACD-HD
MINIMUM
NOMINAL
N
MAXIMUM
64
A
--
--
1.20
A1
0.05
0.10
0.15
A2
0.95
1.0
1.05
b
0.17
0.22
0.27
c
0.09
--
0.20
D
12.00 BASIC
D1
10.00 BASIC
D2
7.50 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.50 Ref.
e
0.50 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.08
D3 & E3
4.5
5.0
5.5
Reference Document: JEDEC Publication 95, MS-026
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
21
REVISION B 7/29/16
813076 DATA SHEET
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
813076CYILF
ICS813076CYILF
813076CYILFT
ICS813076CYILF
64 Lead “Lead-Free” TQFP, E-Pad
Tray
-40°C to 85°C
64 Lead “Lead-Free” TQFP, E-Pad
500 Tape & Reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History
7/29/16
REVISION B 7/29/16
Added OBSOLETE to the front page.
22
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
their respective third party owners.
Copyright 2016. All rights reserved.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
工商网监
湘ICP备2023018690号
