813078I
Femtoclocks™ VCXO-PLL Frequency Generator
for Wireless Infrastructure Equipment
Data Sheet
OBSOLETE
General Description
Features
The ICS813078I is a member of the HiperClocks family of high
performance clock solutions from IDT. The ICS813078I a PLL
based synchronous clock solution that is optimized for wireless
infrastructure equipment where frequency translation and jitter
attenuation is needed.
•
Nine outputs, organized in three independent output banks with
differential LVPECL and single-ended outputs
•
One differential input clock can accept the following differential
input levels: LVDS, LVPECL, LVHSTL
•
•
•
One single-ended clock input
•
Internal Femtoclock frequency multiplier stage eliminates the
need for an expensive external high frequency VCXO
•
•
LVCMOS levels for all control I/O
•
RMS phase jitter @ 61.44MHz, using a 30.72MHz crystal
(12kHz to 20MHz): 0.97ps rms (typical)
•
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference frequency tracking using external loop filter
components
•
•
•
•
•
•
•
PLL fast-lock control
The device contains two internal PLL stages that are cascaded in
series. The first PLL stage attenuates the reference clock jitter by
using an internal or external VCXO circuit. The internal VCXO
requires the connection of an external inexpensive pullable crystal
(XTAL) to the ICS813078I. This first PLL stage (VCXO PLL) uses
external passive loop filter components which are used to
optimize the PLL loop bandwidth and damping characteristics for
the given application. The output of the first stage VCXO PLL is a
stable and jitter-tolerant 30.72MHz reference input for the second
PLL stage. The second PLL stage provides frequency translation
by multiplying the output of the first stage up to 491.52MHz or
614.4MHz. The low phase noise characteristics of the VCXO-PLL
clock signal is maintained by the internal FemtoClock™ PLL,
which requires no external components or complex programming.
Two independently configurable frequency dividers translate the
internal VCO signal to the desired output frequencies. All
frequency translation ratios are set by device configuration pins.
Supported input reference clock frequencies:
10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz,
61.44MHz, and 122.88MHz
Frequency generation optimized for wireless infrastructure
Attenuates the phase jitter of the input clock signal by using
low-cost pullable fundamental mode crystal (XTAL)
RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal
(12kHz to 20MHz): 1.1ps rms (typical)
PLL lock detect output
Absolute pull range is +/-50 ppm
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For replacement device use 8T49N285-dddNLGI
CLK1
REF_SEL
nMR
CLK0
nCLK0
VEE
NA1
© 2016 Integrated Device Technology, Inc
1
nc
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NB0
NC1
NC0
R2
R1
R0
BYPASS1
BYPASS0
nc
nc
NA0
NB1
nc
nc
VCCO
nQA0
QA0
VEE
nQA1
QA1
VCCO
nQA2
QA2
VCC
VEE
nQB0
QB0
VCCO
nQB1
FLM
VCC
VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
5
44
6
43
64-Lead TQFP, E-Pad
7
42
10mm x 10mm x 1mm
8
41
package body
9
40
Y Package
10
39
11
38
12
37
13
36
14
35
1
2
VCCA
nSTOPA
nSTOPB
nSTOPC
QB1
ISET
nc
QC1
VEE
QC2
VCCO_CMOS
QC3
VEE
VEE
XTAL__IN
XTAL_OUT
LF1
LF0
VCC
MF
LOCK
VEE
QC0
VCCO_CMOS
Pin Assignment
Supported output clock frequencies:
30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz,
153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz
July 29, 2016
813078I Data Sheet
Block Diagram
LF1
ISET
LF0
XTAL_IN
XTAL_OUT
fXTAL = 30.72MHz
LOCK
nSTOPA
fOUT
fREF
CLK0
nCLK0
CLK1
00
P
÷1, ÷2,
÷4, ÷5,
÷125
1
fVCXO
fPD
PD
CP
VCXO
÷16,
÷20
3
LUT
Internal VCXO
QA1
nQA1
QA2
nQA2
fVCO
Femto
PLL
MV
÷1, ÷2, ÷12,
÷192, ÷256, ÷384
REF_SEL
R[2:0]
11
10
NA
÷2, ÷4
÷5, ÷8
QA0
nQA0
0x
NB
÷1, ÷4
÷5, ÷8
QB0
nQB0
QB1
nQB1
Multiplier
FLM
MF
BYPASS[1:0]
2
nSTOPB
QC0
NC
÷4, ÷5,
÷8, ÷16
QC1
QC2
NA[1:0]
NB[1:0]
QC3
NC[1:0]
nMR
nSTOPC
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July 29, 2016
813078I Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1
LF1
Analog
Input
2
LF0
Analog
Output
Output to external loop filter. Charge pump output.
3
ISET
Analog
Charge pump current-settings pin.
4, 25, 26,
47, 48, 49
nc
Unused
No connect.
Pulldown
Input from external loop filter. VCXO control voltage input.
5
FLM
Input
6, 7, 37, 61
VCC
Power
VCXO-PLL fast lock mode. See Table 3H. LVCMOS/LVTTL interface levels.
8
CLK1
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
9
REF_SEL
Input
Pulldown
Selects the input reference clock. See Table 3F.
LVCMOS/LVTTL interface levels.
10
nMR
Input
Pullup
11
CLK0
Input
Pulldown
Non-inverting differential clock input.
Pullup/
Pulldown
Inverting differential clock input.
Power supply pins for LVPECL outputs.
Master reset. See Table 3I. LVCMOS/LVTTL interface levels.
12
nCLK0
Input
13, 36, 43,
50, 54, 58, 64
VEE
Power
14. 15
NA1, NA0
Input
Pulldown
Femto-PLL output-divider for QAn/nQAn outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
16, 17
NB1, NB0
Input
Pulldown
Femto-PLL output-divider for QBn/nQBn outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
18, 19
NC1, NC0
Input
Pulldown
Femto-PLL output-divider for QCn outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
20, 21, 22
R2, R1, R0
Input
Pulldown
VCXO-PLL pre-divider and VCXO multiplier selection. See Table 3A.
LVCMOS/LVTTL interface levels.
23,
24
BYPASS1,
BYPASS0
Input
Pullup
27
VCCA
Power
28
nSTOPA
Input
Pullup
Output clock stop for Bank A. See Table 3J. LVCMOS/LVTTL interface levels.
29
nSTOPB
Input
Pullup
Output clock stop for Bank B. See Table 3K. LVCMOS/LVTTL interface levels.
30
nSTOPC
Input
Pullup
Output clock stop for Bank C. See Table 3L. LVCMOS/LVTTL interface levels.
31, 32
QB1, nQB1
Output
Bank B output pair. LVPECL interface levels.
33, 40, 46
VCCO
Power
Output supply pins for LVPECL outputs.
34, 35
QB0, nQB0
Output
Bank B output pair. LVPECL interface levels.
38, 39
QA2, nQA2
Output
Differential Bank A output pair. LVPECL interface levels.
41, 42
QA1, nQA1
Output
Differential Bank A output pair. LVPECL interface levels.
44, 45
QA0, nQA0
Output
Differential Bank A output pair. LVPECL interface levels.
Negative supply pins.
PLL mode selections. See Table 3G. LVCMOS/LVTTL interface levels.
Analog supply pin.
continued on next page.
51, 53, 55, 57
QC3, QC2,
QC1, QC0
Output
Single-ended Bank C outputs. LVCMOS/LVTTL interface levels.
52, 56
VCCO_CMOS
Power
Output supply pins for LVCMOS outputs.
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813078I Data Sheet
Number
Name
Type
59
LOCK
Output
60
MF
Input
62, 63
XTAL_OUT,
XTAL_IN
Input
Description
VCXO lock state. LVCMOS/LVTTL interface levels. See Table 3M.
Pulldown
FemtoClock-PLL feedback divider selection. See Table 3E.
LVCMOS/LVTTL interface levels.
Internal VCXO crystal oscillator interface.
XTAL_IN is the input. XTAL_OUT is the output.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance (per output)
RPULLUP
Input Pullup Resistor
Minimum
Typical
Maximum
Units
4
pF
10
pF
51
k
RPULLDOWN Input Pulldown Resistor
51
k
ROUT
15
Output Impedance
VCC = VCCO_CMOS = 3.465V
QC[3:0]
DEVICE CONFIGURATION
The ICS813078I is a two stage device, a VCXO-PLL stage
followed by a low phase noise FemtoClock PLL multiplier stage.
The VCXO-PLL stage uses a pullable crystal to lock to the
reference clock. The low phase noise FemtoClock multiplies the
VCXO-PLL output clock up to 491.52MHz or 614.4MHz and three
independent output dividers scale the frequency down to the
desired output frequencies. With a given input and VCXO
frequency, the output frequency is a function of the P, MF, MV and
the NA, NB and NC dividers. The P and MV are controlled by the
R[2:0] control pins through the internal lookup table (LUT).
Table 3A. Input Frequency Configuration Example
Table (fVCXO = 30.72MHz)
The VCXO-PLL pre-divider (P) down-scales the input reference
frequency fREF and enables the use of the ICS813078I at a variety
of input frequencies. P and MV must be set to match the VCXO
frequency: fREF ÷ P = fVCXO ÷ MV. For example, at the nominal
VCXO frequency of 30.72MHz and if MV equals one, the input
frequency must be an integer multiple of 30.72MHz (for MV = 2,
the input frequency must be an integer multiple of 15.36MHz). The
FemtoClock PLL stage multiplies the VCXO frequency
(30.72MHz) to 614.4MHz or 491.52MHz by a multiplier MF of 20
or 16. The output frequency equals [(fREF ÷ P) * MV * MF] ÷ NA,
NB, or NC. The NA, NB and NC dividers operate independently.
© 2016 Integrated Device Technology, Inc
4
Input
Internal Dividers
fref
(MHz)
R[2:0]
P
MV
fXTAL
(MHz)
30.72
000
1
1
30.72
61.44
001
2
1
30.72
122.88
010
4
1
30.72
15.36
011
1
2
30.72
10
100
125
384
30.72
12.8
101
5
12
30.72
15
110
125
256
30.72
20
111
125
192
30.72
July 29, 2016
813078I Data Sheet
Table 3B. PLL Output-Divider (NA) Configuration Table.
Inputs
NA1
NA0
Output-Divider
NA
0 (default)
0 (default)
0
QAn Output
Frequency (MHz)
Operation
MF = 0
MF = 1
2
fQAn = fVCO ÷ 2
245.76
307.2
1
4
fQAn = fVCO ÷ 4
122.88
153.6
1
0
5
fQAn = fVCO ÷ 5
98.304
122.88
1
1
8
fQAn = fVCO ÷ 8
61.44
76.8
Table 3C. PLL Output-Divider (NB) Configuration Table.
Inputs
NB1
NB0
Output-Divider
NB
0 (default)
0 (default)
1
0
1
1
1
QBn Output
Frequency (MHz)
Operation
MF = 0
MF = 1
fQBn = fVCO ÷ 1
491.52
614.4
4
fQBn = fVCO ÷ 4
122.88
153.6
0
5
fQBn = fVCO ÷ 5
98.304
122.88
1
8
fQBn = fVCO ÷ 8
61.44
76.8
Table 3D. PLL Output-Divider (NC) Configuration Table.
Inputs
NC1
NC0
Output-Divider
NC
0 (default)
0 (default)
0
QCn Output
Frequency (MHz)
Operation
MF = 0
MF = 1
4
fQCn = fVCO ÷ 4
122.08
153.6
1
5
fQCn = fVCO ÷ 5
98.304
122.88
1
0
8
fQCn = fVCO ÷ 8
61.44
76.8
1
1
16
fQCn = fVCO ÷ 16
30.72
38.4
Table 3E. Femtoclock PLL Feedback Divider (MF) Configuration Table (fXTAL = 30.72MHz)
Input
MF
Feedback Divider MF
0 (default)
16
fVCO = fVCXO x 16 = 491.52MHz
1
20
fVCO = fVCXO x 20 = 614.4MHz
© 2016 Integrated Device Technology, Inc
Operation
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July 29, 2016
813078I Data Sheet
Table 3F. Input Reference Clock Multiplexer (REF_SEL) Configuration Table
Input
REF_SEL
Operation
0 (default)
Selects CLK0, nCLK0 differential input pair as reference frequency.
1
Selects CLK1 single-ended input as reference frequency.
The input reference selector should be tied to logic 0, selecting the differential clock inputs, for best signal integrity and lowest phase noise
Table 3G. PLL Bypass (BYPASS) Configuration Table
Input
BYPASS1
BYPASS0
Operation
0
X
fOUT = ((fREF ÷ P) * MV * MF) ÷ NA, NB, or NC.
VCXO-PLL operation, jitter attenuation and frequency multiplication enabled.
1
0
fOUT = ((fREF ÷ P) * MV) ÷ NA, NB, or NC.
VCXO-PLL enabled, Femto-PLL bypassed. Jitter attenuation (VCXO-PLL) enabled.
AC specifications do not apply.
1 (default)
1 (default)
fOUT = fREF ÷ NA, NB, or NC.
VCXO-PLL and Femto-PLL bypassed, no jitter attenuation and frequency multiplication.
AC specifications do not apply.
The BYPASS[1:0] controls should be set to logic LOW level for normal operation. BYPASS = 1x enables the PLL bypass mode for factory test.
In PLL Bypass Mode, the output frequency is divided by NA, NB, or NC dividers.
Table 3H. Fast Lock Mode (FLM) Configuration Table
Input
FLM
0 (default)
1
Operation
Normal operation.
Fast PLL lock operation. Use this mode only during startup to decrease PLL lock time.
VCC = 3.3V
0V
tLOCK
VCXO-PLL Acquires Lock
VCXO-PLL Locked
LOCK
Fast Lock Mode
(High VCXO-PLL Bandwidth)
FLM
Nominal VCXO-PLL Bandwidth
Figure 1. Recommended Start-up Timing Diagram
Table 3I. Reset (nMR) Configuration Table
Input
nMR
0
1 (default)
Operation
The Femto-PLL is reset.
Normal operation.
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Table 3J. Output Disable (nSTOPA) Configuration Table.
Input
nSTOPA
0
1 (default)
Operation
QA[2:0]/nQA[2:0] outputs are stopped in logic LOW state. The assertion of nSTOPA is asynchronous
to the internal clock signal and may cause an output runt pulse.
Normal operation and outputs enabled.
Table 3K. Output Disable (nSTOPB) Configuration Table.
Input
nSTOPB
0
1 (default)
Operation
QB[1:0] / nQB[1:0] outputs are stopped in logic LOW state. The assertion of nSTOPB is
asynchronous to the internal clock signal and may cause an output runt pulse.
Normal operation and outputs enabled.
Table 3L. Output Disable (nSTOPC) Configuration Table.
Input
nSTOPC
0
1 (default)
Operation
QC[3:0] outputs are stopped in logic LOW state. The assertion of nSTOPC is asynchronous to the
internal clock signal and may cause an output runt pulse.
Normal operation and outputs enabled.
Table 3M. PLL Lock Status Output (LOCK_DT) Configuration Table.
Output
Conditions
Locked
Unlocked
LOCK_DT
Constantly HIGH.
HIGH with occasional LOW pulses.
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813078I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, VO (LVCMOS)
-0.5V to VCCO_CMOS+ 0.5V
Package Thermal Impedance, JA
31.8C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = VCCO_CMOS = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
VCCO,
Output Supply Voltage
VCCO_CMOS
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCC – 0.15
3.3
VCC
V
3.135
3.3
3.465
V
IEE
Power Supply Current
260
mA
ICCA
Analog Supply Current
15
mA
ICCO_CMOS
Output Supply Current
6
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO_CMOS = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
IIL
Input High Current
Input Low Current
Test Conditions
Minimum
Typical
CLK1, REF_SEL, MF,
FLM, NA[1:0], NB[1:0],
NC[1:0], R[2:0]
VCC = VIN = 3.465V
150
µA
nSTOP[A:C],
BYPASS[1:0], nMR
VCC = VIN = 3.465V
10
µA
CLK1, REF_SEL, MF,
FLM, NA[1:0], NB[1:0],
NC[1:0], R[2:0]
VCC = 3.465V,
VIN = 0V
-10
µA
nSTOP[A:C],
BYPASS[1:0], nMR
VCC = 3.465V,
VIN = 0V
-150
µA
2.6
V
VOH
Output High Voltage
QC0:QC3
IOH = -12mA
VOL
Output Low Voltage
QC0:QC3
IOL = 12mA
© 2016 Integrated Device Technology, Inc
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0.5
V
July 29, 2016
813078I Data Sheet
Table 4C. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
CLK0, nCLK0
Minimum
Typical
VCC = VIN = 3.465V
Maximum
Units
150
µA
CLK0
VCC = 3.465V, VIN = 0V
-10
µA
nCLK0
VCC = 3.465V, VIN = 0V
-150
µA
0.15
1.3
V
VEE + 0.5
VCC – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
V
VCCO – 2.0
VCCO – 1.7
V
0.6
1.0
V
NOTE 1: Outputs termination with 50 to VCCO – 2V.
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCO = VCCO_CMOS = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
fREF
fOUT
Parameter
Input Reference Frequency
Output Frequency
Test Conditions
Minimum
R=000
30.72MHz–50ppm
30.72MHz+50ppm
R=001
61.44MHz–50ppm
61.44MHz+50ppm
R=010
122.88MHz–50ppm
122.88MHz+50ppm
R=011
15.36MHz–50ppm
15.36MHz+50ppm
R=100
10MHz–50ppm
10MHz+50ppm
R=101
12.88MHz–50ppm
12.88MHz+50ppm
R=110
15MHz–50ppm
15MHz+50ppm
VCXO-PLL VCO Lock Range
fVCO
Femto-PLL VCO Lock Range
tjit(Ø)
RMS Phase Jitter
Integration Range:
12kHz - 20MHz;
NOTE 1
Period Jitter
R=111
20MHz–50ppm
MHz
MF=0, N=2
245.76
MHz
MF=0, N=4
122.88
MHz
MF=0, N=5
98.304
MHz
MF=0, N=8
61.44
MHz
MF=0, N=16
30.72
MHz
MF=1, N=1
614.4
MHz
MF=1, N=2
307.2
MHz
MF=1, N=4
153.6
MHz
MF=1, N=5
122.88
MHz
MF=1, N=8
76.8
MHz
38.4
30.72MHz–50ppm
MHz
30.72MHz+50ppm
MHz
491.52MHz
1.03
ps
QAn, QBn
153.6MHz, MF=20
0.92
ps
QAn, QBn
122.88MHz, MF=20
1.1
ps
QAn, QBn
122.88MHz, MF=16
1.1
ps
QAn, QBn
61.44MHz, MF=16
0.97
ps
QAn
QBn
153.6MHz, QCn = off
122.88MHz, QCn = off
35
ps
QAn, QBn
122.88MHz, QCn = off
30
ps
100Hz offset
N
20MHz+50ppm
491.52
10Hz offset
Single-Side
Band Noise at:
QAn =122.88MHz
Units
491.52, 614.4
QBn
tjit(per)
Maximum
MF=0, N=1
MF=1, N=16
fVCXO
Typical
1kHz offset
-41.3
30.72MHz XTAL,
fref = 30.72MHz,
10kHz offset
100kHz offset
QBn and QCn = 122.88MHz
1MHz offset
dBc/Hz
-71.5
dBc/Hz
-100.7
dBc/Hz
-127.2
dBc/Hz
-128.2
dBc/Hz
-131.4
dBc/Hz
continued on next page
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Symbol
Parameter
Test Conditions
Minimum
10Hz offset
100Hz offset
N
Single-Side
Band Noise at:
QAn = 61.44MHz
1kHz offset
30.72MHz XTAL,
fref = 30.72MHz,
10kHz offset
100kHz offset
QBn and QCn = 61.44MHz
1MHz offset
tsk(o)
Output Skew
NOTE 2, 3
tsk(b)
Bank Skew;
NOTE 2, 4
tR / tF
Output
Rise/ Fall Time
Output
Duty Cycle
Maximum
Units
-44.6
dBc/Hz
-77.2
dBc/Hz
-106.4
dBc/Hz
-132.8
dBc/Hz
-132.9
dBc/Hz
-137.9
dBc/Hz
fQA = fQB
across QAn and QBn
200
ps
fQA fQB
across QAn and QBn
300
ps
QAn/nQAn
50
ps
QBn/nQBn
50
ps
QCn
65
ps
QAn/nQAn
20% to 80%
100
600
ps
QBn/nQBn
20% to 80%
100
600
ps
QCn
20% to 80%
350
1050
ps
47
53
%
QAn/nQAn
odc
Typical
QBn/nQBn
N1
47
53
%
QBn/nQBn
N=1
43
57
%
45
55
%
QCn
NOTE: TA, Ambient Temperature applied using forced air flow.
NOTE 1: Phase jitter measured using a 30.72MHz quartz crystal.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
➝
Typical Phase Noise at 61.44MHz
Filter
➝
Raw Phase Noise Data
➝
Noise Power dBc
Hz
61.44MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.97ps (typical)
Phase Noise Result by adding
a filter to raw data
Offset Frequency (Hz)
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
➝
Typical Phase Noise at 122.88MHz
Filter
➝
Noise Power dBc
Hz
122.88MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.1ps (typical)
➝
Raw Phase Noise Data
Phase Noise Result by adding
a filter to raw data
Offset Frequency (Hz)
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
Parameter Measurement Information
1.65V±5%
1.65V±5%
1.65V±5%
1.65V±5%
SCOPE
VCC,
VCC,
VCCO
VCCO_CMOS
VCCA
VCCA
Qx
VEE
-1.65V±5%
-1.65V±5%
3.3V LVPECL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
Noise Power
VCC
nCLK0
V
PP
V
Cross Points
Phase Noise Mask
CMR
CLK0
f1
VEE
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Differential Input Level
RMS Phase Jitter
VOH
nQx
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Qx
nQy
Qy
Histogram
Mean Period
(First edge after trigger)
Period Jitter
© 2016 Integrated Device Technology, Inc
Differential Output Skew
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July 29, 2016
813078I Data Sheet
Parameter Measurement Information, continued
nQXn
VCCO
2
QCn
QXn
nQXn
VCCO
2
QCn
QXn
tsk(b)
tsk(b)
Where X = Bank QAn or Bank QBn
LVCMOS Bank Skew
Differential Bank Skew
nQA0:nQA2.
nQB0, nQB1
nQXn
QA0:QA2.
QB0, QB1
QXn
VCCO/2
QCn
tsk(bk-bk)
Where X = Bank QAn or Bank QBn
Output Rise/Fall Time
Differential Output Duty Cycle/Pulse Width/Period
QC0:QC3
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
LVCMOS Output Duty Cycle/Pulse Width/Period
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
Application Information
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of CL is dependant on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must
be taken with the package and load capacitance (CL). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with
the package, it is recommended that a metal-canned package like
HC49 be used. Generally, a metal-canned package has a larger
pulling range than a surface mounted device (SMD). For crystal
selection information, refer to the VCXO Crystal Selection
Application Note.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and CP values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. For other configurations, refer to the Loop Filter
Component Selection for VCXO Based PLLs Application Note.
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
The crystal’s load capacitance CL characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
LF0
LF1
ISET
RS
CP
RSET
CS
XTAL_IN
CTUNE
30.72MHz
If the crystal CL is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal CL is lower than the total external
XTAL_OUT
CTUNE
VCXO Characteristics Table
Symbol
Parameter
Typical
Units
kVCXO
VCXO Gain
9.3
kHz/V
CV_LOW
Low Varactor Capacitance
14.7
pF
CV_HIGH
High Varactor Capacitance
7.5
pF
VCXO-PLL Loop Bandwidth Selection Table
Bandwidth
Crystal Frequency (MHz)
MV
RS (k)
CS (µF)
CP (µF)
RSET (k)
8.5Hz (Low)
30.72
384
20
10
0.1
10
85Hz (Mid)
30.72
192
20
10
0.01
2.0
22.2kHz (High)
30.72
1
30
0.01
0.00001
2.2
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
Mode of Oscillation
fN
Frequency
fT
Frequency Tolerance
fS
Frequency Stability
Typical
Maximum
Units
Fundamental
30.72
Operating Temperature Range
-40
MHz
±20
ppm
±20
ppm
+85
0C
CL
Load Capacitance
10
pF
CO
Shunt Capacitance
4
pF
CO / C1
Pullability Ratio
ESR
Equivalent Series Resistance
20
Drive Level
1
mW
±3 per year
ppm
220
Aging @ 25 0C
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS813078I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, VCCO and
VCCO_CMOS should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 3 illustrates this for a generic VCC pin and also
shows that VCCA requires that an additional 10 resistor along with
a 10F bypass capacitor be connected to the VCCA pin.
© 2016 Integrated Device Technology, Inc
3.3V
VCC
0.01µF
VCCA
0.01µF
10µF
Figure 3. Power Supply Filtering
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July 29, 2016
813078I Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 4A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 4A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 4B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 4C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 4D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
3.3V
2.5V
3.3V
3.3V
2.5V
R3
120Ω
*R3
R4
120Ω
Zo = 60Ω
CLK
CLK
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
Differential
Input
SSTL
R1
120Ω
Differential
Input
Figure 4F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 4E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
© 2016 Integrated Device Technology, Inc
R2
120Ω
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July 29, 2016
813078I Data Sheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
CLK Input
LVCMOS Outputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50W transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 5A and
5B show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it would be
recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 5A. 3.3V LVPECL Output Termination
© 2016 Integrated Device Technology, Inc
R2
84
Figure 5B. 3.3V LVPECL Output Termination
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813078I Data Sheet
EPAD Thermal Release Path
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 6. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
SOLDER
PIN PAD
Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS813078I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS813078I is the sum of the core power plus the power dissipated in the load(s). The following is the
power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVPECL Output Power Dissipation
•
Power (core)_MAX = VCC_MAX *IEE_MAX = 3.465V * 260mA = 900.9mW
Power (output)_MAX = 30mW/Loaded Output Pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VCCO/2
Output Current IOUT = VCCO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 10.7mW * 4 = 42.8mW
•
Dynamic Power Dissipation at 153.6MHz
Power (25MHz) = CPD * Frequency * (VCCO)2 = 10pF * 153.6MHz * (3.465V)2 = 18mW per output
Total Power (153.6MHz) = 18mW * 4 = 72mW
Total Power Dissipation
•
Total Power
= Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (153.6MHz)
= 900.9mW + 150mW + 42.8mW + 72mW
= 1165.7mW
© 2016 Integrated Device Technology, Inc
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813078I Data Sheet
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 31.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.166W * 31.8°C/W = 122.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 64 Lead TQFP, E-Pad Forced Convection
JA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
© 2016 Integrated Device Technology, Inc
0
1
2.5
31.8°C/W
25.8°C/W
24.2°C/W
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July 29, 2016
813078I Data Sheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 64 Lead TQFP, E-Pad
JA vs. Air Flow
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
31.8°C/W
25.8°C/W
24.2°C/W
Transistor Count
The transistor count for ICS813078I is: 6235
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 64 Lead TQFP, E-Pad
-HD VERSION
EXPOSED PAD DOWN
Table 8. Package Dimensions for 64 Lead TQFP, E-Pad
Symbol
N
A
A1
A2
b
c
D&E
D1 & E1
D2 & E2
D3 & E3
e
L
ccc
JEDEC Variation: ACD
All Dimensions in Millimeters
Minimum
Nominal
Maximum
64
1.20
0.05
0.10
0.15
0.95
1.00
1.05
0.17
0.22
0.27
0.09
0.20
12.00 Basic
10.00 Basic
7.50 Ref.
4.5
5.0
5.5
0.50 Basic
0.45
0.60
0.75
0°
7°
0.08
Reference Document: JEDEC Publication 95, MS-026
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
813078BYILF
ICS813078BYILF
“Lead-Free” 64 Lead TQFP, E-Pad
Tray
-40C to +85C
813078BYILFT
ICS813078BYILF
“Lead-Free” 64 Lead TQFP, E-Pad
500 Tape & Reel
-40C to +85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History
1/26/15
Product Discontinuation Notice - CQ-15-01
7/29/16
Replaced PDN with OBSOLETE on front page.
© 2016 Integrated Device Technology, Inc
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July 29, 2016
813078I Data Sheet
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DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
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© 2016 Integrated Device Technology, Inc
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July 29, 2016
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