813N252BKI-04LFT

813N252I-04 VCXO Jitter Attenuator & FemtoClock® NG Multiplier Datasheet General Description Features The 813N252I-04 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® NG frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. • Fourth generation FemtoClock® Next Generation (NG) technology • One LVPECL output pair and one LVDS output pair Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz • Attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode VCXO crystal • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection • FemtoClock NG frequency multiplier provides low jitter, high frequency output • • • Absolute pull range: 100ppm • • • 3.3V supply voltage FemtoClock NG VCO frequency: 625MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package nCLK1 CLK1 VCC nCLK0 CLK0 XTAL_IN XTAL_OUT VCCX Pin Assignment 32 31 30 29 28 27 26 25 LF1 1 24 LF0 2 23 nQB ISET 3 VEE 4 VEE 22 QB 21 VCCO CLK_SEL 5 20 nQA VCC 6 19 QA RESERVED 7 VEE 17 ODASEL_0 ODASEL_1 ODBSEL_0 ODBSEL_1 VCC PDSEL_1 VCCA 10 11 12 13 14 15 16 PDSEL_0 9 PDSEL_2 VEE 8 18 813N252I-04 32 Lead VFQFN 5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm EPad K Package Top View ©2015 Integrated Device Technology, Inc. 1 Revision C, December 11, 2015 813N252I-04 Datasheet XTAL_IN LF1 LF0 ISET Loop Filter XTAL_OUT Block Diagram 25MHz Output Divider PDSEL_[2:0] CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Pullup 3 Pulldown PU/PD 0 Pulldown PU/PD Pulldown 1 VCXO Input Pre-Divider 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440 (default) 00 = 25 (default) 01 = 5 10 = 4 11 = 2 Phase Detector VCXO Charge Pump VCXO Feedback Divider ÷3125 VCXO Jitter Attenuation PLL FemtoClock NG PLL 625MHz 2 Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 2 ©2015 Integrated Device Technology, Inc. 2 Pulldown Pulldown LVDS QA nQA ODASEL_[1:0] LVPECL QB nQB ODBSEL_[1:0] Revision C, December 11, 2015 813N252I-04 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 LF1, LF0 Analog Input/Output Loop filter connection node pins. LF0 is the output. LF1 is the input. 3 ISET Analog Input/Output Charge pump current setting pin. 4, 8, 18, 24 VEE Power 5 CLK_SEL Input 6, 12, 27 VCC Power 7 RESERVED Reserved 9, 10, 11 PDSEL_2, PDSEL_1, PDSEL_0 Input 13 VCCA Power 14, 15 ODBSEL_1, ODBSEL_0 Input Pulldown Frequency select pins for QB, nQB outputs. See Table 3B. LVCMOS/LVTTL interface levels. 16, 17 ODASEL_1, ODASEL_0 Input Pulldown Frequency select pins for QA, nQA outputs. See Table 3B. LVCMOS/LVTTL interface levels. 19, 20 QA, nQA Output Differential clock outputs. LVDS interface levels. 21 VCCO Power Output supply pin. 22, 23 QB, nQB Output Differential clock outputs. LVPECL interface levels. 25 nCLK1 Input Pullup/ Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 26 CLK1 Input Pulldown Non-inverting differential clock input. 28 nCLK0 Input Pullup/ Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 29 CLK0 Input Pulldown Non-inverting differential clock input. 30, 31 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 32 VCCX Power Power supply pin for the XTAL oscillator regulator. Negative supply pins. Pulldown Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Core supply pins. Reserve pin. Do not connect. Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ©2015 Integrated Device Technology, Inc. Test Conditions 3 Minimum Typical Maximum Units Revision C, December 11, 2015 813N252I-04 Datasheet Function Tables Table 3A. Pre-Divider Selection Function Table Inputs PDSEL_2 PDSEL_1 PDSEL_0 Pre-Divider Value 0 0 0 1 0 0 1 193 0 1 0 256 0 1 1 2430 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) Table 3B. Output Divider Function Table Inputs ODxSEL_1 ODxSEL_0 Output Divider Value 0 0 25 (default) 0 1 5 1 0 4 1 1 2 Table 3C. CLK_SEL Function Table Input CLK_SEL Selected Input 0 CLK0, nCLK0 1 CLK1, nCLK1 ©2015 Integrated Device Technology, Inc. 4 Revision C, December 11, 2015 813N252I-04 Datasheet Table 3D. Frequency Function Table Input Frequency (MHz) Pre-Divider Value VCXO Frequency (MHz) FemtoClock Feedback Divider Value FemtoClock VCO Frequency (MHz) Output Divider Value Output Frequency (MHz) 0.008 1 25 25 625 25 25 0.008 1 25 25 625 5 125 0.008 1 25 25 625 4 156.25 0.008 1 25 25 625 2 312.5 1.544 193 25 25 625 25 25 1.544 193 25 25 625 5 125 1.544 193 25 25 625 4 156.25 1.544 193 25 25 625 2 312.5 2.048 256 25 25 625 25 25 2.048 256 25 25 625 5 125 2.048 256 25 25 625 4 156.25 2.048 256 25 25 625 2 312.5 19.44 2430 25 25 625 25 25 19.44 2430 25 25 625 5 125 19.44 2430 25 25 625 4 156.25 19.44 2430 25 25 625 2 312.5 25 3125 25 25 625 25 25 25 3125 25 25 625 5 125 25 3125 25 25 625 4 156.25 25 3125 25 25 625 2 312.5 77.76 9720 25 25 625 25 25 77.76 9720 25 25 625 5 125 77.76 9720 25 25 625 4 156.25 77.76 9720 25 25 625 2 312.5 125 15625 25 25 625 25 25 125 15625 25 25 625 5 125 125 15625 25 25 625 4 156.25 125 15625 25 25 625 2 312.5 155.52 19440 25 25 625 25 25 155.52 19440 25 25 625 5 125 155.52 19440 25 25 625 4 156.25 155.52 19440 25 25 625 2 312.5 ©2015 Integrated Device Technology, Inc. 5 Revision C, December 11, 2015 813N252I-04 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.20 3.3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V VCCX Charge Pump Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 225 mA ICCA Analog Supply Current 20 mA ICCX Charge Pump Supply Current 20 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] VCC = VIN = 3.465V 150 µA PDSEL_[0:2] VCC = VIN = 3.465V 10 µA CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] VCC = 3.465V, VIN = 0V -10 µA PDSEL_[0:2] VCC = 3.465, VIN = 0V -150 µA ©2015 Integrated Device Technology, Inc. 6 Revision C, December 11, 2015 813N252I-04 Datasheet Table 4C. Differential DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE VCC – 0.85 V CLK0, nCLK0, CLK1, nCLK1 Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA CLK0, CLK1 VCC = 3.465V, VIN = 0V -10 µA nCLK0, nCLK1 VCC = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined at the cross point. Table 4D. LVPECL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO – 1.10 VCCO – 0.75 V VCCO – 2.0 VCCO – 1.60 V 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit. Table 4E. LVDS DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ©2015 Integrated Device Technology, Inc. Test Conditions Minimum 247 1.125 7 Typical Maximum Units 454 mV 60 mV 1.375 V 50 mV Revision C, December 11, 2015 813N252I-04 Datasheet AC Electrical Characteristics Table 5. AC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter fIN Input Frequency fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random); NOTE 1 tjit(pk-pk) Peak-to-Peak Jitter tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK PLL Lock Time Test Conditions Minimum 25MHz crystal Frequency Maximum Units 0.008 155.52 MHz 25 312.5 MHz 0.7 ps fOUT = 125MHz, 156.25MHz, 312.5MHz, 25MHz crystal, Integration Range: 12kHz – 20MHz Typical 0.3 QA 1e -12BER 60 ps QB 1e -12BER 25 ps 75 ps QA 20% to 80% 150 400 ps QB 20% to 80% 150 500 ps 48 52 % 6 s NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage. Measured at the output differential cross points. ©2015 Integrated Device Technology, Inc. 8 Revision C, December 11, 2015 813N252I-04 Datasheet Noise Power dBc Hz Typical Phase Noise Offset Frequency (Hz) ©2015 Integrated Device Technology, Inc. 9 Revision C, December 11, 2015 813N252I-04 Datasheet Parameter Measurement Information 2V 2V 2V VCC, VCCO SCOPE VCCX SCOPE VCC, 3.3V±5% POWER SUPPLY + Float GND – Qx VCCA Qx VCCO VCCA VCCX nQx nQx VEE -1.3V±0.165V 3.3V LVDS Output Load Test Circuit 3.3V LVPECL Output Load Test Circuit VCC nQA QA nCLK[0:1] nQB CLK[0:1] QB VEE Output Skew Differential Input Level nQA, nQB QA, QB RMS Phase Jitter ©2015 Integrated Device Technology, Inc. Output Duty Cycle/Pulse Width/Period 10 Revision C, December 11, 2015 813N252I-04 Datasheet Parameter Measurement Information, continued nQB nQA 80% 80% VOD QA 20% 20% tR QB tF LVDS Output Rise/Fall Time LVPECL Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup VCXO & FemtoClock PLL Lock Time ©2015 Integrated Device Technology, Inc. 11 Revision C, December 11, 2015 813N252I-04 Datasheet Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 813N252I-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO and VCCX should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω VCCX 10Ω .01µF 10µF VCCA .01µF 10µF Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. Similarly, if the input clock swing is 1.8V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 0.9V. It is recommended to always use R1 and R2 to provide a known V1 voltage. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2015 Integrated Device Technology, Inc. 12 Revision C, December 11, 2015 813N252I-04 Datasheet Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 3.3V 2.5V R3 120Ω R4 120Ω Zo = 60Ω *R3 CLK CLK Zo = 60Ω nCLK nCLK HCSL *R4 SSTL Differential Input R1 120Ω Differential Input Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ©2015 Integrated Device Technology, Inc. R2 120Ω 13 Revision C, December 11, 2015 813N252I-04 Datasheet Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins LVDS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 4A. 3.3V LVPECL Output Termination ©2015 Integrated Device Technology, Inc. R2 84 Figure 4B. 3.3V LVPECL Output Termination 14 Revision C, December 11, 2015 813N252I-04 Datasheet LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 5A can be used with either type of output structure. Figure 5B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  ZT ZT LVDS Receiver Figure 5A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 5B. Optional Termination LVDS Termination ©2015 Integrated Device Technology, Inc. 15 Revision C, December 11, 2015 813N252I-04 Datasheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ©2015 Integrated Device Technology, Inc. 16 Revision C, December 11, 2015 813N252I-04 Datasheet Schematic Example Figure 7 shows an example of 813N252I-04 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. Two examples of LVPECL and one example of LVDS terminations are   shown in this schematic. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used. VCC R1 125 R2 125 Logic Control Input Examples CLK1 Zo = 50 Set Logic Input to '1' VCC nCLK1 Zo = 50 RU1 1K VCC LVPECL Driver R5 125 R3 84 R6 125 R4 84 Set Logic Input to '0' VCC RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K CLK0 Zo = 50 nCLK0 Zo = 50 R7 84 LVPECL Driver XTAL_OUT R8 85 3.3V C1 TUNE R10 133 X1 R11 133 Zo = 50 Ohm XTAL_IN VCC VCC + C2 TUNE CLK0 nCLK0 Zo = 50 Ohm 10 VCCX C5 0.01u U1 LF CLK_SEL C8 0.1u 1 2 3 4 5 6 7 8 R15 2.21K R9 Rs 470k Cs 0.2uF VEE nQB QB VCCO nQA QA VEE ODASEL_0 LF1 LF0 ISET VEE CLK_SEL VCC RESERVED VEE 3-pole loop filter example - (optional) LF 0.1u C7 LF VCC TBDk LVPECL Termination nQB QB nQA QA + ODASEL_0 R20 100 - LVDS Termination Zo = 50 Ohm + VCC Cp 0.002uF R14 82.5 VCC = VCCX = VCCO= 3.3V 24 23 22 21 20 19 18 17 PDSEL_2 PDSEL_1 PDSEL_0 VCC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1 Cs 0.2uF VCC R13 82.5 9 10 11 12 13 14 15 16 Cp 0.002uF PDSEL_2 PDSEL_1 PDSEL_0 LF 0.1u VCCX XTAL_IN XTAL_OUT CLK0 nCLK0 VCC CLK1 nCLK1 2-pole loop filter for Mid Bandwidth setting Rs 470k VCCO 32 31 30 29 28 27 26 25 C6 10u - C4 ODBSEL_1 ODBSEL_0 ODASEL_1 R12 C3 TBDpF VCCA R19 10 Zo = 50 Ohm - VCC C9 0.1u R16 50 C10 0.01u R17 50 C11 10u LVPECL Optional Y-Termination R18 50 Figure 7. 813N252I-04 Schematic Example ©2015 Integrated Device Technology, Inc. 17 Revision C, December 11, 2015 813N252I-04 Datasheet VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. VCXO Characteristics Table The crystal’s load capacitance (CL) characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). Parameter Typical Units kVCXO VCXO Gain 4.4 kHz/V CV_LOW Low Varactor Capacitance 8 pF CV_HIGH High Varactor Capacitance 16 pF VCXO-PLL Loop Bandwidth Selection Table If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal (CL) is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of (CL) is dependant on the characteristics of the VCXO. The recommended (CL) in the Crystal Parameter Table balances the tuning range by centering the tuning curve. Bandwidth Crystal Frequency (MHz) M RS (k) CS (µF) CP (µF) RSET (k) 8Hz (Low) 25 3125 680 0.20 0.002 22 20Hz (Mid) 25 3125 470 0.20 0.002 5 75Hz (High) 25 3125 680 0.02 0.000 3 2.2 NOTE: When configuring the 813N252I-04 with PLL loop bandwidth less than 75Hz, it is recommended that CLK1, nCLK1 input be used as the only reference clock. In systems where both reference clocks are used, it is recommended to have PLL loop bandwidths of 75Hz or greater. The frequency of oscillation in the LF0 third overtone mode is not LF1 ISET necessarily at exactly three times RS RSET the fundamental frequency. The mechanical properties of the CP CS quartz element dictate the position of the overtones relative to the fundamental. The oscillator XTAL_IN circuit may excite both the CTUNE fundamental and overtone modes 25MHz simultaneously. This will cause a XTAL_OUT nonlinearity in the tuning curve. CTUNE This potential problem is why VCXO crystals are required to be tested for absence of any activity inside a ±200 ppm window at three times the fundamental frequency. Refer to FL_3OVT and FL_3OVT_spurs in the crystal Characteristics table. ©2015 Integrated Device Technology, Inc. Symbol 18 Revision C, December 11, 2015 813N252I-04 Datasheet Crystal Characteristics Symbol Parameter Test Conditions Minimum Mode of Oscillation fN Frequency fT Frequency Tolerance fS Frequency Stability Typical Maximum Units Fundamental 25 Operating Temperature Range -40 MHz ±20 ppm ±20 ppm 85 0 C CL Load Capacitance 10 pF CO Shunt Capacitance 4 pF CO / C1 Pullability Ratio FL_3OVT 3rd Overtone FL 200 ppm FL_3OVT_spurs 3rd Overtone FL Spurs 200 ppm ESR Equivalent Series Resistance 20  Drive Level 1 mW Aging @ 25 0C ©2015 Integrated Device Technology, Inc. 220 240 First Year ±3 ppm Ten Year ±10 ppm 19 Revision C, December 11, 2015 813N252I-04 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 813N252I-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 813N252I-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core_LVDS)MAX = VCC_MAX * IEE_MAX = 3.465V * 225mA = 779.625mW • Power (outputs)MAX = 31.55mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 779.625mW + 31.55mW = 811.175mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.811W * 37°C/W = 115°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2015 Integrated Device Technology, Inc. 0 1 2.5 37.0°C/W 32.4°C/W 29°C/W 20 Revision C, December 11, 2015 813N252I-04 Datasheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V (VCCO_MAX – VOH_MAX) = 0.75V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V (VCCO_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.75V)/50] * 0.75V = 18.75mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.6V)/50] * 1.6V = 12.80mW Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW ©2015 Integrated Device Technology, Inc. 21 Revision C, December 11, 2015 813N252I-04 Datasheet Reliability Information Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29°C/W Transistor Count The transistor count for 813N252I-04 is: 22,280 ©2015 Integrated Device Technology, Inc. 22 Revision C, December 11, 2015 813N252I-04 Datasheet Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N Anvil Anvil Singulation Singula tion e (Ty p.) 2 If N & N 1 are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D e N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C Bottom View w/Type A ID D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 Th er mal Ba se D2 2 N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pin out are shown on the front page. The package dimensions are in Table 8. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 & N 8 ND E D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ©2015 Integrated Device Technology, Inc. 23 Revision C, December 11, 2015 813N252I-04 Datasheet Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 813N252BKI-04LF ICS252BI04L “Lead-Free” 32 Lead VFQFN Tray -40C to 85C 813N252BKI-04LFT ICS252BI04L “Lead-Free” 32 Lead VFQFN Tape & Reel -40C to 85C ©2015 Integrated Device Technology, Inc. 24 Revision C, December 11, 2015 813N252I-04 Datasheet Revision History Sheet Rev Table Page 4C 4D 7 7 A 12 A 6 Description of Change Date Differential DC Characteristics Table - redefined VCMR min. to standard levels as the crosspoint. Changed from 0.5V min. to VEE. Updated Notes. LVPECL DC Characteristics Table - corrected VOH/VOL Parameter verbiage from Current to Voltage and corrected units to “V”. Updated “Wiring the Differential Input to Accept Single-ended Levels”. 3/18/10 Supply Voltage, VCC. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03. 5/24/11 Per PCN #N1210-01 changed revision marking from “A” to “B” in page footer and ordering information table. B T9 C 11 Parameter Measurement Information Section - added LockTime diagram. 12 Updated Wiring the Differential Input to Accept Single-ended Levels Application Note. 15 Updated LVDS Driver Termination Application Note. 18 VCXO-PLL External Components: VCXO-PLL Loop Bandwidth Selection Table - added note. Crystal Characteristics - added “Ten Year” spec to Aging row. 22 Updated Package Outline. 23 Ordering Information Table - changed revision marking from “A” to “B”; deleted Tape & Reel Count; deleted note. Updated header/footer. Deleted “ICS” prefix from part number. ©2015 Integrated Device Technology, Inc. 25 1/18/13 12/11/15 Revision C, December 11, 2015 813N252I-04 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2015 Integrated Device Technology, Inc. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.