813N252AKI-04LFT

VCXO Jitter Attenuator & FemtoClock® NG Multiplier ICS813N252I-04 DATA SHEET General Description Features The ICS813N252I-04 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® NG frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. • Fourth generation FemtoClock® Next Generation (NG) technology • One LVPECL output pair and one LVDS output pair Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz • Attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode VCXO crystal • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection • FemtoClock NG frequency multiplier provides low jitter, high frequency output • • • Absolute pull range: 100ppm • • • 3.3V supply voltage RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package nCLK1 CLK1 VCC nCLK0 CLK0 XTAL_IN XTAL_OUT VCCX Pin Assignment FemtoClock NG VCO frequency: 625MHz 32 31 30 29 28 27 26 25 LF1 1 24 LF0 2 23 nQB VEE ISET 3 22 QB VEE 4 21 VCCO CLK_SEL 5 20 nQA VCC 6 19 QA RESERVED 7 18 VEE 17 ODASEL_0 ODASEL_1 ODBSEL_0 ODBSEL_1 VCC PDSEL_1 VCCA 10 11 12 13 14 15 16 PDSEL_0 9 PDSEL_2 VEE 8 ICS813N252I-04 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS813N252AKI-04 REVISION A MAY 24, 2011 1 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet XTAL_IN LF1 LF0 ISET Loop Filter XTAL_OUT Block Diagram 25MHz Output Divider PDSEL_[2:0] CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Pullup 3 Pulldown PU/PD 0 Pulldown PU/PD Pulldown 1 VCXO Input Pre-Divider 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440 (default) 00 = 25 (default) 01 = 5 10 = 4 11 = 2 Phase Detector VCXO Charge Pump VCXO Feedback Divider ÷3125 VCXO Jitter Attenuation PLL FemtoClock NG PLL 625MHz 2 Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 2 ICS813N252AKI-04 REVISION A MAY 24, 2011 2 Pulldown Pulldown LVDS QA nQA ODASEL_[1:0] LVPECL QB nQB ODBSEL_[1:0] ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2 LF1, LF0 Analog Input/Output Loop filter connection node pins. LF0 is the output. LF1 is the input. 3 ISET Analog Input/Output Charge pump current setting pin. 4, 8, 18, 24 VEE Power 5 CLK_SEL Input 6, 12, 27 VCC Power 7 RESERVED Reserved 9, 10, 11 PDSEL_2, PDSEL_1, PDSEL_0 Input 13 VCCA Power 14, 15 ODBSEL_1, ODBSEL_0 Input Pulldown Frequency select pins for QB, nQB outputs. See Table 3B. LVCMOS/LVTTL interface levels. 16, 17 ODASEL_1, ODASEL_0 Input Pulldown Frequency select pins for QA, nQA outputs. See Table 3B. LVCMOS/LVTTL interface levels. 19, 20 QA, nQA Output Differential clock outputs. LVDS interface levels. 21 VCCO Power Output supply pin. 22, 23 QB, nQB Output Negative supply pins. Pulldown Input clock select. When HIGH selects CLK1/nCLK1. When LOW, selects CLK0/nCLK0. LVCMOS / LVTTL interface levels. Core supply pins. Reserve pin. Do not connect. Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Differential clock outputs. LVPECL interface levels. 25 nCLK1 Input Pullup/ Pulldown 26 CLK1 Input Pulldown Non-inverting differential clock input. 28 nCLK0 Input Pullup/ Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 29 CLK0 Input Pulldown Non-inverting differential clock input. 30, 31 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 32 VCCX Power Power supply pin for the XTAL oscillator regulator. Inverting differential clock input. VCC/2 bias voltage when left floating. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS813N252AKI-04 REVISION A MAY 24, 2011 Test Conditions 3 Minimum Typical Maximum Units ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Function Tables Table 3A. Pre-Divider Selection Function Table Inputs PDSEL_2 PDSEL_1 PDSEL_0 Pre-Divider Value 0 0 0 1 0 0 1 193 0 1 0 256 0 1 1 2430 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) Table 3B. Output Divider Function Table Inputs ODxSEL_1 ODxSEL_0 Output Divider Value 0 0 25 (default) 0 1 5 1 0 4 1 1 2 Table 3C. CLK_SEL Function Table Input CLK_SEL Selected Input 0 CLK0, nCLK0 1 CLK1, nCLK1 ICS813N252AKI-04 REVISION A MAY 24, 2011 4 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Table 3D. Frequency Function Table Input Frequency (MHz) Pre-Divider Value 0.008 1 0.008 VCXO Frequency (MHz) FemtoClock Feedback Divider Value FemtoClock VCO Frequency (MHz) Output Divider Value Output Frequency (MHz) 25 25 625 25 25 1 25 25 625 5 125 0.008 1 25 25 625 4 156.25 0.008 1 25 25 625 2 312.5 1.544 193 25 25 625 25 25 1.544 193 25 25 625 5 125 1.544 193 25 25 625 4 156.25 1.544 193 25 25 625 2 312.5 2.048 256 25 25 625 25 25 2.048 256 25 25 625 5 125 2.048 256 25 25 625 4 156.25 2.048 256 25 25 625 2 312.5 19.44 2430 25 25 625 25 25 19.44 2430 25 25 625 5 125 19.44 2430 25 25 625 4 156.25 19.44 2430 25 25 625 2 312.5 25 3125 25 25 625 25 25 25 3125 25 25 625 5 125 25 3125 25 25 625 4 156.25 25 3125 25 25 625 2 312.5 77.76 9720 25 25 625 25 25 77.76 9720 25 25 625 5 125 77.76 9720 25 25 625 4 156.25 77.76 9720 25 25 625 2 312.5 125 15625 25 25 625 25 25 125 15625 25 25 625 5 125 125 15625 25 25 625 4 156.25 125 15625 25 25 625 2 312.5 155.52 19440 25 25 625 25 25 155.52 19440 25 25 625 5 125 155.52 19440 25 25 625 4 156.25 155.52 19440 25 25 625 2 312.5 ICS813N252AKI-04 REVISION A MAY 24, 2011 5 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.20 3.3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V VCCX Charge Pump Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 225 mA ICCA Analog Supply Current 20 mA ICCX Charge Pump Supply Current 20 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] VCC = VIN = 3.465V 150 µA PDSEL_[0:2] VCC = VIN = 3.465V 10 µA CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] VCC = 3.465V, VIN = 0V -10 µA PDSEL_[0:2] VCC = 3.465, VIN = 0V -150 µA ICS813N252AKI-04 REVISION A MAY 24, 2011 6 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Table 4C. Differential DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE VCC – 0.85 V CLK0, nCLK0, CLK1, nCLK1 Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA CLK0, CLK1 VCC = 3.465V, VIN = 0V -10 µA nCLK0, nCLK1 VCC = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined at the crosspoint. Table 4D. LVPECL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO – 1.10 VCCO – 0.75 V VCCO – 2.0 VCCO – 1.60 V 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit. Table 4E. LVDS DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change ICS813N252AKI-04 REVISION A MAY 24, 2011 Test Conditions Minimum 247 1.125 7 Typical Maximum Units 454 mV 60 mV 1.375 V 50 mV ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet AC Electrical Characteristics Table 5. AC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter fIN Input Frequency fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random); NOTE 1 tjit(pk-pk) Peak-to-Peak Jitter tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK PLL Lock Time Test Conditions Minimum 25MHz crystal Frequency Maximum Units 0.008 155.52 MHz 25 312.5 MHz 0.7 ps fOUT = 125MHz, 156.25MHz, 312.5MHz, 25MHz crystal, Integration Range: 12kHz – 20MHz Typical 0.3 QA 1e -12BER 60 ps QB 1e -12BER 25 ps 75 ps QA 20% to 80% 150 400 ps QB 20% to 80% 150 500 ps 48 52 % 6 s NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage. Measured at the output differential cross points. ICS813N252AKI-04 REVISION A MAY 24, 2011 8 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Noise Power dBc Hz Typical Phase Noise Offset Frequency (Hz) ICS813N252AKI-04 REVISION A MAY 24, 2011 9 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Parameter Measurement Information 2V 2V 2V VCC, VCCO VCCX SCOPE 3.3V±5% POWER SUPPLY + Float GND – Qx VCCA SCOPE VCC, VCCO VCCXVCCA Qx LVDS nQx LVPECL nQx VEE -1.3V±0.165V 3.3V LVDS Output Load AC Test Circuit 3.3V LVPECL Output Load AC Test Circuit VCC nQA QA nCLK[0:1] V V Cross Points PP nQB CMR CLK[0:1] QB t sk(o) VEE Output Skew Differential Input Level Phase Noise Plot Noise Power nQA, nQB QA, QB t PW t f1 Offset Frequency odc = PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Output Duty Cycle/Pulse Width/Period RMS Phase Jitter ICS813N252AKI-04 REVISION A MAY 24, 2011 10 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Parameter Measurement Information, continued nQB nQA 80% 80% 80% 80% VOD QA VSW I N G 20% 20% tR QB 20% 20% tF tF tR LVPECL Output Rise/Fall Time LVDS Output Rise/Fall Time VDD VDD out LVDS ➤ out ➤ out DC Input ➤ LVDS 100 ➤ VOD/∆ VOD VOS/∆ VOS out ➤ DC Input ➤ Differential Output Voltage Setup Offset Voltage Setup ICS813N252AKI-04 REVISION A MAY 24, 2011 11 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813N252I-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO and VCCX should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω VCCX 10Ω .01µF 10µF VCCA .01µF 10µF Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS813N252AKI-04 REVISION A MAY 24, 2011 12 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω Zo = 50Ω nCLK nCLK LVHSTL R1 50Ω IDT LVHSTL Driver R2 50Ω Differential Input LVPECL Differential Input R1 50Ω R2 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V R4 125Ω 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK Differential Input LVPECL R1 84Ω R2 84Ω nCLK Zo = 50Ω Receiver LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS813N252AKI-04 REVISION A MAY 24, 2011 13 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins LVDS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V Zo = 50Ω + + _ LVPECL Input Zo = 50Ω _ LVPECL R1 50Ω R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 84Ω RTT Figure 4A. 3.3V LVPECL Output Termination ICS813N252AKI-04 REVISION A MAY 24, 2011 Input Zo = 50Ω Figure 4B. 3.3V LVPECL Output Termination 14 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 5. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS813N252AKI-04 REVISION A MAY 24, 2011 15 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Schematic Example terminations are shown in this schematic. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used. Figure 7 shows an example of ICS813N252I-04 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. Two examples of LVPECL and one example of LVDS VCC R1 125 R2 125 Logic Control Input Examples CLK1 Zo = 50 Set Logic Input to '1' VCC nCLK1 Zo = 50 RU1 1K VCC LVPECL Driv er R5 125 R3 84 R6 125 R4 84 Set Logic Input to '0' VCC RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K CLK0 Zo = 50 nCLK0 Zo = 50 R7 84 LVPECL Driv er XTAL_OUT R8 85 3.3V C1 TUNE R10 133 X1 R11 133 Zo = 50 Ohm XTAL_IN VCC VCC + C2 TUNE C LK0 nC LK0 Zo = 50 Ohm R12 10 VCCX C5 0.01u U1 LF CLK_SEL C8 0.1u R15 2.21K 3-pole loop filter example - (optional) R9 LF Rs 470k Cs 0.2uF VEE nQB QB VCCO nQA QA VEE ODASEL_0 LF VCC TBDk C3 TBDpF LVPECL Termination nQB QB nQA QA + ODASEL_0 R20 100 - LVDS Termination Zo = 50 Ohm + VCC Cp 0.002uF VCCA R19 10 Zo = 50 Ohm - VCC C9 0.1u R16 50 C10 0.01u R14 82.5 VCC = VCCX = VCCO= 3.3V 24 23 22 21 20 19 18 17 PD SEL_2 PD SEL_1 PD SEL_0 VC C VC C A OD BSEL_1 OD BSEL_0 OD ASEL_1 VCC LF1 LF0 ISET VEE CLK_SEL VCC RESERVED VEE 9 10 11 12 13 OD BSEL_1 14 OD BSEL_0 15 OD ASEL_1 16 Cp 0.002uF Cs 0.2uF 1 2 3 4 5 6 7 8 PD SEL_2 PD SEL_1 PD SEL_0 Rs 470k R13 82.5 0.1u C7 VC C X XT AL_IN XT AL_OU T C LK0 nC LK0 VC C C LK1 nC LK1 2-pole loop filter for Mid Bandwidth setting LF VCCO 0.1u 32 31 30 29 28 27 26 25 C6 10u - C4 R17 50 C11 10u LVPECL Optional Y-Termination R18 50 Figure 7. ICS813N252I-04 Schematic Example ICS813N252AKI-04 REVISION A MAY 24, 2011 16 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The frequency of oscillation in LF0 the third overtone mode is not LF1 ISET necessarily at exactly three RS RSET times the fundamental frequency. The mechanical CP CS properties of the quartz element dictate the position of the overtones relative to the XTAL_IN fundamental. The oscillator CTUNE circuit may excite both the 25MHz fundamental and overtone XTAL_OUT modes simultaneously. This will CTUNE cause a nonlinearity in the tuning curve. This potential problem is why VCXO crystals are required to be tested for absence of any activity inside a ±200 ppm window at three times the fundamental frequency. Refer to FL_3OVT and FL_3OVT_spurs in the crystal Characteristics table. The crystal’s load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. VCXO Characteristics Table Symbol Parameter Typical Units kVCXO VCXO Gain 4.4 kHz/V CV_LOW Low Varactor Capacitance 8 pF CV_HIGH High Varactor Capacitance 16 pF VCXO-PLL Loop Bandwidth Selection Table Bandwidth Crystal Frequency (MHz) M RS (kΩ) CS (µF) CP (µF) RSET (kΩ) 8Hz (Low) 25 3125 680 0.20 0.002 22 20Hz (Mid) 25 3125 470 0.20 0.002 5 75Hz (High) 25 3125 680 0.02 0.0003 2.2 Crystal Characteristics Symbol Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental fN Frequency 25 fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm Operating Temperature Range CL Load Capacitance CO Shunt Capacitance CO / C1 Pullability Ratio FL_3OVT 3rd Overtone FL -40 3 Overtone FL Spurs ESR Equivalent Series Resistance 17 C pF 240 200 ppm 200 ppm 20 Aging @ 25 0C 0 pF 4 220 Drive Level ICS813N252AKI-04 REVISION A MAY 24, 2011 85 10 rd FL_3OVT_spurs MHz Ω 1 mW ±3 per year ppm ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS813N252I-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS813N252I-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core_LVDS)MAX = VCC_MAX * IEE_MAX = 3.465V * 225mA = 779.625mW • Power (outputs)MAX = 31.55mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 779.625mW + 31.55mW = 811.175mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.811W * 37°C/W = 115°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS813N252AKI-04 REVISION A MAY 24, 2011 0 1 2.5 37.0°C/W 32.4°C/W 29°C/W 18 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V (VCCO_MAX – VOH_MAX) = 0.75V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V (VCCO_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.75V)/50Ω] * 0.75V = 18.75mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.6V)/50Ω] * 1.6V = 12.80mW Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW ICS813N252AKI-04 REVISION A MAY 24, 2011 19 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Reliability Information Table 7. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29°C/W Transistor Count The transistor count for ICS813N252I-04 is: 22,280 ICS813N252AKI-04 REVISION A MAY 24, 2011 20 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N Anvil Anvil Singulation Singula tion or OR Sawn Singulation To p View L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D e N &N Odd 0. 08 Chamfer 4x 0.6 x 0.6 max OPTIONAL Th er mal Ba se D2 2 C D2 C Bottom View w/Type A ID Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 RADIUS N N-1 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 ND & NE 8 D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS813N252AKI-04 REVISION A MAY 24, 2011 21 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number 813N252AKI-04LF 813N252AKI-04LFT Marking ICS252AI04L ICS252AI04L Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS813N252AKI-04 REVISION A MAY 24, 2011 22 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet Revision History Sheet Rev Table Page 4C 4D 7 7 A 12 A 6 Description of Change Date Differential DC Characteristics Table - redefined VCMR min. to standard levels as the crosspoint. Changed from 0.5V min. to VEE. Updated NOTEs. LVPECL DC Characteristics Table - corrected VOH/VOL Parameter verbage from Current to Voltage and corrected units to “V”. Updated “Wiring the Differenti Input to Accept Single-ended Levels”. 3/18/10 Supply Voltage, VCC. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03. 5/24/11 ICS813N252AKI-04 REVISION A MAY 24, 2011 23 ©2011 Integrated Device Technology, Inc. VCXO JITTER ATTENUATOR & FEMTOCLOCK® NG MULTIPLIER ICS813N252I-04 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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