FemtoClock® Crystal-to-LVDS Frequency
Synthesizer
844003I-04
Datasheet
General Description
Features
The 844003I-04 is a 3 differential output LVDS Synthesizer designed
to generate Ethernet reference clock frequencies. Using a
19.44MHz, 20MHz or 25MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the settings of four
frequency select pins (DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz,
622.08MHz, 312.5MHz, 250MHz, 156.25MHz, 125MHz and
100MHz. The 844003I-04 has two output banks, Bank A with one
differential LVDS output pair and Bank B with two differential LVDS
output pairs.
•
Three LVDS outputs on two banks, Bank A with one LVDS pair
and Bank B with 2 LVDS output pairs
•
Using a 19.44MHz, 20MHz, or 25MHz crystal, the two output
banks can be independently set for 625MHz, 622.08MHz,
312.5MHz, 250MHz, 156.25MHz, 125MHz or 100MHz
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
•
•
VCO range: 490MHz to 680MHz
•
•
•
•
Full 3.3V output supply mode
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
844003I-04 uses IDT’s 3RD generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The 844003I-04 is
packaged in a 32-pin VFQFN package.
RMS phase jitter at 125MHz (1.875MHz – 20MHz):
0.50ps (typical)
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement part use 8T49N241
nc
VDDO_A
VDDA
VDD
nc
nc
REF_CLK
VDD
Pin Assignment
32 31 30 29 28 27 26 25
VCO_SEL
REF_CLK
5
MR
6
GND
7
nc
8
GND
21
QB0
20
nQB0
19
QB1
18
nQB1
17
VDDO_B
9
Pullup
Pulldown:Pullup
Pullup
10 11 12 13 14 15 16
OEA
4
VCO_SEL
22
5mm x 5mm x 0.925mm
package body
K Package
Top View
OEB
XTAL_SEL
nQA0
GND
3
QA0
23
FB_DIV
XTAL_OUT
24
844003I-04
32 Lead VFQFN
DIV_SELB0
2
DIV_SELB1
DIV_SELA[1:0]
XTAL_IN
DIV_SELA1
OEA
1
DIV_SELA0
Block Diagram
GND
QA0
Pulldown
0
XTAL_IN
OSC
1
0
Phase
Detector
VCO
490-680MHz
00
01
10
11
÷2
÷4 (default)
÷5
÷8
00
01
10
11
÷1
÷2 (default)
÷3
÷4
nQA0
1
XTAL_OUT
XTAL_SEL
QB0
Pullup
FB_DIV
0 = ÷25 (default)
1 = ÷32
FB_DIV
DIV_SELB[1:0]
MR
OEB
Pulldown
nQB0
QB1
nQB1
Pulldown:Pullup
Pulldown
Pullup
©2016 Integrated Device Technology, Inc.
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Revision C, November 10, 2016
844003I-04 Datasheet
Table 1. Pin Descriptions
Number
Name
1, 7, 13, 22
GND
Power
2,
3
XTAL_IN
XTAL_OUT
Input
4
XTAL_SEL
Input
5
VCO_SEL
Type
Input
6
MR
Input
8, 26, 29, 30
nc
Unused
9
DIV_SELA1
Input
Description
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
Pullup
Crystal select pin. Selects between the single-ended REF_CLK or crystal interface.
Has an internal pullup resistor so the crystal interface is selected by default.
LVCMOS/LVTTL interface levels.
Pullup
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset,
(except for ÷1 state, when the device is configured as a buffer), causing the true
outputs QXx to go low and the inverted outputs nQXx to go high. When logic LOW,
the internal dividers and the outputs are enabled. MR has an internal pulldown
resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
No connect.
Pulldown
Division select pin for Bank A. Default = LOW. LVCMOS/LVTTL interface levels.
10
DIV_SELA0
Input
Pullup
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
11
DIV_SELB1
Input
Pulldown
Division select pin for Bank B. Default = LOW. LVCMOS/LVTTL interface levels.
12
DIV_SELB0
Input
Pullup
Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
14
FB_DIV
Input
Pulldown
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels.
15
16
OEB
OEA
Input
Input
Pullup
Output enable Bank B. Active High output enable. When logic HIGH, the output
pair on Bank B is enabled. When logic LOW, the output pair is in a highimpedance state. Has an internal pullup resistor so the default power-up state of
the outputs is enabled. LVCMOS/LVTTL interface levels.
Pullup
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair on Bank A is enabled. When logic LOW, the output pair is in a highimpedance state. Has an internal pullup resistor so the default power-up state of
the outputs is enabled. LVCMOS/LVTTL interface levels.
17
VDDO_B
Power
Output power supply pin for Bank B outputs.
18, 19
nQB1, QB1
Output
Differential Bank B output pair. LVDS interface levels.
20, 21
nQB0, QB0
Output
Differential Bank B output pair. LVDS interface levels.
23, 24
nQA0, QA0
Output
Differential Bank A output pair. LVDS interface levels.
25
VDDO_A
Power
Output supply pin for Bank A outputs.
27, 31
VDD
Power
Core supply pins.
28
VDDA
Power
Analog supply pin.
32
REF_CLK
Input
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to low
state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL
interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
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844003I-04 Datasheet
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Function Tables
Table 3A. Output Bank A Configuration
Select Function Table
Inputs
Table 3B. Output Bank B Configuration
Select Function Table
Outputs
Inputs
Outputs
DIV_SELA1
DIV_SELA0
QA0, nQA0
DIV_SELB1
DIV_SELB0
QB[0:1], nQB[0:1]
0
0
÷2
0
0
÷1
0
1
÷4 (default)
0
1
÷2 (default)
1
0
÷5
1
0
÷3
1
1
÷8
1
1
÷4
Table 3C. OEA Select Function Table
Table 3D. OEB Select Function Table
Input
Outputs
Input
Outputs
OEA
QA0, nQA0
OEB
QB[0:1], nQB[0:1]
0
High-Impedance
0
High-Impedance
1
Active (default)
1
Active (default)
Table 3E. Feedback Divider Configuration
Select Function Table
Input
FB_DIV
Feedback Divide
0
÷25 (default)
1
÷32
©2016 Integrated Device Technology, Inc.
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844003I-04 Datasheet
Table 3F. Bank A Frequency Table
Inputs
DIV_SELA0
Feedback
Divider
Bank A
Output Divider
M/N
Multiplication
Factor
QA0, nQA0
Output Frequency
(MHz)
0
0
25
2
12.5
312.5
0
0
0
25
2
12.5
250
25
0
0
1
25
4
6.25
156.25
24
0
0
1
25
4
6.25
150
20
0
0
1
25
4
6.25
125
25
0
1
0
25
5
5
125
25
0
1
1
25
8
3.125
78.125
24
0
1
1
25
8
3.125
75
20
0
1
1
25
8
3.125
62.5
19.44
1
0
0
32
2
16
311.04
15.625
1
0
0
32
2
16
250
19.44
1
0
1
32
4
8
155.52
18.75
1
0
1
32
4
8
150
15.625
1
0
1
32
4
8
125
15.625
1
1
0
32
5
6.4
100
19.44
1
1
1
32
8
4
77.76
18.75
1
1
1
32
8
4
75
15.625
1
1
1
32
8
4
62.5
Crystal Frequency
(MHz)
FB_DIV
DIV_SELA1
25
0
20
©2016 Integrated Device Technology, Inc.
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844003I-04 Datasheet
Table 3G. Bank B Frequency Table
Inputs
DIV_SELB0
Feedback
Divider
Bank B
Output Divider
M/N
Multiplication
Factor
QBx/ nQBx
Output Frequency
(MHz)
0
0
25
1
25
625
0
0
1
25
2
12.5
312.5
20
0
0
1
25
2
12.5
250
22.5
0
1
0
25
3
8.333
187.5
25
0
1
1
25
4
6.25
156.25
24
0
1
1
25
4
6.25
150
20
0
1
1
25
4
6.25
125
19.44
1
0
0
32
1
32
622.08
19.44
1
0
1
32
2
16
311.04
15.625
1
0
1
32
2
16
250
18.75
1
1
0
32
3
10.667
200
19.44
1
1
1
32
4
8
155.52
18.75
1
1
1
32
4
8
150
15.625
1
1
1
32
4
8
125
Crystal Frequency
(MHz)
FB_DIV
DIV_SELB1
25
0
25
©2016 Integrated Device Technology, Inc.
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Revision C, November 10, 2016
844003I-04 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
37C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 10%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
2.97
3.3
3.63
V
Analog Supply Voltage
VDD – 0.20
3.3
VDD
V
VDDO_A, VDDO_B
Output Supply Voltage
2.97
3.3
3.63
V
IDD
Power Supply Current
140
mA
IDDA
Analog Supply Current
20
mA
IDDO_A + IDDO_B
Output Supply Current
70
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 10%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
REF_CLK, MR, FB_DIV,
DIV_SELA1, DIV_SELB1
VDD = VIN = 3.63V
150
µA
OEA, OEB,
VCO_SEL, XTAL_SEL,
DIV_SELB0, DIV_SELA0
VDD = VIN = 3.63V
5
µA
REF_CLK, MR, FB_DIV,
DIV_SELA1, DIV_SELB1
VDD = 3.465V, VIN = 0V
OEA, OEB,
VCO_SEL, XTAL_SEL,
DIV_SELB0, DIV_SELA0
©2016 Integrated Device Technology, Inc.
6
-5
µA
-150
µA
Revision C, November 10, 2016
844003I-04 Datasheet
Table 4C. LVDS DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 10%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
300
400
500
mV
50
mV
1.55
V
50
mV
1.25
1.35
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
27.2
MHz
21.25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Mode of Oscillation
Typical
Fundamental
FB_DIV = ÷25
19.6
FB_DIV = ÷32
15.313
26.5625
Frequency
NOTE: Characterized using an 18pF parallel resonant crystal.
©2016 Integrated Device Technology, Inc.
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Revision C, November 10, 2016
844003I-04 Datasheet
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
fOUT
tsk(b)
Parameter
Output Frequency
tjit(Ø)
Minimum
Output Divider = ÷1
490
Typical
Output Skew
Maximum
Units
680
MHz
Output Divider = ÷2
245
340
MHz
Output Divider = ÷3
163.33
226.67
MHz
Output Divider = ÷4
122.5
170
MHz
Output Divider = ÷5
98
136
MHz
Output Divider = ÷8
61.25
85
MHz
25
ps
Outputs @ Same Frequency
50
ps
NOTE 2, 3, 4
QB 1, Outputs @ Different Frequencies
250
ps
NOTE 2, 3, 5
QB = 1, Outputs @ Different Frequencies
Bank Skew; NOTE 1
NOTE 2, 3
tsk(o)
Test Conditions
RMS Phase Jitter, Random;
NOTE 6
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
525
ps
625MHz, (1.875MHz - 20MHz)
0.34
ps
312.5MHz, (1.875MHz - 20MHz)
0.34
ps
250MHz, (1.875MHz - 20MHz)
0.42
ps
125MHz, (1.875MHz - 20MHz)
0.50
ps
100MHz, (1.875MHz - 20MHz)
0.41
ps
20% to 80%
150
550
ps
Output Divider ÷1
48
52
%
Output Divider = ÷1
44
56
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Characterized with DIV_SELA[1:0] = 11 and DIV_SELB[1:0] = 11.
NOTE 5: Characterized with DIV_SELA[1:0] = 00 and DIV_SELB[1:0] = 00.
NOTE 6: Please refer to the Phase Noise Plots.
©2016 Integrated Device Technology, Inc.
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Revision C, November 10, 2016
844003I-04 Datasheet
Typical Phase Noise at 100MHz
10Gb Ethernet Filter
Raw Phase Noise Data
Noise Power dBc
Hz
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 625MHz
10Gb Ethernet Filter
Noise Power dBc
Hz
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.34ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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Revision C, November 10, 2016
844003I-04 Datasheet
Parameter Measurement Information
3.3V ±5%
Noise Power
Phase Noise Plot
VDD,
VDDO_A,
VDDO_B VDDA
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V LVDS Output Load AC Test Circuit
RMS Phase Jitter
nQx
nQB0
Qx
QB0
nQy
nQB1
Qy
QB1
tsk(b)
Output Skew
Bank Skew
nQA0,
nQB[0:1]
nQA0,
nQB[0:1]
80%
80%
QA0,
QB[0:1]
VOD
QA0,
QB[0:1]
20%
20%
tR
tF
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc.
Output Duty Cycle/Pulse Width/Period
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Revision C, November 10, 2016
844003I-04 Datasheet
Parameter Measurement Information, continued
Differential Output Voltage Setup
Offset Voltage Setup
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844003I-04 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA, VDDO_A and VDDO_B should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Crystal Input Interface
The 844003I-04 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using an 18pF parallel resonant crystal and were chosen
to minimize the ppm error.
XTAL_IN
C1
27pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
Figure 2. Crystal Input Interface
©2016 Integrated Device Technology, Inc.
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844003I-04 Datasheet
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
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844003I-04 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, we recommend that there
is no trace attached.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1k
resistor can be tied from the REF_CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. Standard termination
for LVDS type output structure requires both a 100 parallel resistor
at the receiver and a 100 differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the amplitude and common mode
input range of the input receivers should be verified for compatibility
with the output.
+
LVDS Driver
LVDS
Receiver
100Ω
–
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
©2016 Integrated Device Technology, Inc.
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844003I-04 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc.
14
Revision C, November 10, 2016
844003I-04 Datasheet
Schematic Example
Figure 6 shows an example of an 844003I-04 application schematic.
In this example, the device is operated at VDD = VDDO _A = VDDO_B
= 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1
and C2 = 27pF are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. Two examples of LVDS for receiver
without built-in termination are shown in this schematic.
VDD
R1
VDDA
Zo = 50 Ohm
10
C6
QA0
C7
10uF
VDD
0.01u
+
VDD
R2
100
Zo = 50 Ohm
Q1
R3
C3
.1uf
C4
0.1uF
Zo = 50
nQA0
-
VDDO_A
33
REF_CLK
Driv er_LVCMOS
32
31
30
29
28
27
26
25
X1
1
2
3
4
5
6
7
8
F
p
8
1
25MHz
C2
27pF
XTAL_SEL
VCO_SEL
MR
GND
XTAL_IN
XTAL_OUT
XTAL_SEL
VCO_SEL
MR
GND
nc
Logic Control Input Examples
VDD
RU1
1K
Set Logic
Input to
'0'
VDD
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
VDDO_A = VDDO_B=3.3V
QA0
nQA0
GND
QB0
nQB0
QB1
nQB1
VDDO_B
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
24
23
22
21
20
19
18
17
Zo = 50 Ohm
QB1
VDDO_B
R4
50
+
0.1uF
C8
9
10
11
12
13
14
15
16
Set Logic
Input to
'1'
VDD=3.3V
D IV_SELA1
D IV_SELA0
D IV_SELB1
D IV_SELB0
GN D
F B_D IV
OEB
OEA
C1
27pF
0.1uF
C5
R EF _C LK
VD D
nc
nc
VD D A
VD D
nc
VD D O_A
U1
OEA
OEB
Zo = 50 Ohm
C9
0.1uF
R5
50
-
nQB1
Alternate
LVDS
Termination
RD2
1K
Figure 6. ICS870931I-01 Schematic Layout Example
©2016 Integrated Device Technology, Inc.
15
Revision C, November 10, 2016
844003I-04 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 844003I-04.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 844003I-04 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (140mA + 20mA) = 580.80mW
•
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.63V * 70mA = 254.1mW
Total Power_MAX = 580.80mW + 254.1mW = 834.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.835W * 37°C/W = 115.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
37.0°C/W
32.4°C/W
29°C/W
16
Revision C, November 10, 2016
844003I-04 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meter per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29°C/W
Transistor Count
The transistor count for 844003I-04 is: 4058
©2016 Integrated Device Technology, Inc.
17
Revision C, November 10, 2016
844003I-04 Datasheet
32 Lead VFQFN Package Outline and Package Dimensions
©2016 Integrated Device Technology, Inc.
18
Revision C, November 10, 2016
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
844003AKI-04LF
ICS403AI04L
“Lead-Free” 32 Lead VFQFN
Tray
-40C to 85C
844003AKI-04LFT
ICS403AI04L
“Lead-Free” 32 Lead VFQFN
Tape & Reel
-40C to 85C
Revision History Sheet
Rev
Table
A
T4A
T6
B
B
T10
C
Page
Description of Change
Date
15
Added Layout Schematic.
6/10/09
6
6
8
12
13
16
18
Absolute Maximum Ratings - updated Input Ratings.
Power Supply DC Characteristics Table - changed IDDO from 55mA max to 70mA max.
AC Characteristics Table - corrected NOTES.
Updated Overdriving the XTAL Interface application note.
Updated LVDS Driver Termination application note.
Updated Power Considerations to coincide with IDDO spec change.
Updated Package Drawing.
5/2/11
1
Product Discontinuation Notice - Last time buy expires November 2, 2016.
PDN# CQ-15-05.
11/5/15
19
Obsolete datasheet per PDN# CQ-15-05.
Ordering Information table - deleted Tape & Reel count and table note.
Updated datasheet header/footer.
11/10/16
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