Octal T1/E1/J1 Long Haul /
Short Haul Transceiver
IDT82P2288
Version 8
JANUARY 10, 2011
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775
Printed in U.S.A.
© 2011 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................................... 3
LIST OF TABLES .................................................................................................................................................................... 7
LIST OF FIGURES ................................................................................................................................................................... 9
FEATURES ............................................................................................................................................................................ 11
APPLICATIONS ..................................................................................................................................................................... 11
BLOCK DIAGRAM ................................................................................................................................................................ 12
1 PIN ASSIGNMENT .......................................................................................................................................................... 13
2 PIN DESCRIPTION ......................................................................................................................................................... 14
3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 22
3.1
3.2
T1 / E1 / J1 MODE SELECTION ..................................................................................................................................................................
RECEIVER IMPEDANCE MATCHING .........................................................................................................................................................
3.2.1 Line Monitor ....................................................................................................................................................................................
3.3 ADAPTIVE EQUALIZER ..............................................................................................................................................................................
3.4 DATA SLICER ..............................................................................................................................................................................................
3.5 CLOCK AND DATA RECOVERY ................................................................................................................................................................
3.6 RECEIVE JITTER ATTENUATOR ...............................................................................................................................................................
3.7 DECODER ....................................................................................................................................................................................................
3.7.1 Line Code Rule ...............................................................................................................................................................................
3.7.1.1 T1 / J1 Mode ....................................................................................................................................................................
3.7.1.2 E1 Mode ...........................................................................................................................................................................
3.7.2 Decode Error Detection .................................................................................................................................................................
3.7.2.1 T1 / J1 Mode ....................................................................................................................................................................
3.7.2.2 E1 Mode ...........................................................................................................................................................................
3.7.3 LOS Detection ................................................................................................................................................................................
3.8 FRAME PROCESSOR .................................................................................................................................................................................
3.8.1 T1/J1 Mode ......................................................................................................................................................................................
3.8.1.1 Synchronization Searching ...............................................................................................................................................
3.8.1.2 Error Event And Out Of Synchronization Detection ..........................................................................................................
3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) .....................................................................................................
3.8.1.4 Interrupt Summary ............................................................................................................................................................
3.8.2 E1 Mode ..........................................................................................................................................................................................
3.8.2.1 Synchronization Searching ...............................................................................................................................................
3.8.2.2 Error Event And Out Of Synchronization Detection ..........................................................................................................
3.8.2.3 Overhead Extraction .........................................................................................................................................................
3.8.2.4 V5.2 Link ..........................................................................................................................................................................
3.8.2.5 Interrupt Summary ............................................................................................................................................................
3.9 PERFORMANCE MONITOR ........................................................................................................................................................................
3.9.1 T1/J1 Mode ......................................................................................................................................................................................
3.9.2 E1 Mode ..........................................................................................................................................................................................
3.10 ALARM DETECTOR ....................................................................................................................................................................................
3.10.1 T1/J1 Mode ......................................................................................................................................................................................
3.10.2 E1 Mode ..........................................................................................................................................................................................
3.11 HDLC RECEIVER .........................................................................................................................................................................................
3.11.1 HDLC Channel Configuration ........................................................................................................................................................
3.11.2 HDLC Mode .....................................................................................................................................................................................
3.11.2.1 HDLC Mode ......................................................................................................................................................................
Table of Contents
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IDT82P2288
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
BIT-ORIENTED MESSAGE RECEIVER (T1/J1 ONLY) ..............................................................................................................................
INBAND LOOPBACK CODE DETECTOR (T1/J1 ONLY) ...........................................................................................................................
ELASTIC STORE BUFFER ..........................................................................................................................................................................
RECEIVE CAS/RBS BUFFER .....................................................................................................................................................................
3.15.1 T1/J1 Mode ......................................................................................................................................................................................
3.15.2 E1 Mode ..........................................................................................................................................................................................
RECEIVE PAYLOAD CONTROL .................................................................................................................................................................
RECEIVE SYSTEM INTERFACE .................................................................................................................................................................
3.17.1 T1/J1 Mode ......................................................................................................................................................................................
3.17.1.1 Receive Clock Master Mode ............................................................................................................................................
3.17.1.2 Receive Clock Slave Mode ..............................................................................................................................................
3.17.1.3 Receive Multiplexed Mode ...............................................................................................................................................
3.17.1.4 Offset ................................................................................................................................................................................
3.17.1.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) ..................................................................................
3.17.2 E1 Mode ..........................................................................................................................................................................................
3.17.2.1 Receive Clock Master Mode ............................................................................................................................................
3.17.2.2 Receive Clock Slave Mode ..............................................................................................................................................
3.17.2.3 Receive Multiplexed Mode ...............................................................................................................................................
3.17.2.4 Offset ................................................................................................................................................................................
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) ..................................................................................
TRANSMIT SYSTEM INTERFACE ..............................................................................................................................................................
3.18.1 T1/J1 Mode ......................................................................................................................................................................................
3.18.1.1 Transmit Clock Master Mode ............................................................................................................................................
3.18.1.2 Transmit Clock Slave Mode .............................................................................................................................................
3.18.1.3 Transmit Multiplexed Mode ..............................................................................................................................................
3.18.1.4 Offset ................................................................................................................................................................................
3.18.2 E1 Mode ..........................................................................................................................................................................................
3.18.2.1 Transmit Clock Master Mode ............................................................................................................................................
3.18.2.2 Transmit Clock Slave Mode .............................................................................................................................................
3.18.2.3 Transmit Multiplexed Mode ..............................................................................................................................................
3.18.2.4 Offset ................................................................................................................................................................................
TRANSMIT PAYLOAD CONTROL ..............................................................................................................................................................
FRAME GENERATOR .................................................................................................................................................................................
3.20.1 Generation ......................................................................................................................................................................................
3.20.1.1 T1 / J1 Mode ....................................................................................................................................................................
3.20.1.2 E1 Mode ...........................................................................................................................................................................
3.20.2 HDLC Transmitter ..........................................................................................................................................................................
3.20.2.1 HDLC Channel Configuration ...........................................................................................................................................
3.20.2.2 HDLC Mode ......................................................................................................................................................................
3.20.2.3 Interrupt Summary ............................................................................................................................................................
3.20.2.4 Reset ................................................................................................................................................................................
3.20.3 Automatic Performance Report Message (T1/J1 Only) ..............................................................................................................
3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only) ..........................................................................................................................
3.20.5 Inband Loopback Code Generator (T1/J1 Only) ..........................................................................................................................
3.20.6 All ‘Zero’s & All ‘One’s ...................................................................................................................................................................
3.20.7 Change Of Frame Alignment .........................................................................................................................................................
TRANSMIT BUFFER ....................................................................................................................................................................................
ENCODER ....................................................................................................................................................................................................
3.22.1 Line Code Rule ...............................................................................................................................................................................
3.22.1.1 T1/J1 Mode ......................................................................................................................................................................
3.22.1.2 E1 Mode ...........................................................................................................................................................................
3.22.2 BPV Error Insertion ........................................................................................................................................................................
3.22.3 All ‘One’s Insertion ........................................................................................................................................................................
TRANSMIT JITTER ATTENUATOR ............................................................................................................................................................
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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.24 WAVEFORM SHAPER / LINE BUILD OUT ...............................................................................................................................................
3.24.1 Preset Waveform Template .........................................................................................................................................................
3.24.1.1 T1/J1 Mode ....................................................................................................................................................................
3.24.1.2 E1 Mode .........................................................................................................................................................................
3.24.2 Line Build Out (LBO) (T1 Only) ...................................................................................................................................................
3.24.3 User-Programmable Arbitrary Waveform ..................................................................................................................................
3.25 LINE DRIVER .............................................................................................................................................................................................
3.26 TRANSMITTER IMPEDANCE MATCHING ...............................................................................................................................................
3.27 TESTING AND DIAGNOSTIC FACILITIES ...............................................................................................................................................
3.27.1 PRBS Generator / Detector .........................................................................................................................................................
3.27.1.1 Pattern Generator ...........................................................................................................................................................
3.27.1.2 Pattern Detector .............................................................................................................................................................
3.27.2 Loopback ......................................................................................................................................................................................
3.27.2.1 System Loopback ...........................................................................................................................................................
3.27.2.2 Payload Loopback ..........................................................................................................................................................
3.27.2.3 Local Digital Loopback 1 ................................................................................................................................................
3.27.2.4 Remote Loopback ..........................................................................................................................................................
3.27.2.5 Local Digital Loopback 2 ................................................................................................................................................
3.27.2.6 Analog Loopback ............................................................................................................................................................
3.27.3 G.772 Non-Intrusive Monitoring ..................................................................................................................................................
3.28 INTERRUPT SUMMARY ............................................................................................................................................................................
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113
4.1
4.2
4.3
4.4
POWER-ON SEQUENCE ...........................................................................................................................................................................
RESET ........................................................................................................................................................................................................
RECEIVE / TRANSMIT PATH POWER DOWN .........................................................................................................................................
MICROPROCESSOR INTERFACE ...........................................................................................................................................................
4.4.1 SPI Mode .......................................................................................................................................................................................
4.4.2 Parallel Microprocessor Interface ..............................................................................................................................................
INDIRECT REGISTER ACCESS SCHEME ...............................................................................................................................................
4.5.1 Indirect Register Read Access ...................................................................................................................................................
4.5.2 Indirect Register Write Access ...................................................................................................................................................
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115
116
116
117
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117
REGISTER MAP .........................................................................................................................................................................................
5.1.1 T1/J1 Mode ....................................................................................................................................................................................
5.1.1.1 Direct Register ................................................................................................................................................................
5.1.1.2 Indirect Register .............................................................................................................................................................
5.1.2 E1 Mode ........................................................................................................................................................................................
5.1.2.1 Direct Register ................................................................................................................................................................
5.1.2.2 Indirect Register .............................................................................................................................................................
REGISTER DESCRIPTION ........................................................................................................................................................................
5.2.1 T1/J1 Mode ....................................................................................................................................................................................
5.2.1.1 Direct Register ................................................................................................................................................................
5.2.1.2 Indirect Register .............................................................................................................................................................
5.2.2 E1 Mode ........................................................................................................................................................................................
5.2.2.1 Direct Register ................................................................................................................................................................
5.2.2.2 Indirect Register .............................................................................................................................................................
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118
125
126
126
132
134
135
135
228
236
236
329
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) ..................................................................................................................
JTAG DATA REGISTER ............................................................................................................................................................................
6.2.1 Device Identification Register (IDR) ...........................................................................................................................................
6.2.2 Bypass Register (BYP) ................................................................................................................................................................
6.2.3 Boundary Scan Register (BSR) ...................................................................................................................................................
TEST ACCESS PORT CONTROLLER ......................................................................................................................................................
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340
340
340
340
343
4 OPERATION .................................................................................................................................................................. 115
4.5
5 PROGRAMMING INFORMATION ................................................................................................................................. 118
5.1
5.2
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................................................... 339
6.1
6.2
6.3
Table of Contents
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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 346
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................
RECOMMENDED OPERATING CONDITIONS .........................................................................................................................................
D.C. CHARACTERISTICS .........................................................................................................................................................................
DIGITAL I/O TIMING CHARACTERISTICS ...............................................................................................................................................
CLOCK FREQUENCY REQUIREMENT ....................................................................................................................................................
T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ...................................................................................................................
E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................................................................
T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................
E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................
JITTER TOLERANCE ................................................................................................................................................................................
7.10.1 T1/J1 Mode ....................................................................................................................................................................................
7.10.2 E1 Mode ........................................................................................................................................................................................
7.11 JITTER TRANSFER ...................................................................................................................................................................................
7.11.1 T1/J1 Mode ....................................................................................................................................................................................
7.11.2 E1 Mode ........................................................................................................................................................................................
7.12 MICROPROCESSOR TIMING SPECIFICATION .......................................................................................................................................
7.12.1 Motorola Non-Multiplexed Mode .................................................................................................................................................
7.12.1.1 Read Cycle Specification ...............................................................................................................................................
7.12.1.2 Write Cycle Specification ................................................................................................................................................
7.12.2 Intel Non-Multiplexed Mode .........................................................................................................................................................
7.12.2.1 Read Cycle Specification ...............................................................................................................................................
7.12.2.2 Write Cycle Specification ................................................................................................................................................
7.12.3 SPI Mode .......................................................................................................................................................................................
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361
ORDERING INFORMATION ................................................................................................................................................ 362
DOCUMENT HISTORY ........................................................................................................................................................ 362
Table of Contents
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Operating Mode Selection ...........................................................................................................................................................................
Related Bit / Register In Chapter 3.1 ...........................................................................................................................................................
Impedance Matching Value For The Receiver .............................................................................................................................................
Related Bit / Register In Chapter 3.2 ...........................................................................................................................................................
Related Bit / Register In Chapter 3.3 & Chapter 3.4 ....................................................................................................................................
Criteria Of Speed Adjustment Start ..............................................................................................................................................................
Related Bit / Register In Chapter 3.6 ...........................................................................................................................................................
Excessive Zero Error Definition ...................................................................................................................................................................
LOS Condition In T1/J1 Mode ......................................................................................................................................................................
LOS Condition In E1 Mode ..........................................................................................................................................................................
Related Bit / Register In Chapter 3.7 ...........................................................................................................................................................
The Structure of SF .....................................................................................................................................................................................
The Structure of ESF ...................................................................................................................................................................................
The Structure of T1 DM ...............................................................................................................................................................................
The Structure of SLC-96 ..............................................................................................................................................................................
Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................
Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................
The Structure Of TS0 In CRC Multi-Frame ..................................................................................................................................................
FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................
Interrupt Source In E1 Frame Processor .....................................................................................................................................................
Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................
Monitored Events In T1/J1 Mode .................................................................................................................................................................
Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................
Monitored Events In E1 Mode .....................................................................................................................................................................
Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................
RED Alarm, Yellow Alarm & Blue Alarm Criteria .........................................................................................................................................
Related Bit / Register In Chapter 3.10.1 ......................................................................................................................................................
Related Bit / Register In Chapter 3.10.2 ......................................................................................................................................................
Related Bit / Register In Chapter 3.11.1 ......................................................................................................................................................
Interrupt Summarize In HDLC Mode ...........................................................................................................................................................
Related Bit / Register In Chapter 3.11.2 ......................................................................................................................................................
Related Bit / Register In Chapter 3.12 .........................................................................................................................................................
Related Bit / Register In Chapter 3.13 .........................................................................................................................................................
Related Bit / Register In Chapter 3.14 .........................................................................................................................................................
Related Bit / Register In Chapter 3.15 .........................................................................................................................................................
A-Law Digital Milliwatt Pattern .....................................................................................................................................................................
µ-Law Digital Milliwatt Pattern .....................................................................................................................................................................
Related Bit / Register In Chapter 3.16 .........................................................................................................................................................
Operating Modes Selection In T1/J1 Receive Path .....................................................................................................................................
Operating Modes Selection In E1 Receive Path ..........................................................................................................................................
Related Bit / Register In Chapter 3.17 .........................................................................................................................................................
Operating Modes Selection In T1/J1 Transmit Path ....................................................................................................................................
Operating Modes Selection In E1 Transmit Path .........................................................................................................................................
Related Bit / Register In Chapter 3.18 .........................................................................................................................................................
Related Bit / Register In Chapter 3.19 .........................................................................................................................................................
Related Bit / Register In Chapter 3.20.1.1 ...................................................................................................................................................
E1 Frame Generation ..................................................................................................................................................................................
Control Over E Bits ......................................................................................................................................................................................
List of Tables
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OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Interrupt Summary In E1 Mode .................................................................................................................................................................... 93
Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 93
Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 95
Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 .................................................................................................................... 95
APRM Message Format .............................................................................................................................................................................. 96
APRM Interpretation .................................................................................................................................................................................... 97
Related Bit / Register In Chapter 3.20.3 ...................................................................................................................................................... 97
Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5 .......................................................................................................................... 97
Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 & Chapter 3.21 ................................................................................................... 98
Related Bit / Register In Chapter 3.22 ......................................................................................................................................................... 99
Related Bit / Register In Chapter 3.23 ....................................................................................................................................................... 100
PULS[3:0] Setting In T1/J1 Mode .............................................................................................................................................................. 101
LBO PULS[3:0] Setting In T1 Mode ........................................................................................................................................................... 101
Transmit Waveform Value For E1 75 W .................................................................................................................................................... 102
Transmit Waveform Value For E1 120 W .................................................................................................................................................. 103
Transmit Waveform Value For T1 0~133 ft ............................................................................................................................................... 103
Transmit Waveform Value For T1 133~266 ft ........................................................................................................................................... 104
Transmit Waveform Value For T1 266~399 ft ........................................................................................................................................... 104
Transmit Waveform Value For T1 399~533 ft ........................................................................................................................................... 105
Transmit Waveform Value For T1 533~655 ft ........................................................................................................................................... 105
Transmit Waveform Value For J1 0~655ft ................................................................................................................................................. 106
Transmit Waveform Value For DS1 0 dB LBO .......................................................................................................................................... 106
Transmit Waveform Value For DS1 -7.5 dB LBO ...................................................................................................................................... 107
Transmit Waveform Value For DS1 -15.0 dB LBO .................................................................................................................................... 107
Transmit Waveform Value For DS1 -22.5 dB LBO .................................................................................................................................... 108
Related Bit / Register In Chapter 3.24 ....................................................................................................................................................... 108
Impedance Matching Value For The Transmitter ...................................................................................................................................... 109
Related Bit / Register In Chapter 3.25 & Chapter 3.26 .............................................................................................................................. 109
Related Bit / Register In Chapter 3.27.1 .................................................................................................................................................... 110
Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 ........................................................................................................................ 113
Related Bit / Register In Chapter 3.28 ....................................................................................................................................................... 114
Parallel Microprocessor Interface .............................................................................................................................................................. 116
Related Bit / Register In Chapter 4 ............................................................................................................................................................ 117
IR Code ...................................................................................................................................................................................................... 340
IDR ............................................................................................................................................................................................................. 340
Boundary Scan (BS) Sequence ................................................................................................................................................................. 340
TAP Controller State Description ............................................................................................................................................................... 343
List of Tables
8
JANUARY 10, 2011
List of Figures
Figure 1. 256-Pin CABGA and PBGA (Top View) ....................................................................................................................................................... 13
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 24
Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 25
Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 25
Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 26
Figure 6. Transmit Path Monitoring (COAX) ............................................................................................................................................................... 26
Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 27
Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 30
Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 30
Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 30
Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 43
Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 44
Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 46
Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 61
Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 62
Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 66
Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 66
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 72
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 73
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 73
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 74
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 75
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 75
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 76
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 81
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 82
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 82
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 83
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 84
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 84
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 85
Figure 32. DSX-1 Waveform Template ...................................................................................................................................................................... 100
Figure 33. T1/J1 Pulse Template Measurement Circuit ............................................................................................................................................ 100
Figure 34. E1 Waveform Template ............................................................................................................................................................................ 101
Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................. 101
Figure 36. G.772 Non-Intrusive Monitor .................................................................................................................................................................... 112
Figure 37. Hardware Reset When Powered-Up ........................................................................................................................................................ 115
Figure 38. Hardware Reset In Normal Operation ...................................................................................................................................................... 115
Figure 39. Read Operation In SPI Mode ................................................................................................................................................................... 116
Figure 40. Write Operation In SPI Mode .................................................................................................................................................................... 116
Figure 41. JTAG Architecture .................................................................................................................................................................................... 339
Figure 42. JTAG State Diagram ................................................................................................................................................................................ 345
Figure 43. I/O Timing in Mode ................................................................................................................................................................................... 348
Figure 44. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 352
Figure 45. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 353
Figure 46. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 355
Figure 47. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 356
Figure 48. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 357
List of Figures
9
JANUARY 10, 2011
IDT82P2288
Figure 49.
Figure 50.
Figure 51.
Figure 52.
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Motorola Non-Multiplexed Mode Write Cycle ...........................................................................................................................................
Intel Non-Multiplexed Mode Read Cycle ..................................................................................................................................................
Intel Non-Multiplexed Mode Write Cycle ..................................................................................................................................................
SPI Timing Diagram .................................................................................................................................................................................
List of Figures
10
358
359
360
361
JANUARY 10, 2011
Octal T1/E1/J1 Long Haul /
IDT82P2288
Short Haul Transceiver
FEATURES
• Three HDLC controllers per link with separate 128-byte transmit
and receive FIFOs per controller
• Programmable bit insertion and bit inversion on per channel/
timeslot basis
• Provides Bit Oriented Message (BOM) generation and detection
• Provides Automatic Performance Report Message (APRM) generation
• Detects and generates alarms (AIS, RAI)
• Provides performance monitor to count Bipolar Violation error,
Excess Zero error, CRC error, framing bit error, far end CRC error,
out of frame and change of framing alignment position
• Supports System Loopback, Payload Loopback, Digital Loopback
and Inband Loopback
• Detects and generates selectable PRBS and QRSS
LINE INTERFACE
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Each link can be configured as T1, E1 or J1
Supports T1/E1/J1 long haul/short haul line interface
HPS for 1+1 protection without external relays
Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024
Hz
Selectable internal line termination impedance: 100 Ω (for T1), 75
Ω / 120 Ω (for E1) and 110 Ω (for J1)
Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encoding/decoding
Provides T1/E1/J1 short haul pulse templates, long haul LBO (per
ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and userprogrammable arbitrary pulse template
Supports G.772 non-intrusive monitoring
Supports T1.102 line monitor
Transmit line short-circuit detection and protection
Separate Transmit and Receive Jitter Attenuators (2 per link)
Indicates the interval between the write pointer and the read
pointer of the FIFO in JA
Loss of signal indication with programmable thresholds according
to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1)
Supports Analog Loopback, Digital Loopback and Remote Loopback
Each receiver and transmitter can be individually powered down
CONTROL INTERFACE
• Supports Serial Peripheral Interface (SPI) microprocessor and parallel Intel/Motorola non-multiplexed microprocessor interface
• Global hardware and software reset
• Two general purpose I/O pins
• Per link power down
GENERAL
• Flexible reference clock (N x 1.544 MHz or N x 2.048 MHz)
(0
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