8305AGLF-TEJ

Low Skew, 1-to-4 Multiplexed Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer ICS8305 DATA SHEET General Description Features The ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. • • • Four LVCMOS / LVTTL outputs, 7 output impedance • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL • • • • • Maximum output frequency: 350MHz • • 0°C to 70°C ambient operating temperature Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well defined performance and repeatability. Block Diagram Selectable differential or LVCMOS / LVTTL clock inputs CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output skew: 35ps (maximum) Part-to-part skew: 700ps (maximum) Additive phase jitter, RMS: 0.04ps (typical) Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V Available in lead-free (RoHS 6) package Pin Assignment CLK_EN Pullup GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK D Q LE LVCMOS_CLK Pulldown 00 CLK Pulldown nCLK Pullup/ 11 Q0 Pulldown CLK_SEL Pullup Q1 Q2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q0 VDDO Q1 GND Q2 VDDO Q3 GND ICS8305 16-Lead TSSOP 4.4mm x 3.0mm x 0.925mm package body G Package Q3 OE Pullup Top View ICS8305AG REVISION C MAY 30, 2014 1 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 1. Pin Descriptions Number Name 1, 9, 13 GND Power Type Description 2 OE Input 3 VDD Power 4 CLK_EN Input Pullup 5 CLK Input Pulldown Non-inverting differential clock input. 6 nCLK Input Pullup/ Pulldown Inverting differential clock input. VDD/2 default when left floating. 7 CLK_SEL Input Pullup 8 LVCMOS_CLK Input Pulldown 10, 12, 14, 16 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. 7 output impedance. LVCMOS/LVTTL interface levels. 11, 15 VDDO Power Output supply pins. Power supply ground Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS/LVTTL interface levels. Power supply pin. Synchronizing clock enable. When LOW, the output clocks are disabled. When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k CPD Power Dissipation Capacitance (per output) 11 pF ROUT Output Impedance 7  ICS8305AG REVISION C MAY 30, 2014 Test Conditions 2 Minimum Typical Maximum Units ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Function Tables Table 3. Control Input Function Table Inputs Outputs OE CLK_EN CLK_SEL Selected Source Q0:Q3 1 0 0 LVCMOS_CLK Disabled; Low 1 0 1 CLK/nCLK Disabled; Low 1 1 0 LVCMOS_CLK Enabled 1 1 1 CLK/nCLK Enabled 0 X X Hi-Z After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. Enabled Disabled nCLK CLK, LVCMOS_CLK CLK_EN Q0:Q3 Figure 1. CLK_EN Timing Diagram ICS8305AG REVISION C MAY 30, 2014 3 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5% or 1.8V±0.5V or 1.5V±5%, TA = 0°C to 70°C Symbol Parameter VDD Positive Supply Voltage VDDO Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.65 1.8 1.95 V 1.425 1.5 1.575 V Output Supply Voltage IDD Power Supply Current 21 mA IDDO Output Supply Current 5 mA ICS8305AG REVISION C MAY 30, 2014 4 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 4B. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL IIH IIL VOH VOL Input Low Voltage Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units CLK_EN, CLK_SEL, OE 2 VDD + 0.3 V LVCMOS_CLK 2 VDD + 0.3 V CLK_EN, CLK_SEL, OE -0.3 0.8 V LVCMOS_CLK -0.3 1.3 V CLK_EN, CLK_SEL, OE VDD = VIN = 3.465V 5 µA LVCMOS_CLK VDD = VIN = 3.465V 150 µA CLK_EN, CLK_SEL, OE VDD = 3.465V, VIN = 0V -150 µA LVCMOS_CLK VDD = 3.465V, VIN = 0V -5 µA VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1.8 V VDDO = 1.8V ± 0.15V 1.5 V VDDO = 1.5V ± 5% VDDO - 0.3 V Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 IOZL Output Hi-Z Current Low IOZH Output Hi-Z Current High VDDO = 3.3V ± 5% 0.5 V VDDO = 2.5V ± 5% 0.5 V VDDO = 1.8V ± 0.15V 0.4 V VDDO = 1.5V ± 5% 0.35 V -5 µA 5 µA NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 4C. Differential DC Characteristics, TA = -40°C to 85°C Symbol Parameter Test Conditions Input High Current nCLK IIH IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units VDD = VIN = 3.465V 150 µA CLK VDD = VIN = 3.465V 150 µA nCLK VDD = 3.465V, VIN = 0V -150 µA CLK VDD = 3.465V, VIN = 0V -5 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. ICS8305AG REVISION C MAY 30, 2014 5 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol Test Conditions fMAX Output Frequency tpLH Propagation Delay, Low to High tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Part-to-Part Skew; NOTE 3, 6 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 tR / tF Output Rise/Fall Time; NOTE 4 odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B Minimum Typical 1.75 Measured on the Rising Edge Maximum Units 350 MHz 2.75 ns 35 ps 700 ps 0.04 ps 20% to 80% 100 700 ps Ref = CLK/nCLK 45 55 % Ref = LVCMOS_CLK, ƒ  300MHz 45 55 % 5 ns 5 ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  350MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency Test Conditions tpLH Propagation Delay, Low to High tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Part-to-Part Skew; NOTE 3, 6 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 tR / tF Output Rise/Fall Time; NOTE 4 odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B Minimum Typical 1.8 Measured on the Rising Edge Maximum Units 350 MHz 2.9 ns 35 ps 800 ps 0.04 ps 20% to 80% 100 700 ps Ref = CLK/nCLK 44 56 % Ref = LVCMOS_CLK, ƒ  300MHz 44 56 % 5 ns 5 ns For NOTES, see Table 5A above. ICS8305AG REVISION C MAY 30, 2014 6 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency Test Conditions LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B tpLH Propagation Delay, Low to High tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Part-to-Part Skew; NOTE 3, 6 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 tR / tF Output Rise/Fall Time; NOTE 4 odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 Minimum Typical 1.95 Measured on the Rising Edge Maximum Units 350 MHz 3.65 ns 35 ps 900 ps 0.04 ps 20% to 80% 100 700 ps Ref = CLK/nCLK 44 56 % Ref = LVCMOS_CLK, ƒ  300MHz 44 56 % 5 ns 5 ns NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  350MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V ± 5%, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency Test Conditions LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B tpLH Propagation Delay, Low to High tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Part-to-Part Skew; NOTE 3, 6 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 tR / tF Output Rise/Fall Time; NOTE 4 odc Output Duty Cycle tEN Output Enable Time; NOTE 4 tDIS Output Disable Time; NOTE 4 Minimum Typical 2 Measured on the Rising Edge Maximum Units 350 MHz 4 ns 35 ps 1 ns 0.04 ps 20% to 80% 200 900 ps ƒ  166MHz 45 55 % ƒ > 166MHz 42 58 % 5 ns 5 ns For NOTES, see Table 5C above. ICS8305AG REVISION C MAY 30, 2014 7 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 0 -10 Additive Phase Jitter at 155.52MHz = 0.04ps (typical) -20 -30 -40 -50 -60 SSB Phase Noise dBc/Hz -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This ICS8305AG REVISION C MAY 30, 2014 is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 8 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDO SCOPE VDD VDDO Qx LVCMOS Qx GND CL ≤ 25pF* *For tR/tF measurement only -1.65V±5% -1.25V±5% 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.55V±5% 2.4V±0.09V 0.75V±5% 0.9V±0.075V SCOPE VDD VDDO SCOPE VDD VDDO Qx GND Qx GND -0.9V±0.075V -0.9V±0.75V 3.3V Core/1.5V LVCMOS Output Load AC Test Circuit 3.3V Core/1.8V LVCMOS Output Load AC Test Circuit VDD VCCO 2 Qx nCLK V PP Cross Points V VCCO 2 CMR CLK Qy tsk(b) GND Output Skew Differential Input Level ICS8305AG REVISION C MAY 30, 2014 9 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued V Part 1 DDO DDO Qx 2 Q0:Q3 V t PW 2 t PERIOD Part 2 V DDO Qy 2 tsk(pp) odc = t PW x 100% t PERIOD Part-to-Part Skew Output Duty Cycle/Pulse Width/Period LVCMOS_CLK 80% VDDO 2 nCLK 80% CLK Clock Outputs 20% 20% tR tF VDDO 2 Q0:Q3 ➤ Output Rise/Fall Time ICS8305AG REVISION C MAY 30, 2014 tPD ➤ Propagation Delay 10 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS_CLK Input LVCMOS Outputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the LVCMOS_CLK input to ground. All unused LVCMOS outputs can be left floating. There should be no trace attached. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8305AG REVISION C MAY 30, 2014 11 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 3.3V 3.3V 2.5V R3 120Ω *R3 R4 120Ω Zo = 60Ω CLK CLK Zo = 60Ω nCLK nCLK HCSL *R4 Differential Input SSTL R1 120Ω Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8305AG REVISION C MAY 30, 2014 R2 120Ω Differential Input Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 12 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Schematic Example This application note provides general design guide using ICS8305 LVCMOS buffer. Figure 4 shows a schematic example of the ICS8305 LVCMOS clock buffer. In this example, the input is driven by an LVCMOS driver. CLK_EN is set at logic low to select LVCMOS_CLK input. VDD Zo = 50 VDD R1 43 R4 1K R5 1K U1 1 2 3 4 5 6 7 8 VDD Zo = 50 Ro ~ 7 Ohm R3 GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK Q0 VDDO Q1 GND Q2 VDDO Q3 GND 16 15 14 13 12 11 10 9 LVCMOS Receiv er Zo = 50 R2 43 43 3,.3V LVCMOS R6 1K ICS8305 (U1,3) (U1,11) (U1,15) C1 C2 C3 0.1u 0.1u 0.1u VDD VDD=3.3V LVCMOS Receiv er Figure 4. ICS8305 LVCMOS Clock Output Buffer Schematic Example ICS8305AG REVISION C MAY 30, 2014 13 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Reliability Information Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS8305: 459 Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 7. Package Dimensions for 16 Lead TSSOP Symbol N A A1 A2 b c D E E1 e L  aaa All Dimensions in Millimeters Minimum Maximum 16 1.20 0.5 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.10 6.40 Basic 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS8305AG REVISION C MAY 30, 2014 14 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Ordering Information Table 8. Ordering Information Part/Order Number 8305AGLF 8305AGLFT Marking 8305AGLF 8305AGLF ICS8305AG REVISION C MAY 30, 2014 Package “Lead-Free” 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP 15 Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Revision History Sheet Rev A B B C C C Table Page T8 14 T5A - T5C 5&6 7 T1 T4A T4B T5D C 1/20/04 Added Additive Phase Jitter to AC Characteristics Tables. Added Additive Phase Jitter Section. 2/26/04 2 Pin Description Table - corrected CLK_EN description. 12/6/04 1 Features Section - added 1.5V output to Supply Mode bullet and added Lead-Free bullet. Power Supply DC Characteristics Table - added VDDO 1.5V. LVCMOS DC Characteristics Table - added VOH/VOL 1.5V. Added 3.3V/1.5V AC Characteristics Table. Added 3.3V/1.5V Output Load AC Test Circuit Drawing. Added Recommendations for Unused Input and Output Pins. Added Lead-Free part number. 11/17/05 Ordering Information Table - added lead-free marking. Corrected non-lead free marking from ICS8305AG to 8305AG. 2/22/08 Updated to current datasheet format Deleted HiPerClockS references. Added Note: Electrical parameters are guaranteed ... to Notes Updated the ‘Wiring the Differential Input to Accept Single Ended Levels’ section Deleted: ICS from part numbers; quantity from shipping; LF Note; disclaimer. 9/17/12 Features Section - removed leaded part reference Ordering Information - removed leaded parts. PDN# CQ-13-02 Updated Technical Support contact email address 5/30/14 T8 T8 15 8 T8 Date Ordering Information table - corrected Part/Order Number typo from ICS88305AGT to ICS8305AGT. 4 4 7 10 11 16 T5A-T5D Description of Change 1, 12 6, 7 11 15 1 15 17 ICS8305AG REVISION C MAY 30, 2014 16 ©2014 Integrated Device Technology, Inc. ICS8305 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Clocks@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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