840004AG-11LFT

840004-11 FemtoClock™ Crystal-to-LVCMOS/LVTTL Frequency Synthesizer Datasheet General Description Features The 840004-11 is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet reference clock frequencies and is a member of the family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, 125MHz and 62.5MHz can be generated based on one frequency select pin (F_SEL). The 840004-11 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The 840004-11 is packaged in a small 20-pin TSSOP package. • Four single-ended LVCMOS/LVTTL outputs 17 typical output impedance • • • • • Crystal oscillator interface Input frequency range: 22.4MHz to 28MHz Output frequency range: 56MHz - 140MHz VCO range: 560MHz - 700MHz RMS phase jitter at 125MHz (1.875MHz – 20MHz): 0.70ps (typical) Phase Noise: Offset Noise Power 100Hz -95.5 dBc/Hz 1kHz -123.6 dBc/Hz 10kHz -132.8 dBc/Hz 100kHz -133.4 dBc/Hz • • • Full 3.3V output supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Frequency Select Function Table for Ethernet Frequencies Inputs F_SEL M Divider Value N Divider Value Output Frequency (MHz), 25MHz Reference 0 25 10 62.5 1 25 5 125 (default) Block Diagram Pin Assignment OE Pullup F_SEL F_SEL nc nc nc Pullup F_SEL 25MHz XTAL_IN OSC Phase Detector VCO XTAL_OUT N 0 ÷10 1 ÷5 (default) Q0 OE nc nc Q1 VDDA nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT Q2 ICS840004-01 M = ÷25 (fixed) Q3 ©2015 Integrated Device Technology, Inc 1 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View December 7, 2015 840004-11 Datasheet Table 1. Pin Descriptions Number Name 1 F_SEL Input Type Description 2, 3, 4, 6, 7, 9, 20 nc Unused 5 OE Input 8 VDDA Power Analog supply pin. 10 VDD Power Core supply pin. 11, 12 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 13, 19 GND Power Power supply ground. 14, 15, 17, 18 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. 17 typical output impedance. LVCMOS/ LVTTL interface levels. 16 VDDO Power Output supply pin. Pullup Frequency select pin. LVCMOS/LVTTL interface levels. No connect. Pullup Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP ROUT Test Conditions Minimum Typical Maximum Units 4 pF 8 pF Input Pullup Resistor 51 k Output Impedance 17  ©2015 Integrated Device Technology, Inc VDD = VDDO = 3.465V 2 December 7, 2015 840004-11 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 10 mA Maximum Units No Load Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OE, F_SEL VDD = VIN = 3.465V 5 µA IIL Input Low Current OE, F_SEL VDD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V ± 5% 2.6 V VOL Output Low Voltage; NOTE 1 VDDO = 3.3V ± 5% 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. Table 4. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant crystal. ©2015 Integrated Device Technology, Inc 3 December 7, 2015 840004-11 Datasheet AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fout Output Frequency tsk(o) Output Skew: NOTE 1, 2 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum F_SEL = 1 F_SEL = 0 Typical Maximum Units 112 140 MHz 56 70 MHz 80 ps 125MHz, Integration Range: 1.875MHz – 20MHz 0.70 ps 62.5MHz, Integration Range: 1.875MHz – 20MHz 0.54 ps 20% to 80% 200 700 ps F_SEL = 0 48 52 % F_SEL = 1 46 54 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. ©2015 Integrated Device Technology, Inc 4 December 7, 2015 840004-11 Datasheet ➝ Typical Phase Noise at 62.5MHz 1Gb Ethernet Filter Noise Power dBc Hz 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.54ps (typical) ➝ ➝ Raw Phase Noise Data Phase Noise Result by adding a 1Gb Ethernet filter to raw data Offset Frequency (Hz) ©2015 Integrated Device Technology, Inc 5 December 7, 2015 840004-11 Datasheet ➝ Typical Phase Noise at 125MHz 1Gb Ethernet Filter Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.70ps (typical) ➝ ➝ Raw Phase Noise Data Phase Noise Result by adding a 1Gb Ethernet filter to raw data Offset Frequency (Hz) ©2015 Integrated Device Technology, Inc 6 December 7, 2015 840004-11 Datasheet Parameter Measurement Information 1.65V±5% Phase Noise Plot Noise Power 1.65V±5% SCOPE VDD, VDDO VDDA Qx Phase Noise Mask GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V±5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit RMS Phase Jitter V DDO Qx 2 V DDO Qy Q0:Q3 2 tsk(o) Output Skew 80% 80% tR tF 20% 20% Output Rise/Fall Time V DDO 2 Q0:Q3 t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle Pulse Width/Period ©2015 Integrated Device Technology, Inc 7 December 7, 2015 840004-11 Datasheet Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVCMOS Outputs All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 840004-11 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. ©2015 Integrated Device Technology, Inc 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering 8 December 7, 2015 840004-11 Datasheet Crystal Input Interface The 840004-11 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22pF X1 18pF Parallel Crystal XTAL_OUT C2 22pF Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals VCC the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface ©2015 Integrated Device Technology, Inc 9 December 7, 2015 840004-11 Datasheet Reliability Information Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 840004-11: 1795 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 7. Package Dimensions for 20 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ©2015 Integrated Device Technology, Inc 10 December 7, 2015 840004-11 Datasheet Ordering Information Table 8. Ordering Information Part/Order Number 840004AG-11LF 840004AG-11LFT Marking ICS40004A11L ICS40004A11L ©2015 Integrated Device Technology, Inc Package 20 Lead “Lead-Free” TSSOP 20 Lead “Lead-Free” TSSOP 11 Shipping Packaging Tube Tape & Reel Temperature 0C to 70C 0C to 70C December 7, 2015 840004-11 Datasheet Revision History Sheet Rev A A Table Page Description of Change T5 T8 4 9 11 AC Characteristics Tables - added Thermal note. Added LVCMOS to XTAL Interface section. Ordering Information Table - deleted “ICS” prefix from Part/Order Number column. Converted datasheet format. 9/16/09 T8 11 Ordering Information - removed leaded devices, quantity for tape and reel and the LF note below the table. Updated datasheet format. 12/7/15 ©2015 Integrated Device Technology, Inc Date 12 December 7, 2015 840004-11 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2015 Integrated Device Technology, Inc. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.