840021AGILF

FemtoClock™ Crystal-to-LVCMOS/LVTTL Clock Generator ICS840021I DATA SHEET General Description Features The ICS840021I is a Gigabit Ethernet Clock Generator. The ICS840021I uses a 25MHz crystal to HiPerClockS™ synthesize 125MHz. The ICS840021I has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The ICS840021I is packaged in a small 8-pin TSSOP and 16-pin VFQFN, making it ideal for use in systems with limited board space. • • One LVCMOS/LVTTL output, 15Ω output impedance • • • Output frequency: 125MHz • • RMS phase noise at 125MHz (typical) ICS Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal VCO range: 560MHz to 680MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.48ps (typical) 3.3V Phase noise: Noise Power Offset 100Hz ................-97.8 dBc/Hz 1kHz ..............-124.6 dBc/Hz 10kHz ..............-132.5 dBc/Hz 100Hz ..............-131.1 dBc/Hz • Pin Assignments VDDA OE XTAL_OUT XTAL_IN 1 2 3 4 • • VDD Q0 GND RESERVED 8 7 6 5 Voltage Supply Modes: VDD/VDDA = 3.3V VDD/VDDA = 2.5V -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages ICS840021I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View Block Diagram 2 XTAL_OUT 11 VDD XTAL_IN 3 Phase Detector VCO ÷5 Q0 ÷25 (fixed) 10 GND nc 4 25MHz OSC 16 15 14 13 OE 1 12 Q0 XTAL_OUT Pullup XTAL_IN VDD nc VDDA nc OE 6 7 8 nc nc nc nc 9 GND 5 ICS840021I 16-Lead VFQFN 3.0mm x 3.0mm x 0.925mm package body K Package Top View ICS840021AGI REVISION C JANUARY 27, 2010 1 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Table 1. Pin Descriptions Name Type Description VDDA Power Analog supply pin. OE Input XTAL_OUT, XTAL_IN Input nc Unused RESERVED Reserved GND Power Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 15Ω output impedance. VDD Power Core supply pin. Pullup Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to high-impedance state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Reserved pin. Power supply ground. NOTE: Pullup refers to internal input resistors. See Table 1, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP ROUT Minimum Typical Maximum Units 4 pF VDD = 3.465V 7 pF VDD = 2.625V 7 pF Input Pullup Resistor 51 kΩ Output Impedance 15 Ω Function Table Table 3. Control Function Table Control Input Output OE Q0 0 High-Impedance 1 Active ICS840021AGI REVISION C JANUARY 27, 2010 2 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 8 TSSOP 16 VFQFN 101.7°C/W (0 mps) 74.9°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 65 mA IDDA Analog Supply Current 10 mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 60 mA IDDA Analog Supply Current 10 mA ICS840021AGI REVISION C JANUARY 27, 2010 Test Conditions 3 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% OR 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VDD = 3.3V Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current OE VDD = VIN = 3.465V OR 2.625V 5 µA IIL Input Low Current OE VDD =3.465V OR 2.625V, VIN = 0V -150 µA V Output High Voltage; NOTE 1 VDD = 3.465V 2.6 VOH VDD = 2.625V 1.8 V VOL Output High Voltage; NOTE 1 VDD = 3.465V OR 2.625V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit" diagrams. Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW ICS840021AGI REVISION C JANUARY 27, 2010 4 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR AC Electrical Characteristics Table 6A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Integration Range: 1.875MHz – 20MHz 20% to 80% Typical Maximum Units 125 MHz 0.48 ps 200 500 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. Table 6B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Integration Range: 1.875MHz – 20MHz 20% to 80% Typical Maximum Units 125 MHz 0.50 ps 250 550 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. ICS840021AGI REVISION C JANUARY 27, 2010 5 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Typical Phase Noise at 125MHz (3.3V OR 2.5V) ← Gb Ethernet Filter ← Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz (3.3V) = 0.48ps (typical) 1.875MHz to 20MHz (2.5V) = 0.50ps (typical) Raw Phase Noise Data ← Phase Noise Result by adding a Gb Ethernet Filter to raw data Offset Frequency (Hz) ICS840021AGI REVISION C JANUARY 27, 2010 6 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Parameter Measurement Information 1.25V± 5% 1.65V± 5% SCOPE VDD, VDDA Qx LVCMOS SCOPE VDD, VDDA Qx LVCMOS GND GND -1.25V ± 5% -1.65V ± 5% 3.3V Output Load AC Test Circuit 2.5V Output Load AC Test Circuit V DD 2 Q0 80% t PW t PERIOD Q0 odc = 80% t PW 20% 20% tR tF x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time Noise Power Phase Noise Plot Phase Noise Mask f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter ICS840021AGI REVISION C JANUARY 27, 2010 7 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. ICS840021I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individ- ually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Crystal Input Interface The ICS840021I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 33p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. Crystal Input Interface ICS840021AGI REVISION C JANUARY 27, 2010 8 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface ICS840021AGI REVISION C JANUARY 27, 2010 9 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Application Schematic Figure 4A shows a schematic example of the ICS840021I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF VDD VDDA R2 10 C3 C4 10uF 0.1u U1 1 2 3 4 OE C2 33pF parallel resonant 25MHz crystal is used for generating 125MHz output frequency. The C1 = 22pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND Reserv ed 8 7 6 5 X1 Zo = 50 Ohm C5 0.1u ICS840021i C1 22pF R3 43 VDD Q LVCMOS VDD=3.3V Figure 4A. ICS840021I Schematic Example PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of ICS840021I P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. Table 7. Footprint Table Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2, R3 0603 NOTE: Table 7, lists component sizes shown in this layout example. Figure 4B. ICS840021I PC Board Layout Example ICS840021AGI REVISION C JANUARY 27, 2010 10 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Reliability Information Table 8A. θJA vs. Air Flow Table for a 8 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W 0 1 2.5 74.97°C/W 65.5°C/W 58.8°C/W Table 8B. θJA vs. Air Flow Table for a 16 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS840021I is: 1961 ICS840021AGI REVISION C JANUARY 27, 2010 11 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 9A. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS840021AGI REVISION C JANUARY 27, 2010 12 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Package Outline - K Suffix for 16 Lead VFQFN (Ref.) Seating Plane ND & NE Even (ND-1)x e (R ef.) A1 Index Area L A3 N Top View N e (Typ.) 2 If ND & NE 1 Anvil Singulation or Sawn Singulation are Even 2 E2 (NE -1)x e (Re f.) E2 2 b A (Ref.) D e D2 2 ND & NE Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C Thermal Base D2 C Bottom View w/Type A ID Bottom View w/Type B ID Bottom View w/Type C ID BB 4 CHAMFER 4 N N-1 There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) 2 1 2 1 CC 2 1 4 N N-1 DD 4 RADIUS 4 N N-1 AA 4 Table 9B. Package Dimensions JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS840021AGI REVISION C JANUARY 27, 2010 13 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 840021AGI 840021AGIT 840021AGILF 840021AGILFT 840021AKILF 840021AKILFT Marking 021AI 021AI 21AIL 21AIL 1AIL 1AIL Package 8 Lead TSSOP 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS840021AGI REVISION C JANUARY 27, 2010 14 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Revision History Sheet Rev Table Page A T10 11 Ordering Information Table - Added Lead-Free Marking. 7-30-07 9 Added LVCMOS to XTAL Interface section. Changed formatting throughout data sheet 1-20-09 T1 1 2 Pin Assignment - changed pin 5 from nc to Reserved. Pin Description Table - changed pin 5 from nc to Reserved. 5/4/09 T8B T9B 10 1 3 11 13 14 Add 16 VFQFN Pin Assignment. Absolute Maximum Ratings - added 16 VFQFN Package Thermal Impedance information. Added 16 VFQFN Air Flow Table. Added 16 VFQFN Package Drawing and Dimensions. Ordering Information Table - added 16 VFQFN ordering information. 6/25/09 Deleted “Proposed” label throughout the datasheet. 7/14/09 Feature Section corrected temperature bullet from 40°C to -40°C. Added new VFQFN bottom view package drawing. 1/27/10 A B C C C 1 13 Description of Change ICS840021AGI REVISION C JANUARY 27, 2010 Date 15 ©2010 Integrated Device Technology, Inc. ICS840021I Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.