840022AGLFT

PRELIMINARY ICS840022 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS840022 is a Gigabit Ether net Clock ICS Generator and a member of the HiPerClocks TM HiPerClockS™ family of high performance devices from IDT. The ICS840022 uses a 25MHz crystal to synthesize 125MHz or 62.5MHz. The ICS840022 has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The ICS840022 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One LVCMOS/LVTTL output, 7Ω output impedence • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal • Output frequencies: 125MHz or 62.5MHz (selectable) • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.55ps (typical) • RMS phase noise at 125MHz: Offset Noise Power 100Hz ............. -106.3 dBc/Hz 1kHz ............. -126.3 dBc/Hz 10kHz ............. -131.7 dBc/Hz 100kHz ............. -130.8 dBc/Hz • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages • Industrial temperature information available upon request FUNCTION TABLE Inputs FREQ_SEL Output Frequencies (with a 25MHz crystal) 0 125MHz 1 62.5MHz BLOCK DIAGRAM PIN ASSIGNMENT OE VDDA OE XTAL_OUT XTAL_IN FREQ_SEL XTAL_IN OSC XTAL_OUT Phase Detector VCO 0 ÷5 Q 560MHz-680MHz w/25MHz Ref. 1 ÷10 M = ÷25 (fixed) 1 2 3 4 8 7 6 5 VDD Q GND FREQ_SEL ICS840022 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 1 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Type 2 OE Input 5 XTAL_OUT, XTAL_IN FREQ_SEL Input 6 GND Power 7 Q Output 8 VDD Power 3, 4 Input Description Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. Pullup When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 7Ω output impedence. Core supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Minimum Typical Maximum Units 4 pF TBD pF Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 7 Ω VDD, VDDA = 3.465V TABLE 3. CONROL FUNCTION TABLE Control Inputs Output OE Q 0 Hi-Z 1 Active IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 2 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDA Analog Supply Voltage IDD Power Supply Current 45 IDDA Analog Supply Current 8 V mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current 5 µA 150 µA OE VDD = VIN = 3.465V VDD = VIN = 3.465V FREQ_SEL OE VDD = 3.465V, VIN = 0V FREQ_SEL VDD = 3.465V, VIN = 0V IIL Input Low Current VOH Output High Voltage; NOTE 1 -150 µA -5 µA 2.6 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 0.5 V Maximum Units TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Maximum Units TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol fOUT tjit(Ø) tR / tF Parameter Test Conditions Output Frequency RMS Phase Jitter; NOTE 1 Output Rise/Fall Time 125MHz, (Intergration Range: 1.875MHz - 20MHz) 62.5MHz, (Intergration Range: 1.875MHz - 20MHz) 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 3 Minimum Typical 125 MHz 62.5 MHz 0.55 ps 0.50 ps 350 ps 50 % ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY TYPICAL PHASE NOISE AT 62.5MHZ (3.3V) ➤ 0 -10 -20 Gb Ethernet Filter -30 -40 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.55ps -60 -70 -80 -90 -100 Raw Phase Noise Data -110 -120 ➤ NOISE POWER dBc Hz -50 -130 -140 -150 ➤ -160 -170 -180 -190 100 1k 10k Phase Noise Result by adding Gb Ethernet Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ (3.3V) 0 ➤ -10 -20 -30 Gb Ethernet Filter -50 125MHz -60 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.50ps -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -40 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 4 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.65V ± 5% Noise Power Phase Noise Plot SCOPE VDD, VDDA Qx Phase Noise Mask LVCMOS GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V ± 5% 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER 80% 80% tR tF Q t PW t odc = Clock Outputs PERIOD t PW 20% 20% x 100% t PERIOD LVCMOS OUTPUT RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 5 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840022 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT PINS LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 6 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS840022 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p FIGURE 2. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 7 TO XTAL INPUT INTERFACE ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY APPLICATION SCHEMATIC output frequency. The C1 = 22pF and C2pF = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Figure 4A shows a schematic example of the ICS840022. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz VDD VDDA R2 10 C3 10uF VDD C4 0.1u R1 U1 1K 1 2 3 4 OE C2 33pF VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND FREQ_SEL VDD Q 8 7 6 5 R3 33 Zo = 50 Ohm FRE_SEL X1 C5 0.1u ICS840022 C1 22pF LVCMOS VDD=3.3V FIGURE 4A. ICS840022 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of ICS840022 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 7. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R1, R2, R3 0603 NOTE: Table 7, lists component sizes shown in this layout example. FIGURE 4B. ICS840022 PC BOARD LAYOUT EXAMPLE IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 8 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W 9 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR PRELIMINARY 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 10 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840022AG 0022A 8 lead TSSOP tube 0°C to 70°C ICS840022AGT 0022A 8 lead TSSOP 2500 tape & reel 0°C to 70°C ICS840022AGLF 022AL 8 lead "Lead-Free" TSSOP tube 0°C to 70°C ICS840022AGLFT 022AL 8 lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 11 ICS840022AG REV. A JANUARY 26, 2007 ICS840022 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA