ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
General Description
Features
The ICS840271I is a PLL-based Frequency
Translator intended for use in telecommunication
HiPerClockS™
applications such as Synchronous Ethernet. The
internal PLL translates Ethernet clock frequencies
such as 125MHz (1Gb Ethernet), 156.25MHz
(10GbE XAUI) and 161.1328MHz (10Gb Ethernet) to an output
frequency of 25MHz. The PLL does not any require external
components. The input frequency is selectable by a 2-pin
interface. The ICS840271I is optimized for low cycle-to-cycle jitter
on the 25MHz output signal. The input of the device accepts
differential (LVPECL, LVDS, LVHSTL, SSTL, HCSL) or
single-ended (LVCMOS) signals. The extended temperature range
supports telecommunication and networking equipment
requirements. The ICS840271I uses a small RoHS 6, 8-pin
TSSOP package and is an effective solution for space-constrained
applications.
•
Clock frequency translator for Synchronous Ethernet
applications
•
One single-ended output (LVCMOS or LVTTL levels),
16Ω output impedance
•
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
•
Supports input clock frequencies of: 125MHz, 156.25MHz or
161.1328MHz
•
•
Generates a 25MHz output clock signal
•
Internal PLL is optimized for low cycle-to-cycle jitter at the
output
•
•
•
Full 3.3V or 2.5V supply voltage
ICS
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/LVTTL) input levels
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
VDDA
CLK
nCLK
SEL(1:0)
Predivider
SEL0
PLL
Feedback
divider
Output
divider
Q
25 MHz
Input Control Logic
00 = PLL Bypass
01 = 161.1328125 MHz
10 = 156.2500000 MHz
11 = 125.0000000 MHz
IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
1
CLK
nCLK
1
2
3
4
8
7
6
5
VDD
Q
GND
SEL1
ICS840271I
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS840271BGI REV. A APRIL 23, 2009
ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VDDA
Power
2
SEL0
Input
Pulldown
Selects the input reference frequency and the PLL bypass mode.
LVCMOS/LVTTL interface levels. See Table 3.
3
CLK
Input
Pulldown
Non-inverting differential clock input.
4
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
5
SEL1
Input
Pullup
6
GND
Power
Power supply ground.
7
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
8
VDD
Power
Core supply pin.
Analog supply pin.
Selects the input reference frequency and the PLL bypass mode.
LVCMOS/LVTTL interface levels. See Table 3.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
51
kΩ
VDD = 3.465V
16
Ω
VDD = 2.625V
19
Ω
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
Typical
Maximum
Units
Function Tables
Table 3. SEL[1:0] Function Table
Inputs
SEL1
SEL0
CLK, nCLK (MHz)
Mode
Output (MHz)
0
0
REF
PLL Bypass
REF/ 5
0
1
161.1328125
PLL Enabled
25
1 (default)
0 (default)
156.25
PLL Enabled
25
1
1
125
PLL Enabled
25
NOTE: REF = Input clock signal frequency
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVCMOS)
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
129.5°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
IDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.08
3.3
VDD
V
Power Supply Current
75
mA
Analog Supply Current
8
mA
Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
IDD
IDDA
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VDD – 0.08
2.5
VDD
V
Power Supply Current
72
mA
Analog Supply Current
8
mA
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Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
Test Conditions
Minimum
VDD = 3.3V
Typical
Maximum
Units
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
SEL1
VDD = VIN = 3.465V or 2.625V
5
µA
SEL0
VDD = VIN = 3.465V or 2.625V
150
µA
SEL1
VDD = 3.465V, VIN = 0V
-150
µA
SEL0
VDD = 3.465V, VIN = 0V
-5
µA
VDD = 3.465V, IOH = 12mA
2.6
V
VDD = 2.625V, IOH = 12mA
1.8
V
VDD = 3.465V or 2.625V, IOL = -12mA
0.5
V
Maximum
Units
150
µA
Table 4D. Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Test Conditions
CLK/nCLK
Minimum
VDD = VIN = 3.465V or 2.625V
Typical
CLK
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA
nCLK
VDD = 3.465V or 2.625V,
VIN = 0V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage;
NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(cc))
Cycle-to-Cycle Jitter
tLOCK
PLL Lock Time
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
25
Units
MHz
SEL0 ≠ SEL1
40
ps
SEL0 = SEL1 = 1
15
ps
SEL1 = 0, SEL0 = 1
1
s
SEL 1 = 1, SEL0 = X
50
ms
200
700
ps
47
53
%
20% to 80%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
Table 5B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(cc))
Cycle-to-Cycle Jitter
tLOCK
PLL Lock Time
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
25
Units
MHz
SEL0 ≠ SEL1
50
ps
SEL0 = SEL1 = 1
15
ps
SEL1 = 0, SEL0 = 1
1
s
SEL 1 = 1, SEL0 = X
50
ms
200
700
ps
47
53
%
20% to 80%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
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Parameter Measurement Information
1.25V±5%
1.65V±5%
1.25V±5%
1.65V±5%
SCOPE
VDD
VDDA
VDDA
Qx
LVCMOS
SCOPE
VDD
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
VDD
Q
nCLK
➤
Cross Points
PP
V
CMR
tcycle n
➤
V
➤
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
CLK
GND
Differential Input Level
Cycle-to-Cycle Jitter
V
DDO
2
Q
t PW
t
PERIOD
t PW
80%
tR
tF
20%
20%
Q
odc =
80%
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Output Rise/Fall Time
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Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS840271I provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that
an additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
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Schematic Example
Figure 4 shows an example of ICS840271I applications schematic.
In this example, the device is operated at VDD = 3.3V. The input is
driven by either a 3.3V LVPECL or LVDS driver. One example of
LVCMOS termination is shown in this schematic. The decoupling
capacitors should be located a close as possible to the power pin.
Logic Input Pin Examples
Set Logic
Input to
'1'
VDD
Set Logic
Input to
'0'
VDD
RU1
1K
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
VDD
R1
To Logic
Input
pins
RD2
1K
VDD
C1
0.01u
VDDA
10
C2
0.1u
U1
C3
10u
SEL0
1
2
3
4
VDDA
SEL0
CLK
nCLK
VDD
Q
GND
SEL1
VDD
R3
125
8
7
6
5
Q
R2
33
Zo = 50 Ohm
SEL1
LVCMOS
R4
125
CLK
Zo = 50
nCLK
Zo = 50
LVPECL Driv er
R5
84
R6
84
Figure 4. ICS840271I Schematic layout
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS840271I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS840271I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(75mA + 8mA) = 287.6mW
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 16Ω)] = 26.25mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 16Ω * (26.25mA)2 = 11mW per output
Total Power Dissipation
•
Total Power
= Power (core)MAX + Total Power (ROUT)
= 287.6mW + 11mW
= 298.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.299W *129.5°C/W = 123.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
0
1
2.5
129.5°C/W
125.5°C/W
123.5°C/W
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SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Reliability Information
Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
129.5°C/W
125.5°C/W
123.5°C/W
Transistor Count
The transistor count for ICS840271I is: 2732
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
8
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
3.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number
840271BGILF
840271BGILFT
Marking
71BIL
71BIL
Package
“Lead-Free” 8 Lead TSSOP
“Lead-Free” 8 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
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Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
netcom@idt.com
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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