8413S08BKILFT

8413S08 Clock Generator for Cavium Processors Data Sheet General Description Features The 8413S08 is a high performance PLL-based clock generator optimized for processor core, PCI/PCI-X/PCIe bus, SGMII and Gigabit Ethernet PHY clocks. The clock generator offers ultra-low jitter outputs that make it ideal to serve as a central clocking device for multiple clock destinations. The output frequencies are generated from a 25MHz parallel resonant crystal, or external differential input source. The industrial temperature range of the 8413S08 supports tele-communication, networking and storage requirements. • Eight selectable 100MHz or 125MHz clocks for PCI Express and sRIO, HCSL interface levels • • • One 156.25MHz SGMII clock, LVPECL interface levels • Crystal oscillator interface designed for 25MHz, parallel resonant crystal • Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, LVHSTL, HCSL input levels • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels • Output supply voltage modes: VDD / VDDO 3.3V/3.3V 3.3V/2.5V • • Full 3.3V output supply mode (HCSL) • • -40°C to 85°C ambient operating temperature Three LVCMOS/LVTTL outputs, 20 output impedance Selectable external crystal or differential (single-ended) input source PCI Express™(2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter compliant Available in lead-free (RoHS 6) package VDDO_B QD QC VDDO_CD OE_QREF0 OE_CD F_SELB F_SELA GND nQB QB VDDO_REF0 QREF0 GND Pin Assignment 56 55 54 53 52 51 50 49 48 47 46 45 44 43 VDD VDDA XTAL_IN 3 4 5 6 7 8 9 10 11 40 39 38 IREF VDDO_A nQA7 QA7 ICS8413S08I 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nPLL_SEL XTAL_OUT nXTAL_SEL GND VDD 41 ©2016 Integrated Device Technology, Inc. 1 37 36 35 34 33 32 31 30 29 nQA6 QA6 VDDO_A nQA5 QA5 nQA4 QA4 VDDO_A GND VDDO_A nQREF1 QREF2 nQREF2 QREF3 nQREF3 VDDO_REF 42 VDDO_A QA0 nQA0 QA1 nQA1 VDDO_A QA2 nQA2 QA3 nQA3 QREF1 1 2 CLK nCLK VDDO_REF October 3, 2016 8413S08 Data Sheet Block Diagram QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 0 = 100MHz 1 = 125MHz QA4 nQA4 Pulldown nPLL_SEL QA5 Pulldown nXTAL-SEL nQA5 QA6 nQA6 QA7 nQA7 XTAL_IN OSC 25MHz 0 XTAL_OUT FemtoClock PLL 2.5GHz Center Frequency CLK Pulldown nCLK PU/PD 0 Pulldown FSEL_B Pulldown nQB 1 1 50MHz QC 33.3 MHz QD OE_CD FSEL_A QB 0 = 156.25MHz 1 = 100MHz Clock Output OE_QREF0_ Control Logic Pullup Pullup QREF0 QREF1 nQREF1 QREF2 nQREF2 QREF3 nQREF3 ©2016 Integrated Device Technology, Inc. 2 October 3, 2016 8413S08 Data Sheet Table 1. Pin Descriptions Number Name 1, 8 VDDO_REF Power Type QREF[1:3], nQREF[1:3] (LVPECL) output supply pins. 3.3V or 2.5V supply. Description 2, 3 QREF1, nQREF1 Output Differential reference output pair. 3.3V or 2.5V LVPECL interface levels. 4, 5 QREF2, nQREF2 Output Differential reference output pair. 3.3V or 2.5V LVPECL interface levels. 6, 7 QREF3, nQREF3 Output Differential reference output pair. 3.3V or 2.5V LVPECL interface levels. 9, 42 VDD Power Core supply pins. 10 VDDA Power Analog supply pin. 11, 12 XTAL_IN, XTAL_OUT Input 13 nXTAL_SEL Input 14, 29, 46, 54 GND Power 15 nPLL_SEL Input Pulldown PLL bypass control pin. See Table 3C. LVCMOS/LVTTL interface levels. 16 CLK Input Pulldown Non-inverting differential clock input. 17 nCLK Input Pullup/ Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 18, 23, 28, 30, 35, 40 VDDO_A Power Bank A (HCSL) output supply pins. 3.3V supply. 19, 20 QA0, nQA0 Output Differential output pair. HCSL interface levels. 21, 22 QA1, nQA1 Output Differential output pair. HCSL interface levels. 24, 25 QA2, nQA2 Output Differential output pair. HCSL interface levels. 26, 27 QA3, nQA3 Output Differential output pair. HCSL interface levels. 31, 32 QA4, nQA4 Output Differential output pair. HCSL interface levels. 33, 34 QA5, nQA5 Output Differential output pair. HCSL interface levels. 36, 37 QA6, nQA6 Output Differential output pair. HCSL interface levels. 38, 39 QA7, nQA7 Output Differential output pair. HCSL interface levels. 41 IREF Input 43 VDDO_B Power Bank B (LVPECL) output supply pin. 3.3V or 2.5V supply. 44, 45 QB, nQB Output Differential output pair. 3.3V or 2.5V LVPECL interface levels. 47 F_SELA Input Pulldown Selects the QAx, nQAx output frequency. See Table 3A. LVCMOS/LVTTL interface levels. 48 F_SELB Input Pulldown Selects the QB output frequency. See Table 3B. LVCMOS/LVTTL interface levels. 49 OE_CD Input Pullup Active HIGH output enable for Bank C and Bank D outputs. See Table 3E. LVCMOS/LVTTL interface levels. 50 OE_QREF0 Input Pullup Active HIGH output enable for QREF0 output. See Table 3F. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown Input source control pin. See Table 3D. LVCMOS/LVTTL interface levels. Power supply ground. External fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode QAx, nQAx outputs. Pin Descriptions continues on next page. ©2016 Integrated Device Technology, Inc. 3 October 3, 2016 8413S08 Data Sheet Number Name Type Description 51 VDDO_CD Power Bank C and D (LVCMOS) output supply pin. 3.3V or 2.5V supply. 52 QC Output Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels. 53 QD Output Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels. 55 QREF0 Output Single-ended reference output. 3.3V or 2.5V LVCMOS/LVTTL interface levels. 56 VDDO_REF0 Power QREF0 (LVCMOS) output supply pin. 3.3V or 2.5V supply. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Test Conditions Power Dissipation Capacitance (per output) Minimum Typical Maximum Units 2 pF VDD, VDDO_A, VDDO_B, VDDO_CD, VDDO_QREF0, VDDO_QREF = 3.465V 4 pF VDD = 3.465V, VDDO_B, VDDO_CD, VDDO_QREF0 = 2.625V 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance QC, QD, QREF0 VDDO_CD, VDDO_QREF0 = 3.465V 20  QC, QD, QREF0 VDDO_CD, VDDO_QREF0 = 2.625V 25  ©2016 Integrated Device Technology, Inc. 4 October 3, 2016 8413S08 Data Sheet Function Tables Table 3A. QAx, nQAx Control Input Function Table Input Output Frequency FSEL_A QAx, nQAx[0:7] 0 (default) 100MHz 1 125MHz Table 3B. QB, nQB Control Input Function Table Input Output Frequency FSEL_B QB, nQB 0 (default) 156.25MHz 1 100MHz Table 3C. nPLL_SEL Control Input Function Table Input nPLL_SEL Operation 0 (default) PLL Mode 1 PLL Bypass Table 3D. nXTAL_SEL Control Input Function Table Input nXTAL_SEL Clock Source 0 (default) XTAL_IN, XTAL_OUT 1 CLK, nCLK Table 3E. OE_CD Control Input Function Table Input Outputs OE_CD QC, QD 0 High-Impedance 1(default) Enabled able 3F. OE_QREF0 Control Input Function Table Input Output OE_QREF0 QREF0 0 High-Impedance 1(default) Enabled ©2016 Integrated Device Technology, Inc. 5 October 3, 2016 8413S08 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_in Other Inputs -0.5V to VDD + 0.5V 0V to VDD -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to VDD + 0.5V Outputs, IO (HCSL) Continuos Current Surge Current 10mA 15mA Outputs, IO (LVPECL) Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 31.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.16 3.3 VDD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 84 mA IDDA Analog Supply Current 16 mA IDDO_X Output Supply Current 66 mA No Load, CLK selected NOTE: VDDO_X denotes VDDO_A, VDDO_B, VDDO_CD, VDDO_QREF0, VDDO_QREF. NOTE: IDDO_X denotes IDDO_A, IDDO_B, IDDO_CD, IDDO_QREF0, IDDO_QREF. Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.16 3.3 VDD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 84 mA IDDA Analog Supply Current 16 mA IDDO_X Output Supply Current 54 mA No Load, CLK selected NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_QREF0, VDDO_QREF. NOTE: IDDO_X denotes IDDO_B, IDDO_CD, IDDO_QREF0, IDDO_QREF. ©2016 Integrated Device Technology, Inc. 6 October 3, 2016 8413S08 Data Sheet Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2.2 VDD + 0.3 V -0.3 0.8 V FSEL_A, FSEL_B, nXTAL_SEL, nPLL_SEL VDD = VIN = 3.465V 150 µA OE_CD, OE_QREF0 VDD = VIN = 3.465V 10 uA FSEL_A, FSEL_B, nXTAL_SEL, nPLL_SEL VDD = 3.465V, VIN = 0V -10 µA OE_CD, OE_QREF0 VDD = 3.465V, VIN = 0V -150 uA VDDO_X = 3.465V 2.6 V VDDO_X = 2.625V 1.8 V VOH Output High Voltage; NOTE 1 VOL Output Low Voltage: NOTE 1 VDDO_X = 3.465V or 2.625V 0.5 V NOTE: VDDO_X denotes VDDO_CD, VDDO_QREF0. NOTE 1: Outputs terminated with 50 to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 4D. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD – 0.85 V Maximum Units CLK, nCLK Minimum Typical VDD = VIN = 3.465V Maximum Units 150 µA CLK VDD = 3.465V, VIN = 0V -10 µA nCLK VDD = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH. Table 4E. LVPECL DC Characteristics, VDD = VDDO_B = VDDO_REF = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VDDO_X – 1.4 VDDO_X – 0.9 V VOL Output Low Voltage; NOTE 1 VDDO_X – 2.0 VDDO_X – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VDDO_X – 2V. Table 4F. LVPECL DC Characteristics, VDD = 3.3V± 5%, VDDO_B = VDDO_REF = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VDDO_X – 1.4 VDDO_X – 0.9 V VDDO_X – 2.0 VDDO_X – 1.5 V 0.4 1.0 V NOTE 1: Outputs terminated with 50 to VDDO_X – 2V. ©2016 Integrated Device Technology, Inc. 7 October 3, 2016 8413S08 Data Sheet Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. AC Electrical Characteristics Table 6A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 11.51 17.45 86 ps Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 1.08 1.67 3.10 ps Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.06 0.11 3.0 ps Phase Jitter RMS; NOTE 3, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.26 0.38 0.8 ps Symbol Parameter tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4 tREFCLK_HF_R MS (PCIe Gen 2) tREFCLK_LF_R MS (PCIe Gen 2) tREFCLK_RMS (PCIe Gen 3) Test Conditions Minimum NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. ©2016 Integrated Device Technology, Inc. 8 October 3, 2016 8413S08 Data Sheet Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions tjit(cc) tjit(Ø) Output Frequency Cycle-to-Cycle Jitter; NOTE 2, 3 RMS Phase Jitter, (Random); NOTE 1 MHz 100 MHz QC 50 MHz QD 33.333 MHz QB, nQB 47 80 ps QC 155 200 ps QD 105 185 ps QREF0 25MHz (10kHz to 5MHz) 0.61 0.82 ps QREF[1:3], nQREF[1:3] 25MHz (10kHz to 5MHz) 0.51 0.70 ps 156.25MHz (12kHz to 20MHz) 0.58 0.72 ps 225 ps 110 QC, QD QREF0 20% to 80% QREF[1:3] nQREF[1:3] odc Output Duty Cycle Units 156.25 QB, nQB Output Rise/Fall Time Maximum FSEL_B = 1 QB, nQB tR / tF Typical FSEL_B = 0 QB, nQB fOUT Minimum 400 1400 ps 400 1400 ps 110 225 ps QB, nQB measured at crosspoint 48 52 % QC, QD measured at VDDO_CD/2 48 52 % QREF0 measured at VDDO_QREF0/2 45 55 % measured at crosspoint 45 55 % QREF[1:3], nQREF[1:3] NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_QREF and VDDO_QREF0. NOTE 1: Refer to the phase noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Jitter performance using XTAL inputs. ©2016 Integrated Device Technology, Inc. 9 October 3, 2016 8413S08 Data Sheet HCSL AC Electrical Characteristics Table 6C. HCSL AC Characteristics, VDD = 3.3V ± 5%, VDDO_A = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical fOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 54 80 ps tsk(o) Output Skew; NOTE 2, 3 30 100 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 4 100MHz (1.875MHz to 20MHz) 0.29 0.37 ps 100MHz (12kHz to 20MHz) 0.63 0.81 ps VRB Ring-Back Voltage Margin; NOTE 5, 6 -100 100 mV tSTABLE Time before VRB is allowed; NOTE 5, 6 500 VMAX Absolute Max Output Voltage; NOTE 7, 8 1150 mV VMIN Absolute Min Output Voltage; NOTE 7, 9 -300 VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 250 VCROSS Total Variation of VCROSS over All Edges; NOTE 7, 10, 12 tSLEW+ Rising Edge Rate; NOTE 5, 13 tSLEWodc FSEL_A = 0 100 FSEL_A = 1 125 Maximum Units MHz MHz ps mV 550 mV 140 mV 0.6 5.5 V/ns Falling Edge Rate; NOTE 5, 13 0.6 5.5 V/ns Output Duty Cycle; NOTE 6 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 4: Refer to the Phase Noise Plot. NOTE 5: Measurement taken from differential waveform. NOTE 6: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the Vrb ±100mV range. See Parameter Measurement Information Section. NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at the crossing point where the instantaneous voltage value of the rising edge of Q[Ax:Ex] equals the falling edge of nQ[Ax:Ex]. NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising Q[Ax:Ex] and falling nQ[Ax:Ex]. This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Q[Ax:Ex] minus nQ[Ax:Ex]). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. ©2016 Integrated Device Technology, Inc. 10 October 3, 2016 8413S08 Data Sheet Typical Phase Noise at 100MHz (HCSL Output) Noise Power dBc Hz 100MHz RMS Phase Jitter 1.875MHz to 20MHz = 0.29ps (typical) Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 11 October 3, 2016 8413S08 Data Sheet Typical Phase Noise at 156.25MHz (LVPECL Output) Noise Power dBc Hz 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.58ps (typical) Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 12 October 3, 2016 8413S08 Data Sheet Parameter Measurement Information 2.05V±5% 1.65V±5% 1.25V±5% 1.65V±5% VDD, VDDO_CD, VDDO_QREF0 2.05V±5% SCOPE SCOPE VDD VDDA VDDO_CD, VDDO_QREF0 Qx Qx VDDA GND GND -1.65V±5% - 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit -1.25V±5% 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 2V 2.8V±0.04V 2V 2V 2.8V±0.04V VDD VDDO_B, VDDO_REF Qx SCOPE VDD VDDO_B, VDDO_REF VDDA Qx SCOPE VDDA LVPECL nQx GND nQx GND -1.3V±0.165V -0.5V±0.125V 3.3V Core/3.3V LVPECL Output Load AC Test Circuit 3.3V Core/2.5V LVPECL Output Load AC Test Circuit 3.3V±5% 3.3V±5% 3.3V±5% 3.3V±5% VDD, VDDO_A VDD, VDDO_A VDDA QX VDDA VDDA nQX This load condition is used for IDD, tjit(cc), tjit(Ø) and tsk(o) measurements. 3.3V Core/3.3V HCSL Output Load AC Test Circuit ©2016 Integrated Device Technology, Inc. 3.3V Core/3.3V HCSL Output Load AC Test Circuit 13 October 3, 2016 8413S08 Data Sheet Parameter Measurement Information, continued VDD nCLK V V Cross Points PP CMR CLK GND Differential Input Level RMS Phase Jitter nQA, nQB V DDOX 2 DDOX 2 tcycle n ➤ QC, QD V V DDOX ➤ 2 tcycle n+1 QA, QB ➤ tcycle n ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles LVCMOS Cycle-to-Cycle Jitter nQB, nQREF[1:3] 80% tcycle n+1 Differential Cycle-to-Cycle Jitter QC, QD, QREF0 80% VSW I N G QB, QC, QD QREF0, QREF[1:3] 20% 20% tR tF LVCMOS/LVPECL Output Rise/Fall Time ©2016 Integrated Device Technology, Inc. LVCMOS Output Duty Cycle/Pulse Width 14 October 3, 2016 8413S08 Data Sheet Parameter Measurement Information, continued nQB, nQREF[1:3] QB, QREF[1:3] LVPECL Output Duty Cycle/Pulse Width Differential Measurement Points for Ringback Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing Differential Measurement Points for Duty Cycle/Period Differential Measurement Points for Rise/Fall Time Edge Rate ©2016 Integrated Device Technology, Inc. 15 October 3, 2016 8413S08 Data Sheet Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. The unused LVPECL output can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Crystal Inputs LVCMOS Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVCMOS output can be left floating. There should be no trace attached. Differential Outputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. ©2016 Integrated Device Technology, Inc. 16 October 3, 2016 8413S08 Data Sheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht  s  = H3  s    H1  s  – H2  s   The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y  s  = X  s   H3  s    H1  s  – H2  s   In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ©2016 Integrated Device Technology, Inc. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 17 October 3, 2016 8413S08 Data Sheet Wiring the Differential Input to Accept Single-Ended Levels line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission VCC VCC VCC VCC R3 100 Ro RS R1 1K Zo = 50 Ohm + Driver V1 Ro + Rs = Zo R4 100 Receiv er - C1 0.1uF R2 1K Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2016 Integrated Device Technology, Inc. 18 October 3, 2016 8413S08 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. Figure 2A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ©2016 Integrated Device Technology, Inc. 19 October 3, 2016 8413S08 Data Sheet Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ©2016 Integrated Device Technology, Inc. 20 October 3, 2016 8413S08 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Figure 4A. 3.3V LVPECL Output Termination ©2016 Integrated Device Technology, Inc. Figure 4B. 3.3V LVPECL Output Termination 21 October 3, 2016 8413S08 Data Sheet Termination for 2.5V LVPECL Outputs level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VDD – 2V. For VDDO = 2.5V, the VDDO – 2V is very close to ground 2.5V VDDO = 2.5V 2.5V 2.5V VDDO = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V VDDO = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 5C. 2.5V LVPECL Driver Termination Example ©2016 Integrated Device Technology, Inc. 22 October 3, 2016 8413S08 Data Sheet Recommended Termination Figure 6A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω differential. 0.5" Max Rs 1-14" 0-0.2" 22 to 33 +/-5% 0.5 - 3.5" L1 L2 L4 L5 L1 L2 L4 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 6A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 6B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential. 0.5" Max Rs 0 to 33 L1 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Expres s Driver 49.9 +/- 5% Rt Figure 6B. Recommended Termination (where a point-to-point connection can be used) ©2016 Integrated Device Technology, Inc. 23 October 3, 2016 8413S08 Data Sheet Schematic Layout components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Figure 7 shows an example of 8413S08 application schematic. In this example, the device is operated VDD= VDDO_A= VDDO_REF= VDDO_B= VDDO_CD=VDDO_REF0= 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 18pF and C2 = 18pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 8413S08 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequency. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices R2 33 R 35 33 QA0 Logic Control Input Examples Set Logic Input to '1' VD D R U1 1K nQA0 RU2 N ot Ins tall To Logic Input pins ToLogic Input pins R D1 N ot Ins tall RD2 1K nXTAL_SEL 13 nP LL_SEL 15 F_SELA 47 F_SELB 48 OE _C D 49 OE _QR EF 0 50 R6 50 nXTA L_SE L 19 QA0 20 nQA0 21 QA1 22 nQA1 24 QA2 25 nQA2 26 QA3 27 nQA3 31 QA4 32 nQA4 33 QA5 34 nQA5 36 QA6 37 nQA6 38 QA7 39 nQA7 nPLL_S EL F _S ELA F _S ELB OE_C D OE_QR EF0 XTA L_I N X1 25MHz 11 F p 8 1 C1 18pF XTA L_OU T 12 C2 XTAL_I N XTAL_OU T 18pF Zo = 50 Ohm C LK 16 nC LK 17 C LK (U1:9)(U1:42) R 11 50 R 10 50 C27 C 26 0. 1uF 0. 1uF R12 50 V D DO_R EF V D DO_R EF V D DO_A V D DO_A V D DO_A V D DO_A V D DO_A V D DO_A FB 1 V DD m uR at a, BLM18BB221SN 1 0. 1uF 10uF 10 R30 C 21 10uF 2 V D DO_R EF C37 0.1uF C 34 10uF 0. 1uF 0.1uF V DD A 1 8 V DD O_R EF V DD O_R EF 18 23 V DD O_A 28 V DD O_A 30 V DD O_A 35 V DD O_A 40 V DD O_A V DD O_A 43 V DD O_B 51 V DD O_C D 56 V DD O_R EF0 Opt ional R 34 0-33 QB QA5 nQA 5 Zo = 50 R9 + 0-33 nQB Zo = 50 - QA6 nQA 6 HCSL Optional Termination QA7 nQA 7 R 32 50 R 31 50 Recommended for PCI Express Point-to-Point Connection 55 QR EF0 R1 30 Zo = 50 Ohm LVC MOS QR EF2 nQR E F2 3.3V R7 133 + Zo = 50 Ohm - nQRE F1 R 36 82. 5 VD D O 41 R8 133 Zo = 50 Ohm QR EF1 R 37 82.5 I R EF 57 Optional Four Resistor Thevinin Terminat ion EP AD Zo = 50 Ohm BLM18B B221SN 1 1 QA4 nQA 4 QD 2 QRE F1 3 nQRE F1 4 QRE F2 5 nQRE F2 6 QRE F3 7 nQRE F3 R3 475 3. 3V VDDO_CD=VDDO_REF0=3.3V QA3 nQA 3 QC 14 GN D 29 GN D 46 GN D 54 GN D (U1:1)(U1:8) C38 VDD=VDDO_A=VDDO_REF=VDDO_B=3.3V QA2 nQA 2 53 QRE F0 B LM18BB221S N2 Ferrit e Bead C 36 Recommended for PCI Express Add-In Card HCSL Termination QA1 nQA 1 52 QD 3.3V 1 R 33 50 44 45 QC 10 VD DA 3. 3V QB nQB 9 42 V DD V DD P EC L D ri v er C 24 - nC LK Zo = 50 Ohm C 25 + Zo = 50 U1 Set Logic Input to '0' VD D Zo = 50 QR EF3 (U1:1)(U1:8) (U1:56) 2 + VD D O_RE F Zo = 50 Ohm F errite Bead C 7 C6 0. 1uF C8 C 28 10uF 0.1uF 0. 1uF nQRE F3 C 29 - 0. 1uF R 13 50 3. 3V BLM18B B221SN 1 1 VD D O_A F errite Bead C 10 C9 0. 1uF R 15 50 (U1:18)(U1:23)(U1:28)(U1:30)(U1:35)(U1:40) 2 R 14 50 C 11 C12 C 31 C 30 C33 C 32 10uF 0.1uF 0. 1uF 0.1uF 0. 1uF 0. 1uF 0. 1uF Figure 7. 8413S08 Application Schematic The schematic example focuses on functional connections and is not configuration specific. ©2016 Integrated Device Technology, Inc. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. 24 October 3, 2016 8413S08 Data Sheet VFQFN EPAD Thermal Release Path achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 8. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 8. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ©2016 Integrated Device Technology, Inc. 25 October 3, 2016 8413S08 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 8413S08. Equations and example calculations are also provided. 1. Power Dissipation The total power dissipation for the 8413S08 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core • Power(core) = VDD_MAX * (IDD + IDDA + IDDOx) = 3.465V *(84mA + 16mA + 66mA) = 575.19mW LVPECL Output LVPECL driver power dissipation is 30mW/Loaded output pair, total LVPECL output dissipation: • Power(LVPECL) = 30mW * 4 = 120mW HSCL Output HSCL driver power dissipation is 46.8mW/Loaded output pair, total HSCL output dissipation: • Power(HSCL) = 46.8mW * 8 = 374.4mW LVCMOS Output • Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.75mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.75mA)2 = 12.3mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 12.3mW * 3 = 36.9mW Dynamic Power Dissipation at 50MHz Power (50MHz) = CPD * Frequency * (VDD)2 = 4pF * 50MHz * (3.465V)2 = 2.4mW per output Total Power (50MHz) = 2.4mW * 3 = 7.2mW Total Power Dissipation • Total Power = Power (core) + Power (LVPECL) + Power(HCSL) + Total Power (ROUT) + Total Power (50MHz) = 575.19mW + 120mW + 374.4mW + 36.9mW + 7.2mW = 1113.7mW ©2016 Integrated Device Technology, Inc. 26 October 3, 2016 8413S08 Data Sheet 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 31.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.113W *31.4°C/W = 119.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 56 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc. 0 1 2.5 31.4°C/W 27.5°C/W 24.6°C/W 27 October 3, 2016 8413S08 Data Sheet 3A. Calculations and Equations. The purpose of this section is to calculate power dissipation on the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 10. VDDO Q1 VOUT RL VDDO - 2V Figure 9. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VDDO – 2V. • For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.9V (VDDO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.7V (VDDO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc. 28 October 3, 2016 8413S08 Data Sheet 3B. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 11. VDDO IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC Figure 10. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDDO_MAX. Power = (VDDO_MAX – VOUT) * IOUT, since VOUT – IOUT * RL = (VDDO_MAX – IOUT * RL) * IOUT = (3.6V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 46.8mW ©2016 Integrated Device Technology, Inc. 29 October 3, 2016 8413S08 Data Sheet Reliability Information Table 8. JA vs. Air Flow Table for a 56 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 31.4°C/W 27.5°C/W 24.6°C/W Transistor Count The transistor count for 8413S08 is: 9994 ©2016 Integrated Device Technology, Inc. 30 October 3, 2016 8413S08 Data Sheet Package Outline and Package Dimensions Package Outline - K Suffix for 56 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL Bottom View w/Type A ID N &N Odd 0. 08 C 4 D2 2 Th er mal Ba se D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER e N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions Reference Document: JEDEC Publication 95, MO-220 JEDEC Variation: VLLD-2/-5 All Dimensions in Millimeters Symbol Minimum Maximum N 56 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 14 ND & NE D&E 8.00 Basic D2 4.35 4.65 E2 5.05 5.35 e 0.50 Basic L 0.30 0.50 ©2016 Integrated Device Technology, Inc. NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. 31 October 3, 2016 8413S08 Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number 8413S08BKILF 8413S08BKILFT Marking ICS8413S08BIL ICS8413S08BIL ©2016 Integrated Device Technology, Inc. Package “Lead-Free” 56 VFQFN “Lead-Free” 56 VFQFN 32 Shipping Packaging Tray Tape & Reel Temperature -40C to 85C -40C to 85C October 3, 2016 8413S08 Data Sheet Revision History Revision Date 10/3/16 Description of Change Updated header and footer. Removed ICS from part numbers where needed. Ordering Information - Deleted quantity from tape and reel. Removed note from below table. ©2016 Integrated Device Technology, Inc. 33 October 3, 2016 8413S08 Data Sheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com www.IDT.com/go/sales www.IDT.com/go/supp ort DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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