FemtoClock® NG Crystal-to-HCSL
Clock Generator
841604
DATASHEET
GENERAL DESCRIPTION
FEATURES
The 841604 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz
and 125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (< 1ps rms) suitable to clock components requiring precise and
low-jitter PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the 841604 can also drive the
high-speed sRIO and PCIe SerDes clock inputs of communication
processors, DSPs, switches and bridges.
• Four differential clock outputs: configurable for PCIe (100MHz)
and sRIO (125MHz) clock signals
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter, 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.45ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
OSC
FemtoClock
PLL
XTAL_OUT
REF_IN Pulldown
1
Q0
1
0
VCO = 500MHz
nQ0
÷N
0
÷4
Q1
÷5 (default)
nQ1
REF_SEL Pulldown
Q2
M = ÷20
nQ2
IREF
BYPASS Pulldown
Q3
FSEL Pulldown
nQ3
XTAL_IN
XTAL_OUT
MR/nOE
VDD
nc
nc
nc
nc
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
BYPASS
IREF
FSEL
VDD
nQ3
Q3
nQ2
Q2
GND
nQ1
Q1
nQ0
Q0
841604
MR/nOE Pulldown
841604 REVISION A 4/17/15
REF_SEL
REF_IN
VDD
GND
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
1
©2015 Integrated Device Technology, Inc.
841604 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
REF_SEL
Input
Pulldown
Pulldown LVCMOS/LVTTL PLL reference clock input.
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3D.
2
REF_IN
Input
3, 8, 14,
24
VDD
Power
Core supply pins.
4, 13, 19
GND
Power
Power supply ground.
5, 6
XTAL_IN,
XTAL_OUT
Input
7
MR/nOE
Input
9, 10, 11,
12
nc
Unused
No connect.
15, 16
Q0, nQ0
Output
Differential output pair. HCSL interface levels.
17, 18
Q1, nQ1
Output
Differential output pair. HCSL interface levels.
20, 21
Q2, nQ2
Output
Differential output pair. HCSL interface levels.
22, 23
Q3, nQ3
Output
25
FSEL
Input
26
IREF
Output
27
BYPASS
Input
28
VDDA
Power
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z). When
Pulldown
logic LOW, the internal dividers and the outputs are enabled. Asynchronous
function. LVCMOS/LVTTL interface levels. See Table 3C.
Differential output pair. HCSL interface levels.
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
HCSL current reference resistor output. An external fixed precision resistor
(475W) from this pin to ground provides a reference current used for differential current-mode Qx/nQx clock outputs.
Selects PLL operation/PLL bypass operation. Asynchronous function. LLVCPulldown
MOS/LVTTL interface levels. See Table 3B.
Analog supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
TABLE 3A. FSEL FUNCTION TABLE (f
ref
Input
Minimum
Typical
Maximum
TABLE 3B. BYPASS FUNCTION TABLE
= 25MHZ)
Outputs
Input
FSEL
N
Q0:1/nQ0:1
BYPASS
0
5
VCO/5 (100MHz) PCIe (default)
0
PLL enabled (default)
1
4
VCO/4 (125MHz) sRIO
1
PLL bypassed (fOUT = fREF ÷ N)
PLL Configuration
TABLE 3D. REF_SEL FUNCTION TABLE
TABLE 3C. MR/nOE FUNCTION TABLE
Input
Input
REF_SEL
Input Reference
0
Outputs enabled (default)
0
XTAL (default)
1
Device reset, outputs disabled (high-impedance)
1
REF_IN
MR/nOE
Function
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
Units
2
REVISION A 4/17/15
841604 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
64.5°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.15
3.3
VDD
V
IDD
IDDA
Power Supply Current
87
mA
Analog Supply Current
15
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
REF_IN, REF_SEL,
BYPASS, MR/nOE, FSEL
REF_IN, REF_SEL,
BYPASS, MR/nOE, FSEL
Minimum
Typical
Maximum
Units
2
V + 0.3
V
-0.3
0.8
V
150
µA
DD
VDD = VIN = 3.465V
-5
VDD = 3.465V, VIN = 0V
µA
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
REVISION A 4/17/15
3
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tjit(Ø)
Tj
TREFCLK_HF_RMS
RMS Phase Jitter (Random); NOTE 1
Phase Jitter Peak-to-Peak; NOTE 2
Phase Jitter RMS; NOTE 3
Test Conditions
Minimum Typical Maximum Units
VCO/5
100
MHz
VCO/4
125
MHz
100MHz, (1.875MHz - 20MHz)
0.36
ps
125MHz, (1.875MHz - 20MHz)
0.45
ps
12.81
ps
12.30
ps
1.32
ps rms
1.19
ps rms
100MHz, (1.2MHz – 50MHz),
106 samples, 25MHz crystal input
125MHz, (1.2MHz – 62.5MHz),
106 samples, 25MHz crystal input
100MHz, 106 samples,
25MHz crystal input
125MHz, 106 samples,
25MHz crystal input
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
50
ps
tsk(o)
Output Skew; NOTE 4, 5
75
ps
Rise Edge
Rate
Rising Edge Rate; NOTE 6, 7
0.6
4
V/ns
Fall Edge Rate Falling Edge Rate; NOTE 6, 7
0.6
4
V/ns
-100
100
mV
1150
mV
V RB
V MAX
VMIN
V CROSS
DVCROSS
Ringback Voltage; NOTE 6, 8
Absolute Max. Output Voltage; NOTE
9, 10
Absolute Min. Output Voltage; NOTE
9, 11
Absolute Crossing Voltage;
NOTE 9, 12, 13
Total Variation of VCross over all edges;
NOTE 9, 12, 14
-300
250
odc
Output Duty Cycle; NOTE 6, 15
48
TSTABLE
Power-up Stable Clock Output; NOTE
6, 8
500
tL
PLL Lock Time
mV
550
mV
140
mV
52
%
ps
90
ms
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note, PCI Express Reference Clock Requirements.Maximum limit for PCI Express Generation 2 is 3.1ps rms.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx).
The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential zero crossing. See Parameter Measurement Information Section.
NOTE 8: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from single ended waveform.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the V CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 15: Input duty cycle must be 50%.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
4
REVISION A 4/17/15
841604 DATA SHEET
TYPICAL PHASE NOISE AT 100MHZ
100MHz
➤
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.36ps (typical)
Raw Phase Noise Data
➤
➤
NOISE POWER dBc
Hz
PCIe Filter
Phase Noise Result by adding
a PCIe Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
125MHz
➤
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.45ps (typical)
Raw Phase Noise Data
➤
➤
NOISE POWER dBc
Hz
PCIe Filter
Phase Noise Result by adding
a PCIe Filter to raw data
OFFSET FREQUENCY (HZ)
REVISION A 4/17/15
5
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
3.3V±5%
3.3V±5%,
3.3V±5%,
VDD
100Ω
33
Measurement
Point
VDD
VDDA
VDDA
49.9Ω
IREF
GND
2pF
100Ω
33
49.9Ω
475Ω
0V
Measurement
Point
2pF
0V
This load condition is used for IDD, tsk(o), and tjit measurements.
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
RMS PHASE JITTER
TSTABLE
VRB
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Q - nQ
VRB
TSTABLE
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
6
REVISION A 4/17/15
841604 DATA SHEET
PARAMETER MEASUREMENT INFORMATION, CONTINUED
SINGLE-ENDED MEASUREMENT POINTS FOR
ABSOLUTE CROSS POINT/SWING
SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT
20
0
-3dB
1.2MHz
Mag (dB)
-20
-3dB
21.9MHz
-40
-60
-80
-100
104
105
106
Frequency (Hz)
H3(s) * (H1(s) – H2(s))
COMPOSITE PCIe TRANSFER FUNCTION
DIFFERENTIAL MESUREMENT POINTS FOR DUTY CYCLE PERIOD
REVISION A 4/17/15
7
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
107
108
841604 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The 841604
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each
pin. Figure 1 illustrates this for a generic VDD pin and also shows
that VDDA requires that an additional10Ω resistor along with a 10µF
bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
DIFFERENTIAL OUTPUTs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-downs; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
8
REVISION A 4/17/15
841604 DATA SHEET
CRYSTAL INPUT INTERFACE
The 841604 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram
is shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full swing
to half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω.
VDD
VCC
VDD
VCC
R1
Ro
.1uf
Rs
Zo = 50
Zo = Ro + Rs
XTAL_IN
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
REVISION A 4/17/15
9
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
SCHEMATIC EXAMPLE
Figure 4 shows an example of 841604 application schematic. In
this example, the device is operated at VDD = 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of HCSL terminations are shown in this
schematic. The decoupling capacitors should be located as close
as possible to the power pin.
VDD
R1
VDD
VDDA
10
C4
0.1u
C3
10u
R2
33
Zo = 50
R3
475
-
TL1
R4
33
Zo = 50
X1
25MHz
18pF
C1
27pF
+
TL2
U1
REF_SEL
C2
27pF
VDD
MR/nOE
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REF_SEL
REF_IN
VDD
GND
XTAL_IN
XTAL_OUT
MR_nOE
VDD
nc
nc
nc
nc
GND
VDD
VDDA
BY PASS
IREF
FSEL
VDD
nQ3
Q3
nQ2
Q2
GND
nQ1
Q1
nQ0
Q0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R5
50
R6
50
Recommended for
PCI Express Add-In
Card
BY PASS
FSEL
VDD
VDD=3.3V
HCSL Termination
ICS841604I
Logic Control Input Examples
Zo = 50
Set Logic
Input to
'1'
VDD
RU1
1K
Set Logic
Input to
'0'
VDD
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
-
TL3
Zo = 50
VDD
(U1:3)
VDD
(U1:8)
(U1:14)
(U1:24)
C6
.1uf
C7
.1uf
C8
.1uf
+
TL4
R7
50
C5
.1uf
RD2
1K
R8
50
Recommended for PCI
Express Point-to-Point
Connection
FIGURE 4. 841604 SCHEMATIC EXAMPLE
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
10
REVISION A 4/17/15
841604 DATA SHEET
RECOMMENDED TERMINATION
Figure 5A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
0.7V Differential HCSL
Add-In Card
0.7V Differential HCSL
Clock Driver
FIGURE 5A. RECOMMENDED TERMINATION
Figure 5B is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50Ω impedance.
0.7V Differential HCSL
Clock Driver
FIGURE 5B. RECOMMENDED TERMINATION
REVISION A 4/17/15
11
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 841604.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS41604I is the sum of the core power plus the analog plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA) = 3.465V * (87mA + 15mA) = 353.43mW
Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 44.5mW = 178mW
Total Power_MAX (3.465V, with all outputs switching) = 353.43mW + 178mW = 531.43mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 64.54°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.531W * 64.5°C/W = 119.2 °C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
64.5°C/W
12
1
2.5
60.4°C/W
58.5°C/W
REVISION A 4/17/15
841604 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
FIGURE 6. HCSL DRIVER CIRCUIT AND TERMINATION
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD is HIGH.
Power
= (VDD_HIGH – VOUT ) * IOUT, since VOUT = IOUT * RL
= (VDD_HIGH – IOUT * RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
REVISION A 4/17/15
13
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
64.5°C/W
1
2.5
60.4°C/W
58.5°C/W
TRANSISTOR COUNT
The transistor count for 841604 is: 2785
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
28
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
9.60
9.80
E
E1
8.10 BASIC
6.00
e
6.20
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
14
REVISION A 4/17/15
841604 DATA SHEET
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
841604AGILF
ICS841604AGILF
28 Lead “Lead-Free” TSSOP
tube
-40°C to 85°C
841604AGILFT
ICS841604AGILF
28 Lead “Lead-Free” TSSOP
tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION A 4/17/15
15
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
REVISION HISTORY SHEET
Rev
A
Table
Page
T10
15
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
Description of Change
Ordering Information - removed leaded devices.
Updated data sheet format.
16
Date
4/17/15
REVISION A 4/17/15
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(Rev.1.0 Mar 2020)
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