841S04
PCI Express™ Clock Generator
Datasheet
General Description
Features
The 841S04 is a PLL-based clock generator specifically designed for
PCI Express™ Clock Generation applications. This device
generates a 100MHz HCSL clock. The device offers a HCSL (Host
Clock Signal Level) clock output from a clock input reference of
25MHz. The input reference may be derived from an external source
or by the addition of a 25MHz crystal to the on-chip crystal oscillator.
An external reference may be applied to the XTAL_IN pin with the
XTAL_OUT pin left floating.
•
•
•
•
•
•
•
•
•
•
•
The device offers spread spectrum clock output for reduced EMI
applications. An I2C bus interface is used to enable or disable spread
spectrum operation as well as select either a down spread value of
-0.35% or -0.5%.
Block Diagram
25MHz
4
PLL
Divider
Network
4
SRCT[1:4]
SRCC[1:4]
XTAL_OUT
SDATA Pullup
SCLK Pullup
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
RMS period jitter: 3ps (maximum)
Output skew: 70ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
I2C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_IN
OSC
Four 0.7V current mode differential HCSL output pairs
I2C
Logic
4
IREF
SRCT3
SRCC3
VSS
VDD
SRCT2
SRCC2
SRCT1
SRCC1
VSS
VDD
VSS
IREF
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SRCC4
SRCT4
VDD
SDATA
SCLK
XTAL_OUT
XTAL_IN
VDD
VSS
nc
VDDA
VSS
841S04
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
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841S04 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
SRCT3, SRCC3
Output
Differential output pair. HCSL interface levels.
3, 9, 11, 13, 16
VSS
Power
Ground for core and SRC outputs.
4, 10, 17, 22
VDD
Power
Power supply for core and SRC outputs.
5, 6
SRCT2, SRCC2
Output
Differential output pair. HCSL interface levels.
7, 8
SRCT1, SRCC1
Output
Differential output pair. HCSL interface levels.
12
IREF
Input
14
VDDA
Power
An external fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx clock
outputs.
Power supply for PLL.
15
nc
Unused
18,
19
XTAL_IN,
XTAL_OUT
No connect.
Input
20
SCLK
Input
Pullup
I2C SMBus compatible SCLK. This pin has an internal pullup resistor, but is in
high-impedance in power-down mode. LVCMOS/LVTTL interface levels.
21
SDATA
I/O
Pullup
I2C SMBus compatible SDATA. This pin has an internal pullup resistor, but is
in high-impedance in power-down mode. LVCMOS/LVTTL interface levels.
23, 24
SRCT4, SRCC4
Output
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Differential output pair. HCSL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
©2016 Integrated Device Technology, Inc.
Test Conditions
2
Minimum
Typical
Maximum
Units
Revision C, July 15, 2016
841S04 Datasheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock output
buffers, can be individually enabled or disabled. The registers
associated with the Serial Data Interface initialize to their default
setting upon power-up, and therefore, use of this interface is optional.
Clock device register changes are normally made upon system
initialization, if any are required. The interface cannot be used during
system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write, and block read operations from the controller. For block
write/read operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the ability
to stop after any complete byte has been transferred. For byte write
and byte read operations, the system controller can access
individually indexed bytes. The offset of the indexed byte is encoded
in the command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B, while
Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
6:5
Chip select address, set to “00” to access device.
4:0
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
Description = Block Write
Start
Slave address - 7 bits
Bit
Description = Block Read
1
Start
2:8
Slave address - 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits
11:18
Command Code - 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
Byte Count - 8 bits
20
Repeat start
20:27
28
29:36
37
38:45
46
Acknowledge from slave
21:27
Slave address - 7 bits
Data byte 1 - 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
30:37
Byte Count from slave - 8 bits
38
Acknowledge
39:46
Data Byte 1 from slave - 8 bits
47
Acknowledge
48:55
Data Byte 2 from slave - 8 bits
56
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
©2016 Integrated Device Technology, Inc.
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841S04 Datasheet
Table 3C. Byte Read and Byte Write Protocol
Bit
Description = Byte Write
1
Start
2:8
Bit
Description = Byte Read
1
Slave address - 7 bits
Start
2:8
Slave address - 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits
11:18
Command Code - 8 bits
Acknowledge from slave
19
Acknowledge from slave
Data Byte- 8 bits
20
Repeat start
19
20:27
28
Acknowledge from slave
29
Stop
21:27
Slave address - 7 bits
28
Read
29
Acknowledge from slave
30:37
Data from slave - 8 bits
38
Not Acknowledge
39
Stop
Control Registers
Table 4A. Byte 0: Control Register 0
Bit
@Pup
Name
7
0
Reserved
6
5
1
1
Table 4B. Byte 1: Control Register 1
Description
Bit
@Pup
Name
Description
Reserved
7
0
Reserved
Reserved
6
0
Reserved
Reserved
SRC[T/C]4
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z)
1 = Enable
5
0
Reserved
Reserved
4
0
Reserved
Reserved
SRC[T/C]3
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z)
1 = Enable
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
4
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
3
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z)
1 = Enable
2
1
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Table 4C. Byte 2: Control Register 2
NOTE: Pup denotes Power-up.
©2016 Integrated Device Technology, Inc.
4
Bit
@Pup
Name
Description
7
1
SRCT/C
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
6
1
Reserved
Reserved
5
1
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
2
0
SRC
1
1
Reserved
Reserved
0
0
Reserved
Reserved
SRC Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
Revision C, July 15, 2016
841S04 Datasheet
Table 4G. Byte 6: Control Register 6
Table 4D. Byte 3:Control Register 3
Bit
@Pup
Name
Description
7
1
Reserved
Reserved
6
0
Reserved
Reserved
5
1
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
2
1
Reserved
Reserved
1
1
Reserved
Reserved
0
1
Reserved
Reserved
NOTE: Pup denotes Power-up.
Table 4E. Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
1
Reserved
Table 4F. Byte 5: Control Register 5
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
©2016 Integrated Device Technology, Inc.
@Pup
Name
7
0
TEST_SEL
Description
REF/N or Hi-Z Select
0 = Hi-Z,
1 = REF/N
TEST Clock
Mode Entry Control
0 = Normal Operation,
1 = REF/N or Hi-Z Mode
6
0
TEST_MODE
5
0
Reserved
Reserved
4
1
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
1
Reserved
Reserved
0
1
Reserved
Reserved
Table 4H. Byte 7: Control Register 7
Reserved
Bit
Bit
5
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
5
0
Revision Code Bit 1
4
0
Revision Code Bit 0
3
0
Vendor ID Bit 3
2
0
Vendor ID Bit 2
1
0
Vendor ID Bit 1
0
1
Vendor ID Bit 0
Revision C, July 15, 2016
841S04 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, JA
77.5C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.21
3.3
VDD
V
IDD
Power Supply Current
80
mA
IDDA
Analog Supply Current
21
mA
Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
SDATA, SCLK
VDD = VIN = 3.465V
IIL
Input Low Current
SDATA, SCLK
VDD = 3.465V, VIN = 0V
Minimum
Typical
Maximum
2.2
©2016 Integrated Device Technology, Inc.
6
-150
Units
V
1.0
V
10
µA
µA
Revision C, July 15, 2016
841S04 Datasheet
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fref
Frequency
SCLK
SCLK Frequency
Frequency Tolerance;
NOTE 1
Test Conditions
Minimum
Typical
Maximum
25
Units
MHz
400
kHz
XTAL
50
ppm
External
Reference
0
ppm
53
%
70
ps
10.0533
ns
35
ps
3
ps
700
ps
20
%
odc
SRCT/SRCC Output Duty Cycle; NOTE 2, 3
tsk(o)
SRCT/C to SRCT/C Output Clock Skew;
NOTE 2, 3
tPERIOD
Average Period; NOTE 4
47
9.9970
tjit(cc)
SRCT/C Cycle-to-Cycle Jitter; NOTE 2, 3
tjit(per)
Period Jitter, RMS; NOTE 2, 3, 5
t R / tF
SRCT/SRCC Rise/Fall Time; NOTE 6
tRFM
Rise/Fall Time Matching; NOTE 7
tDC
XTAL_IN Duty Cycle; NOTE 8
tR / tF
Rise/Fall Time Variation
VHIGH
Voltage High
520
VLOW
Voltage Low
-150
VCROSS
Absolute Crossing Voltage
250
VCROSS
Total Variation of VCROSS over all edges
VOX
Output Crossover Voltage
VOVS
Maximum Overshoot Voltage
VUDS
Minimum Undershoot Voltage
VRB
Ring Back Voltage
2.24
150
47.5
@ 0.7V Swing
250
52.5
%
145
ps
875
mV
mV
550
mV
140
mV
550
mV
VHIGH + 0.3
V
-0.3
V
0.2
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: With recommended crystal.
NOTE 2: Measured at crossing point VOX.
NOTE 3: Measured using a 50 to GND termination.
NOTE 4: Measured at crossing point VOX at 100MHz.
NOTE 5: If using the RMS period jitter to calculate peak-to-peak jitter, then use the typical RMS period jitter specification times the RMS
multiplier. For example, for a bit error rate of 10E-12, the peak-to-peak jitter would be 2.24ps x 14 = 31.36ps.
NOTE 6: Measured from VOL = 0.175V to VOH = 0.525V.
NOTE 7: Determined as a fraction of 2*(tR – tF) / (tR + tF).
NOTE 8: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification.
©2016 Integrated Device Technology, Inc.
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Revision C, July 15, 2016
841S04 Datasheet
Parameter Measurement Information
3.3V±5%
3.3V±5%
SRCC[1:4]
VDD
SRCT[1:4]
VDDA
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
3.3V HCSL Output Load AC Test Circuit
Cycle-to-Cycle Jitter
HIGH
SRCCx
VREF
SRCTx
LOW
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
SRCCy
SRCTy
Histogram
Mean Period
(First edge after trigger)
Period Jitter
Output Skew
SRCC[1:4]
SRCC[1:4]
SRCT[1:4]
SRCT[1:4]
Output Duty Cycle/Pulse Width/Period
©2016 Integrated Device Technology, Inc.
HCSL Output Rise/Fall Time
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Revision C, July 15, 2016
841S04 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
Differential Outputs
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Table 7. Recommended Crystal Specifications
Symbol
Parameter
Value
Crystal Cut
Fundamental at Cut
Resonance
Parallel Resonance
CL
Load Capacitance
18pF
CO
Shunt Capacitance
5pF - 7pF
ESR
Equivalent Series Resistance
20 - 50
Output Driver Current
The 841S04 outputs are HCSL current drive with the current being
set with a resistor from IREF to ground. For a 50 P.C. board trace, the
drive current would typically be set with a RREF of 475 which
products an IREF of 2.32mA. The IREF is multiplied by a current mirror
to an output drive of 6*2.32mA or 13.92mA. See Figure 1 for current
mirror and output drive details.
IREF
RREF
RL
RL
Figure 1. HCSL Current Mirror and Output Drive
©2016 Integrated Device Technology, Inc.
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Revision C, July 15, 2016
841S04 Datasheet
Recommended Termination
Figure 2A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
0.5" Max
Rs
types. All traces should be 50Ω impedance single-ended or 100Ω
differential.
1-14"
0-0.2"
22 to 33 +/-5%
L1
L2
L4
L1
L2
L4
0.5 - 3.5"
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 2A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 2B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 2B. Recommended Termination (where a point-to-point connection can be used)
©2016 Integrated Device Technology, Inc.
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Revision C, July 15, 2016
841S04 Datasheet
Schematic Layout
Figure 3 shows an example of 841S04 application schematic. In this
example, the device is operated at VDD = 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The load capacitance C1 = 18pF
and C2 = 18pF is recommended for frequency accuracy. Depending
on the parasitic of the printed circuit board layout, these values might
require a slight adjustment for optimize the frequency accuracy.
Crystals with other load capacitance specifications can be used. This
will required adjusting C1 and C2. For this device, the crystal load
capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 841S04 provides separate power
supplies to isolate noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
R5
33
SRCT1
Zo = 50
R7
SRCC1
VDD
+
33
Zo = 50
-
VDD
R8
50
R9
50
Recommended for PCI
Express Add-In Card
IREF
12
11
10
9
8
7
6
5
4
3
2
1
U1
IREF
VSS
VDD
VSS
SRCC1
SRCT1
SRCC2
SRCT2
VDD
VSS
SRCC3
SRCT3
R13
475
VSS
VDDA
nc
VSS
VDD
XTAL_IN
XTAL_OUT
SCLK
SDATA
VDD
SRCT4
SRCC4
HCSL Termination
13
14
15
16
17
18
19
20
21
22
23
24
Optional
R9
0-33
SRCT4
VDD
Zo = 50
+
VDDA
R3
10
VDD
C3
R10
0-33
SRCC4
C4
0.1u
10uF
Zo = 50
-
VDD
C1
18pF
25MHz
X1
R7
50
F
p
8
1
VDD
HCSL Optional
Termination
R8
50
Recommended for PCI
Express Point-to-Point
Connection
C2
18pF
3.3V
R6
SP
BLM18BB221SN1
R7
SP
1
SCLK
SDATA
Ferrite Bead
C6
C5
0.1uF
VDD
(U1-4)
2
10uF
(U1-10)
(U1-17)
C8
0.1uF
C9
0.1uF
VDD
C7
0.1uF
(U1-22)
C10
0.1uF
Figure 3. 841S04 Application Schematic
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
©2016 Integrated Device Technology, Inc.
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
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Revision C, July 15, 2016
841S04 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 841S04.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 841S04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
The maximum current at 85°C is as follows:
IDD_MAX = 77mA
IDDA_MAX = 20mA
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(77mA + 20mA) = 336.105mW
•
Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 44.5mW = 178mW
Total Power_MAX = 336.105mW + 178mW = 514.105mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 77.5°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.514W * 77.5°C/W = 124.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
77.5°C/W
73.2°C/W
71.0°C/W
12
Revision C, July 15, 2016
841S04 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 4.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
Figure 4. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power
= (VDD_MAX – VOUT) * IOUT,
since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
©2016 Integrated Device Technology, Inc.
13
Revision C, July 15, 2016
841S04 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
77.5°C/W
73.2°C/W
71.0°C/W
Transistor Count
The transistor count for 841S04 is: 1874
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 10. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc.
14
Revision C, July 15, 2016
841S04 Datasheet
Ordering Information
Table 11. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
841S04CGILF
ICS841S04CGIL
“Lead-Free” 24 Lead TSSOP
Tube
-40C to 85C
841S04CGILFT
ICS841S04CGIL
“Lead-Free” 24 Lead TSSOP
Tape & Reel
-40C to 85C
©2016 Integrated Device Technology, Inc.
15
Revision C, July 15, 2016
841S04 Datasheet
Revision History Sheet
Rev
A
A
Table
Page
Description of Change
Date
T11
11
15
Schematic Layout - updated text.
Ordering Information Table - added non-lead-free information.
2/1/11
T11
15
Removed leaded orderable parts from Ordering Information table
11/14/12
Updated datasheet header/footer.
Deleted “ICS” prefix and “I” suffix from part number.
5/24/16
Features section, corrected last bullet.
7/15/16
B
C
1
©2016 Integrated Device Technology, Inc.
16
Revision C, July 15, 2016
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