Crystal-to-HCSL, 100MHz PCI Express ™
Clock Synthesizer
General Description
Features
The 841S102 is a PLL-based clock synthesizer specifically designed
for PCI_Express™ Clock applications. This device generates a
100MHz differential HCSL clock from an input reference of 25MHz.
The input reference may be derived from an external source or by
the addition of a 25MHz crystal to the on-chip crystal oscillator. An
external reference is applied to the XTAL_IN pin with the XTAL_OUT
pin left floating.The device offers spread spectrum clock output for
reduced EMI applications. An I2C bus interface is used to enable or
disable spread spectrum operation as well as select either a down
spread value of -0.35% or -0.5%.The 841S102 is available in a
lead-free package.
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841S102
Datasheet
Two 0.7V current mode differential HCSL output pairs
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.23ps (typical)
Cycle-to-cycle jitter: 20ps (maximum)
I2C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) package
PCI Express Gen 1, 2 and 3 jitter compliant
HiPerClockS™
Block Diagram
XTAL_IN
Pin Assignment
25MHz
OSC
PLL
XTAL_OUT
SDATA
Pullup
SCLK
Pullup
I2C
Logic
Divider
Network
2
2
SRCT[1:2]
SRCC[1:2]
2
VSS
VDD
SRCT2
SRCC2
SRCT1
SRCC1
VSS
VDD
VSS
IREF
IREF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
SDATA
SCLK
nc
XTAL_OUT
XTAL_IN
VDD
VSS
VDDA
VSS
841S102
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Pin Description and Pin Characteristics Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 7, 9, 11,
13
VSS
Power
Power supply ground.
2, 8,
14, 20
VDD
Power
Power supply pins.
3, 4
SRCT2, SRCC2
Output
Differential output pair. HCSL interface levels.
5, 6
SRCT1, SRCC1
Output
Differential output pair. HCSL interface levels.
10
IREF
Input
An external fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx clock
outputs.
12
VDDA
Power
Analog supply for PLL.
15, 16
XTAL_IN, XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
17
nc
Unused
18
SCLK
Input
Pullup
I2C compatible SCLK. This pin has an internal pullup resistor. Open drain.
LVCMOS/LVTTL interface levels.
19
SDATA
I/O
Pullup
I2C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
No connect.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
51
k
©2016 Integrated Device Technology, Inc.
Test Conditions
2
Minimum
Typical
Maximum
Units
Revision B, July 7, 2016
841S102 Datasheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. Through the Serial Data
Interface, various device functions, such as clock output buffers, can
be individually enabled or disabled. The registers associated with the
serial interface initialize to their default setting upon power-up, and
therefore, use of this interface is optional. Clock device register
changes are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write and block read operations from the controller. For block
write/read operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the ability to
stop after any complete byte has been transferred. For byte write and
byte read operations, the system controller can access individually
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B, while
Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
6:5
Chip select address, set to “00” to access device.
4:0
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
Description = Block Write
Bit
Start
1
Slave address - 7 bits
2:8
Description = Block Read
Start
Slave address - 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits
11:18
Command Code - 8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count - 8 bits
20
Repeat start
19
20:27
28
29:36
37
38:45
46
Acknowledge from slave
21:27
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
28
Read = 1
29
Acknowledge from slave
30:37
Acknowledge from slave
38
Data Byte/Slave Acknowledges
39:46
Data Byte N - 8 bits
47
Acknowledge from slave
48:55
Stop
Slave address - 7 bits
56
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Table 3C. Byte Read and Byte Write Protocol
Bit
1
2:8
Description = Byte Write
Bit
Start
1
Slave address - 7 bits
2:8
Description = Byte Read
Start
Slave address - 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits
11:18
Command Code - 8 bits
Acknowledge from slave
19
Acknowledge from slave
Data Byte - 8 bits
20
Repeat start
19
20:27
28
Acknowledge from slave
29
Stop
©2016 Integrated Device Technology, Inc.
21:27
4
Slave address - 7 bits
28
Read
29
Acknowledge from slave
30:37
Data from slave - 8 bits
38
Not Acknowledge
39
Stop
Revision B, July 7, 2016
841S102 Datasheet
Control Registers
Table 3G. Byte 3:Control Register 3
Table 3D. Byte 0: Control Register 0
Bit
@Pup
Name
7
0
Reserved
6
1
5
1
4
1
Description
Bit
@Pup
Name
Description
Reserved
7
1
Reserved
Reserved
Reserved
Reserved
6
0
Reserved
Reserved
Reserved
Reserved
5
1
Reserved
Reserved
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
4
0
Reserved
Reserved
SRC[T/C]2
3
1
Reserved
Reserved
2
1
Reserved
Reserved
1
1
Reserved
Reserved
0
1
Reserved
Reserved
3
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z)
1 = Enable
2
1
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
NOTE: Pup denotes Power-up.
Table 3E. Byte 1: Control Register 1
Table 3H. Byte 4: Control Register 4
Bit
@Pup
Name
Description
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
7
0
Reserved
Reserved
6
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
0
1
Reserved
Reserved
Table 3F. Byte 2: Control Register 2
Bit
@Pup
Name
Table 3I. Byte 5: Control Register 5
Description
7
1
SRCT/C
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
6
1
Reserved
Reserved
5
1
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
SRC Spread Spectrum
Enable
0 = Spread Off,
1 = Spread On
2
0
SRC
1
1
Reserved
Reserved
0
0
Reserved
Reserved
©2016 Integrated Device Technology, Inc.
5
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Revision B, July 7, 2016
841S102 Datasheet
Table 3J. Byte 6: Control Register 6
Bit
@Pup
Name
7
0
TEST_SEL
Table 3K. Byte 7: Control Register 7
Description
REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N
TEST Clock
Mode Entry Control
TEST_MODE
0 = Normal Operation,
1 = REF/N or Hi-Z Mode
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
5
0
Revision Code Bit 1
4
0
Revision Code Bit 0
6
0
3
0
Vendor ID Bit 3
5
0
Reserved
Reserved
2
0
Vendor ID Bit 2
4
1
Reserved
Reserved
1
0
Vendor ID Bit 1
3
0
Reserved
Reserved
0
1
Vendor ID Bit 0
2
0
Reserved
Reserved
1
1
Reserved
Reserved
0
1
Reserved
Reserved
NOTE: Pup denotes Power-up.
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, JA
81.3C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.22
3.3
VDD
V
IDD
Power Supply Current
80
mA
IDDA
Analog Supply Current
22
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage SDATA, SCLK
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current SDATA, SCLK
10
µA
IIL
Input Low Current
SDATA, SCLK
SDATA, SCLK
Minimum
Typical
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
-150
µA
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications, VDD = 3.3V±5%, TA = -40°C to 85°C
Typical
Maximum
PCIe Industry
Specification
Units
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.3
19.3
86
ps
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.07
1.53
3.1
ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS; NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.19
0.32
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.18
0.3
0.8
ps
Parameter
Symbol
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
tREFCLK_HF_RMS
(PCIe Gen 2)
Test Conditions
Minimum
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the
datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen
1 is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
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Revision B, July 7, 2016
841S102 Datasheet
Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
100
MHz
fREF
Reference frequency
25
MHz
tjit(Ø)
Phase Jitter, RMS (Random);
NOTE 1
1.23
ps
tsk(o)
Output Skew; NOTE 2, 3
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
tL
PLL Lock Time
FM
SSC Modulation Frequency;
NOTE 4
SSCRED
Spectral Reduction; NOTE 4
VRB
Ring-back Voltage Margin;
NOTE 5, 6
VMAX
Absolute Max. Output Voltage;
NOTE 7, 8
VMIN
Absolute Min. Output Voltage;
NOTE 7, 9
-300
VCROSS
Absolute Crossing Voltage;
NOTE 7, 10, 11
250
VCROS
S
35
PLL Mode
25MHz Crystal
30
32
-7
-10
-100
Measured between 150mV to
+150mV
Output Duty Cycle
ps
20
ps
55
ms
33.33
kHz
dB
100
mV
1150
mV
mV
550
mV
140
mV
0.6
4.0
V/ns
48
52
%
Total Variation of VCROSS over all
edges; NOTE 7, 10, 12
Rise/Fall Edge Rate;
NOTE 7, 13
odc
25MHz crystal, ƒ = 100MHz,
Integration Range: 12kHz – 20MHz
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using a 25MHz quartz crystal.
NOTE 1: Refer to phase jitter plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Spread Spectrum clocking enabled.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 7: Measurement taken from single-ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 12: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in
Vcross for any particular system.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Noise Power dBc
Hz
Typical Phase Noise at 100MHz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Parameter Measurement Information
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
VDD
Measurement
Point
VDD
VDDA
VDDA
2pF
Measurement
Point
IREF
GND
2pF
0V
This load condition is used for IDD, tjit(cc), tjit(Ø), and tsk(o)
measurements.
0V
3.3V HCSL Output Load Test Circuit
3.3V HCSL Output Load Test Circuit
SRCC1,
SRCC2
SRCT1,
SRCT2
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
RMS Phase Jitter
Cycle-to-Cycle Jitter
VMAX
SRCC
SRCC
VCROSS_MAX
VCROSS
VCROSS_MIN
SRCT
VMIN
SRCT
Single-ended Measurement Points for Absolute Cross
Point and Swing
©2016 Integrated Device Technology, Inc.
Single-ended Measurement Points for Delta Cross Point
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841S102 Datasheet
Parameter Measurement Information, continued
TSTABLE
VRB
Rise Edge Rate
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Fall Edge Rate
+150mV
0.0V
-150mV
SRCT SRCC
SRCC SRCT
VRB
TSTABLE
Differential Measurement Points for Ringback
Differential Measurement Points for Rise/Fall Edge Rate
Clock Period (Differential)
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
0.0V
SRCT SRCC
Differential Measurement Points for Duty Cycle/Period
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 841S102 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD and VDDA should be individually connected
to the power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates this for a
generic VDD pin and also shows that VDDA requires that an additional
10 resistor along with a 10F bypass capacitor be connected to the
VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
Differential Outputs
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Crystal Input Interface
The 841S102 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
XTAL_IN
C1
18pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
18pF
Figure 2. Crystal Input Interface
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
Recommended Termination
Figure 4A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
0.5" Max
Rs
types. All traces should be 50Ω impedance single-ended or 100Ω
differential.
0.5 - 3.5"
1-14"
0-0.2"
22 to 33 +/-5%
L1
L2
L4
L1
L2
L4
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 4B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 4B. Recommended Termination (where a point-to-point connection can be used)
©2016 Integrated Device Technology, Inc.
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841S102 Datasheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
PCIe Gen 2A Magnitude of Transfer Function
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
©2016 Integrated Device Technology, Inc.
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
16
Revision B, July 7, 2016
841S102 Datasheet
Schematic Layout
Figure 5 shows an example of the 841S102 application schematic
where the device is operated at VDD = 3.3V with an 18pF parallel
resonant 25MHz crystal. The schematic focuses on functional
connections and is intended as an example only and may not
represent the exact user configuration. For example the I2C bus
connections are shown as optionally provided via a two pin header
whereas they could just as easily be driven from an FPGA. Two types
of HCSL termination are shown in this schematic; one for PCIe add-in
cards and one for point to point connections, which are connections
on the same PCB as the 841S102.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter
performance isolation of the VDD pin from power supply is required.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uf capacitor on the VDD pin must be placed on the device side with
direct return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices.The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
Tuning caps C1 and C2 are required for frequency accuracy.
C1 = C2 = 18pF are used in this example as typical values, but their
value may be adjusted slightly up or down to optimize the oscillator
frequency accuracy. When routing the load caps be sure to keep all
routing on the top layer. Route the ground connection of C1 and C2
together and then to a ground at the 841S102. Do not share the
tuning capacitor ground with any other ground, that is ensure that
only crystal current circulates in the tuning capacitors.
©2016 Integrated Device Technology, Inc.
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Revision B, July 7, 2016
841S102 Datasheet
R1
33
SRCT1
Zo = 50
+
TL1
VDD
R2
33
SRCC1
Zo = 50
-
TL2
VDD
R3
50
SRCC2
SRCT2
C6
0.1uF
C5
0.1uF
U1
Recommended for PCI Express Add-In Card
10
9
8
7
6
5
4
3
2
1
IREF
R4
50
IREF
VSS
VDD
VSS
SRCC1
SRCT1
SRCC2
SRCT2
VDD
VSS
R5
VSS
VDDA
VSS
VDD
XTAL_IN
XTAL_OUT
nc
SCLK
SDATA
VDD
475 Ohm
11
12
13
14
15
16
17
18
19
20
VDD
HCSL Termination
R6
10
VDD
VDDA
C4
0.01u
C3
10uF
VDD
C7
0.1uF
SRCT2
C8
0.1uF
25MHz (18pF)
X1
+
TL3
SRCC2
C2
18pF
Zo = 50
C1
18pF
Zo = 50
-
TL4
3.3V
R9
SP
J1
5
4
3
2
1
R11
R10
SP
SCLK
SDATA
R7
50
Recommended for PCI Express Point-to-Point Connection
0
VDD
3.3V
SDA
2
R12
R8
50
FB1
1
BLM18BB221SN1
0
SCL
C10
10uF
C9
0.1uF
Figure 5. 841S102 Application Schematic.
©2016 Integrated Device Technology, Inc.
18
Revision B, July 7, 2016
841S102 Datasheet
Spread Spectrum
Spread-spectrum clocking is a frequency modulation technique for
EMI reduction. When spread-spectrum is enabled, a 32kHz triangle
waveform is used with 0.35% or 0.5% down-spread from the nominal
100MHz clock frequency. An example of a triangle frequency
modulation profile is shown in Figure 6A below.
An example of the amount of down spread relative to the nominal
clock frequency can be seen in the frequency domain, as shown in
Figure 6B. The ratio of this difference to the fundamental frequency
is typically 0.35% or 0.5%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 6B. It is important to note the
841S102 7dB minimum spectral reduction is the component-specific
EMI reduction, and will not necessarily be the same as the system
EMI reduction.
➤
The 841S102 triangle modulation frequency deviation is either 0.35%
or 0.5% down-spread from the nominal clock frequency.
Frequency
Fnom
(1 - δ) Fnom
0.5/fm
1/fm
➤
Time
Figure 6A. Triangle Frequency Modulation
– 7 dBm
B
A
= 0.35 or 0.5%%
Figure 6B. 100MHz Typical Clock Output In Frequency Domain
(A) Spread-Spectrum OFF
(B) Spread-Spectrum ON
©2016 Integrated Device Technology, Inc.
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Revision B, July 7, 2016
841S102 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 841S102.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 841S102 is the sum of the core power plus the analog, plus the power dissipated due to loading.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
The maximum current at 85°C is as follows:
IDD_MAX = 75mA
IDDA_MAX = 20mA
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(75mA + 20mA) = 329.175mW
•
Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 44.5mW = 89mW
Total Power_MAX = 329.175mW + 89mW = 418.175mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.418W * 81.3°C/W = 119°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc.
0
1
2.5
81.3°C/W
76.9°C/W
74.8°C/W
20
Revision B, July 7, 2016
841S102 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 7.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
Figure 7. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power
= (VDD_MAX – VOUT) * IOUT,
since VOUT – IOUT * RL
= (VDD_MA – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
©2016 Integrated Device Technology, Inc.
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Revision B, July 7, 2016
841S102 Datasheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
81.3°C/W
76.9°C/W
74.8°C/W
Transistor Count
The transistor count for 841S102 is: 11,775
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc.
22
Revision B, July 7, 2016
841S102 Datasheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
841S102EGILF
ICS41S102EIL
“Lead-Free” 20 Lead TSSOP
Tube
-40C to 85C
841S102EGILFT
ICS41S102EIL
“Lead-Free” 20Lead TSSOP
Tape & Reel
-40C to 85C
©2016 Integrated Device Technology, Inc.
23
Revision B, July 7, 2016
841S102 Datasheet
Revision History Sheet
Rev
A
B
Table
Page
Description of Change
13
14
16, 17
18
Updated the “Overdriving the XTAL Interface” note.
Updated the termination note.
Updated schematic and text.
Spread Spectrum note, second paragraph: The 841S102 triangle modulation
frequency deviation is Either 0.35% Or 0.5% down-spread from the nominal clock
frequency
2/8/13
Updated datasheet header/footer.
Deleted “ICS” prefix and “I” suffix in the part number.
7/7/16
©2016 Integrated Device Technology, Inc.
Date
24
Revision B, July 7, 2016
841S102 Datasheet
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