843002AGI-01LF

843002I-01 FemtoClocks® Crystal-to3.3V, 2.5V LVPECL Frequency Synthesizer DATASHEET GENERAL DESCRIPTION FEATURES The 843002I-01 is a 2 output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The 843002I-01 uses IDT’s FemtoClock® low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernetjitter requirements. The 843002I-01 is packaged in a small 20-pin TSSOP package. • Two 3.3V or 2.5V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.55ps (typical) • Output skew: 30ps (maximum) • Supply Voltage Modes Core/Outputs 3.3/3.3 2.5/2.5 • -40°C to 85°C ambient operating temperature • Available in lead-free RoHS-compliant package FREQUENCY SELECT FUNCTION TABLE PIN ASSIGNMENT Inputs F_SEL1 F_SEL0 0 0 25 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125 N Divider Value 4 nc VCCO Q0 nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC Output Frequency (25MHz Ref.) M Divider Value 156.25 (default) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCO Q1 nQ1 VEE VCC nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 843002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Q0 Top View BLOCK DIAGRAM F_SEL[1:0] Pulldown nPLL_SEL REF_CLK 2 Pulldown F_SEL[1:0] Pulldown 1 1 ÷4 (default) 01 10 11 ÷5 ÷10 ÷5 nQ0 Q1 nQ1 25MHz XTAL_IN 00 OSC XTAL_OUT 0 Phase Detector VCO 625MHz 0 (w/25MHz Reference) nXTAL_SEL Pulldown M = 25 (fixed) MR Pulldown 843002I-01 REVISION A 2/20/15 1 ©2015 Integrated Device Technology, Inc. 843002I-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name 1, 7 nc Type 2, 20 VCCO Power 3, 4 Q0, nQ0 Ouput Unused Description No connect. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS/LVTTL Pulldown interface levels. 5 MR Input 6 nPLL_SEL Input 8 VCCA Power 9, 11 F_SEL0, F_SEL1 Input 10, 16 VCC Power Core supply pin. 12, 13 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. 14 REF_CLK Input Pulldown LVCMOS/LVTTL reference clock input. 15 nXTAL_SEL Input Selects between crystal or REF_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 17 VEE Power Negative supply pins. 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. NOTE: refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Pulldown TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Test Conditions 2 Minimum Typical Maximum Units REVISION A 2/20/15 843002I-01 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter VCC VCCA Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.97 3.3 3.63 V Analog Supply Voltage 2.97 3.3 3.63 V VCCO Output Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 130 mA ICCA Analog Supply Current 13 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 VCCO Output Supply Voltage 2.375 2.5 2.625 V 2.5 2.625 V IEE Power Supply Current 115 mA ICCA Analog Supply Current 12 mA TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = VIN = 3.63V or 2.625V IIL Input Low Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = VIN = 3.63V or 2.625V REVISION A 2/20/15 Test Conditions Minimum Typical Maximum Units VCC = 3.3V 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V 150 µA 3 -5 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER µA 843002I-01 DATA SHEET TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 22.4 25 27.2 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C Symbol fOUT tsk(o) Parameter Output Frequency Test Conditions Minimum Maximum Units F_SEL[1:0] = 00 140 Typical 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz 30 ps Output Skew; NOTE 1, 2 tjit(Ø) RMS Phase Jitter; NOTE 2, 3 tR / tF Output Rise/Fall Time 156.25MHz, (1.875MHz - 20MHz) 0.55 ps 125MHz, (1.875MHz - 20MHz) 0.60 ps 62.5MHz, (1.875MHz - 20MHz) 0.70 20% to 80% 350 odc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Measured using crystal input. ps 650 ps 52 % TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C Symbol fOUT tsk(o) tjit(Ø) Parameter Output Frequency Test Conditions Minimum Maximum Units F_SEL[1:0] = 00 140 Typical 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz 30 ps Output Skew; NOTE 1, 2 RMS Phase Jitter; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle 156.25MHz, (1.875MHz - 20MHz) 0.55 ps 125MHz, (1.875MHz - 20MHz) 0.60 ps 62.5MHz, (1.875MHz - 20MHz) 0.74 ps 20% to 80% 350 650 ps 48 52 % For Notes, see Table 5A above. FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 4 REVISION A 2/20/15 843002I-01 DATA SHEET TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V ➤ 0 -10 -20 10 Gigabit Ethernet Filter -30 dBc Hz -40 -50 156.25MHz -60 RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.55ps (typical) -70 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER -80 -120 -130 -140 -150 ➤ -160 -170 -180 -190 100 1k Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) REVISION A 2/20/15 5 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER OUTPUT RISE/FALL TIME FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 6 REVISION A 2/20/15 843002I-01 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V or 2.5V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The 843002I-01 has been character ized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF 843002I-01 FIGURE 2. CRYSTAL INPUT INTERFACE REVISION A 2/20/15 7 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. REF_CLK INPUT: For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3A. LVPECL OUTPUT TERMINATION FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER FIGURE 3B. LVPECL OUTPUT TERMINATION 8 REVISION A 2/20/15 843002I-01 DATA SHEET TERMINATION FOR 2.5V LVPECL OUTPUT ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to 2.5V 2.5V VCCO=2.5V Zo = 50 Ohm R1 250 2.5V VCCO=2.5V R3 250 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - 2,5V LVPECL Driv er R2 62.5 2,5V LVPECL Driv er R4 62.5 R1 50 R2 50 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE REVISION A 2/20/15 9 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET LAYOUT GUIDELINE parallel resonant 26.5625MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Figure 5A shows a schematic example of the 843002I-01. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF 3.3V VCC VCCA R2 10 C3 10uF Zo = 50 Ohm C4 0.01u VCCO RD1 Not Install 10 9 8 7 6 5 4 3 2 1 - R4 82.5 ICS843002i-01 R6 82.5 VCC=3.3V F_SEL1 XTAL_OUT XTAL_IN REF_CLK nXTAL_SEL VCC VEE nQ1 Q1 VCCO RU2 Not Install To Logic Input pins Zo = 50 Ohm U1 To Logic Input pins VCCO=3.3V Zo = 50 Ohm + 11 12 13 14 15 16 17 18 19 20 RU1 1K Set Logic Input to '0' VCC C7 0.1u VCC F_SEL0 VCCA nc nPLL_SEL MR nQ0 Q0 VCCO nc Set Logic Input to '1' VCC R5 133 + VCC C6 0.1u Logic Control Input Examples R3 133 RD2 1K Zo = 50 Ohm VCCO C8 0.1u C2 33pF X1 25 MHz 18pF C1 27pF R8 50 VCC R7 50 R9 50 C9 0.1u Optional Termination 843002I-01 FIGURE 5A. 843002I-01 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 5B shows an example of 843002I-01 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 C4, C5, C6, C7, C8 R2 0805 0603 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 5B. 843002I-01 PC BOARD LAYOUT EXAMPLE FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 10 REVISION A 2/20/15 843002I-01 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843002I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843002I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 130mA = 471.9mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.532W * 66.6°C/W = 120.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. REVISION A 2/20/15 11 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 12 REVISION A 2/20/15 843002I-01 DATA SHEET RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 843002I-01 is: 2955 REVISION A 2/20/15 13 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 14 REVISION A 2/20/15 843002I-01 DATA SHEET TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843002AGI-01LF ICS3002AI01L 20 Lead “Lead-Free” TSSOP tube -40°C to 85°C 843002AGI-01LFT ICS3002AI01L 20 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION A 2/20/15 15 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET REVISION HISTORY SHEET Rev A A Table T10 T10 Page 15 17 15 Description of Change Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Ordering Information - removed leaded devices, PDN CQ-13-02 Updated data sheet format FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 16 Date 12/14/10 2/20/15 REVISION A 2/20/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. 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