FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01
DATASHEET
GENERAL DESCRIPTION
FEATURES
The 843002-01 is a 2 output LVPECL synthesizer optimized
to generate Ethernet reference clock frequencies. Using a
25MHz 18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The 84300201 uses ICS’ 3rd generation low phase noise VCO technology
and can achieve 1ps or lower typical rms phase jitter, easily
meeting Ethernet jitter requirements. The 843002-01 is
packaged in a small 20-pin TSSOP package.
• Two 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies:
156.25MHz, 125MHz and 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.54ps (typical)
• Typical phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ................-97.3 dBc/Hz
1KHz ..............-119.1 dBc/Hz
10KHz ..............-126.4 dBc/Hz
100KHz ..............-127.6 dBc/Hz
• Full 3.3V supply mode
• Lead-Free package fully RoHS compliant
• -30°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
Inputs
N Divider
Value
F_SEL1
F_SEL0
0
0
25
4
156.25
0
1
25
5
125
1
0
25
10
62.5
1
1
Not Used
nc
VCCO
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
Output Frequency
(25MHz Ref.)
M Divider
Value
Not Used
nPLL_SEL
TEST_CLK
Pulldown
2
Pulldown
F_SEL[1:0]
Pulldown
1
1
25MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
20
19
18
17
16
15
14
13
12
11
VCCO
Q1
nQ1
VEE
VCC
nXTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
F_SEL1
843002-01
BLOCK DIAGRAM
F_SEL[1:0]
1
2
3
4
5
6
7
8
9
10
0
Phase
Detector
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
Q0
G Package
Top View
nQO
Q1
nQ1
VCO
625MHz
0
(w/25MHz
Reference)
Pulldown
M = 25 (fixed)
MR
Pulldown
843002-01 REVISION B 4/6/15
1
©2015 Integrated Device Technology, Inc.
843002-01 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 7
nc
Type
Unused
Description
No connect.
2, 20
VCCO
Power
Output supply pins.
3, 4
Q0, nQ0
Ouput
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
5
MR
Input
6
nPLL_SEL
Input
8
VCCA
Power
9, 11
F_SEL0,
F_SEL1
Input
10, 16
VCC
Power
Core supply pin.
12, 13
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
14
TEST_CLK
Input
Pulldown LVCMOS/LVTTL clock input.
15
nXTAL_SEL
Input
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
VEE
Power
18, 19
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
2, 20
VCCO
Power
Output supply pins.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Negative supply pins.
NOTE: refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pulldown
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
Test Conditions
2
Minimum
Typical
Maximum
Units
REVISION B 4/6/15
843002-01 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.97
3.3
3.63
V
VCCA
Analog Supply Voltage
2.97
3.3
3.63
V
VCCO
Output Supply Voltage
2.97
3.3
3.63
V
IEE
Power Supply Current
135
mA
ICC
Core Supply Current
100
mA
ICCA
Analog Supply Current
15
mA
ICCO
Output Supply Current
31
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
nPLL_SEL, nXTAL_SEL,
Input
F_SEL0, F_SEL1, MR
Low Voltage
TEST_CLK
VIL
Test Conditions
Minimum
IIH
Input
High Current
TEST_CLK, MR, nPLL_
SEL, nXTAL_SEL
VCC = VIN = 3.63V
IIL
Input
Low Current
TEST_CLK, MR, nPLL_
SEL, nXTAL_SEL
VCC = 3.63V, VIN = 0V
Maximum
Units
2
Typical
V + 0.3
V
-0.3
0.8
V
-0.3
1.0
V
150
µA
CC
-5
µA
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
Ω
REVISION B 4/6/15
3
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
22.4
25
27.2
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C
Symbol
fOUT
tsk(o)
Parameter
Output Frequency
Test Conditions
Minimum
Maximum
Units
F_SEL[1,:0] = 00
140
Typical
170
MHz
F_SEL[1,:0] = 01
112
136
MHz
F_SEL[1,:0] = 10
56
68
MHz
20
ps
Output Skew; NOTE 1, 2
tjit(Ø)
RMS Phase Jitter; NOTE 3
tR / tF
Output Rise/Fall Time
156.25MHz, (1.875MHz - 20MHz)
0.54
ps
125MHz, (1.875MHz - 20MHz)
0.60
ps
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.79
300
odc
Output Duty Cycle
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Phase jitter is dependent on the input source used.
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
4
ps
600
ps
51
%
REVISION B 4/6/15
843002-01 DATA SHEET
TYPICAL PHASE NOISE AT 62.5MHZ
➤
0
-10
-20
-30
10 Gigabit Ethernet Filter
-50
62.5MHz
-60
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.79ps (typical)
-70
-80
-90
-100
Raw Phase Noise Data
-110
-120
➤
NOISE POWER dBc
Hz
-40
-130
-140
-150
-160
-170
-180
➤
-190
100
1k
10k
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
➤
0
-10
-20
-30
10 Gigabit Ethernet Filter
-50
125MHz
-60
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.60ps (typical)
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
NOISE POWER dBc
Hz
-40
-120
-130
-140
-150
-160
-170
-180
➤
-190
100
1k
10k
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
100k
1M
10M
OFFSET FREQUENCY (HZ)
REVISION B 4/6/15
5
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
100M
843002-01 DATA SHEET
TYPICAL PHASE NOISE AT 156.25MHZ
➤
0
-10
-20
-30
10 Gigabit Ethernet Filter
-50
156.25MHz
-60
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.54ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-40
-120
-130
-140
-150
-160
➤
-170
-180
-190
100
1k
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
6
REVISION B 4/6/15
843002-01 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
REVISION B 4/6/15
7
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 843002-01 provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and
VCCO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2A. LVPECL OUTPUT TERMINATION
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
FIGURE 2B. LVPECL OUTPUT TERMINATION
8
REVISION B 4/6/15
843002-01 DATA SHEET
CRYSTAL INPUT INTERFACE
were determined using a 25MHz 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
The 843002-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below
Figure 3. CRYSTAL INPUt INTERFACE
REVISION B 4/6/15
9
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
LAYOUT GUIDELINE
pF parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.
Figure 4A shows a schematic example of the 843002-01. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18
VCC
Zo = 50 Ohm
VCCA
R2
10
C3
10uF
+
C4
0.01u
Zo = 50 Ohm
-
VCC
VCCO
C6
0.1u
Set Logic
Input to
'0'
VCC
RD1
Not Install
R5
50
ICS843002-01
VCC=3.3V
F_SEL1
XTAL_OUT
XTAL_IN
TEST_CLK
nXTAL_SEL
VCC
VEE
nQ1
Q1
VCCO
RU2
Not Install
To Logic
Input
pins
R6
50
U1
To Logic
Input
pins
VCCO=3.3V
Zo = 50 Ohm
+
11
12
13
14
15
16
17
18
19
20
RU1
1K
VCC
F_SEL0
VCCA
nc
nPLL_SEL
MR
nQ0
Q0
VCCO
nc
Set Logic
Input to
'1'
VCC
R4
50
C7
0.1u
10
9
8
7
6
5
4
3
2
1
Logic Control Input Examples
RD2
1K
Zo = 50 Ohm
VCCO
C8
0.1u
C2
33pF
X1
25 MHz
18pF
R8
50
VCC
R7
50
C1
27pF
R9
50
C9
0.1u
FIGURE 4A. 843002-01 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of 843002-01 P.C. board layout.
The crystal X1 footprint shown in this example allows installation
of either surface mount HC49S or through-hole HC49 package.
The footprints of other components in this example are listed in
the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
C4, C5, C6, C7, C8
R2
0805
0603
0603
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 4B. 843002-01 PC BOARD LAYOUT EXAMPLE
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
10
REVISION B 4/6/15
843002-01 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843002-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843002-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 135mA = 490mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 490mW + 60mW = 550mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.550W * 66.6°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION B 4/6/15
11
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCCO- 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
12
REVISION B 4/6/15
843002-01 DATA SHEET
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 843002-01 is: 2955
REVISION B 4/6/15
13
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
14
REVISION B 4/6/15
843002-01 DATA SHEET
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843002AG-01LF
ICS43002A01L
20 Lead “Lead-Free” TSSOP
tube
-30°C to 85°C
ICS843002AG-01LFT
ICS43002A01L
20 Lead “Lead-Free” TSSOP
tape & reel
-30°C to 85°C
NOTE: Parts that are ordered with an “LF” to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION B 4/6/15
15
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
T10
1
15
Added Lead-Free bullet in Features Section.
Added Lead-Free Part/Order Number in Ordering Information table.
1/5/05
A
T10
15
Added Lead-Free Marking to Ordering Information Table.
1/11/05
B
T5
4
AC Characteristics Table - delete Propagation Delay.
5/6/05
15
Ordering Information - removed leaded devices.
Updated datasheet format.
4/6/15
A
B
T10
FemtoClock® Crystal-to-3.3V LVPECL
Frequency Synthesizer
Description of Change
16
Date
REVISION B 4/6/15
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Sales
800-345-7015 or +408-284-8200
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www.IDT.com
Technical Support
email: clocks@idt.com
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this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
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(Rev.1.0 Mar 2020)
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