PRELIMINARY
ICS843002-31
FEMTOCLOCKS™ VCXO BASED
FREQUENCY TRANSLATOR/JITTER ATTENUATOR
GENERAL DESCRIPTION
FEATURES
The ICS843002-31 is a member of the
ICS
HiperClockS™ family of high performance clock
HiPerClockS™ solutions from IDT. This monolithic device is a highperfor mance, PLL-based synchronous clock
generator and jitter attenuation circuit. The
ICS843002-31 contains two clock multiplication stages that are
cascaded in series. The first stage is a VCXO-based PLL that
is optimized to provide reference clock jitter attenuation, to be
jitter tolerant, and to provide a stable reference clock for the
second multiplication stage. The second stage is the proprietary
IDT FemtoClock™circuit which is a high-frequency, subpicosecond clock multiplier.
• Outputs:
• Two high frequency differential LVPECL outputs
Output frequency: up to 700MHz
The VCXO PLL has an on-chip VCXO circuit that uses an
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
dividers suppor ting complex PLL multiplication ratios and
input reference clock rates as low as 2.3kHz. External loop
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter attenuation of a recovered data clock.
• FemtoClock frequency multiplier supports rate of:
560MHz - 700MHz
The FemtoClock circuit can multiply the VCXO crystal frequency
by a factor of 28 or 32 (selectable) and provide a clock output of
up to 700MHz.
• 3.3V supply voltage
• One LVCMOS/LVTTL VCXO PLL output with output enable
• One Reference clock output with output enable
• One LOCK detect output
• Input mux supports 3 selectable inputs: one differential input
pair and two LVCMOS/LVTTL input clocks
• 13-bit VCXO PLL feedback and reference dividers provide
wide range of frequency translation ratio options
• ‘Lock Detect’ output reports lock status of VCXO PLL
• VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below (user adjustable)
• RMS phase jitter, random at 12kHz to 20MHz:
1 1
13
QA ÷1
QA ÷2
QA ÷4
QA ÷8
XOIN Output
OFB Output
MP Output
Disabled
Drive Low
QB
nQB
MP
REF_CLK
OE_REF
LOCK
LOCK Detect
NOTE 1: For application configuration (non-test/bypass modes).
NOTE 2: Bold lines
are primary clock paths (non-control/non-feedback lines).
Not all control lines and signal paths are shown in this simplified block diagram.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
2
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
SIMPLIFIED BLOCK DIAGRAM - CLOCK SIGNAL PATHS
External Loop
Filter Connection
17.5 - 25MHz
CLK1
QA Output
Divider NPA[2:0]
XTAL_IN
XTAL_OUT
01
VCXO PLL
VCLK
÷1
÷12
÷16
Disabled Drive Low
LF0 LF1
Input Divider
XOIN[12:0]
÷1 to ÷8191
CLK2
00:
01:
10:
11:
1 1 Bypass
nCLK0
BYPASS MODE
VCXO PLL Output
Divider NV[1:0]
ISET
Charge Pump
Current
CLK0
IN
PRELIMINARY
FemtoClock™
Frequency
Multiplier
NPA[2:0]
000: ÷1
001: ÷2
010: ÷4
011: ÷8
100: ÷12
101: ÷14
110: ÷16
111: Disabled Drive Low
QA
nQA
10
000: ÷1
001: ÷2
010: ÷4
QB
nQB
011: ÷8
111: Disabled
FemtoClock™
Feedback Divider
VCXO PLL
Feedback Divider
XOFB[12:0]
÷1 to ÷8191
MP
0: ÷32
1: ÷28
110: MP
101: XOFB
100: XOIN
NPB2
NPB1
NPB0
NOTE 1: Setting SEL1:SEL0 = 11 enables bypass mode.
Only clock signals on the CLK0/nCLK0 input pair are routed
to the device in bypass mode.
NOTE 2: Bold lines
show clock bypass paths.
Not all control lines and signal paths are shown in this
simplified block diagram.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
3
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT PAGE)
Number
Name
Type
Analog
Input/Output
Analog
Input/Output
Power
1, 2
LF1, LF0
3
ISET
4, 41, 48
VEE
5, 6
NV1, NV0
Input
7, 13
VCC
Power
8
MR
Input
9
CLK0
Input
10
nCLK0
Input
11
OE_REF
Input
12
CLK1
Input
Pullup/ Inver ting differential clock input.
Pulldown VCC/2 bias voltage when left floating.
Output enable control for reference clock output. When logic LOW,
Pulldown the reference clock output is in high impedance. When logic HIGH,
the output is enabled. LVCMOS/LVTTL interface levels.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
1 4, 1 5
SEL1, SEL0
Input
Pulldown Input clock select. LVCMOS/LVTTL interface levels.
16
17, 18,
19, 20,
21, 22,
23, 24,
25, 26,
27, 28
CLK2
Input
Pulldown Clock input. LVCMOS/LVTTL interface levels.
XOIN12:XOIN1
Input
Pulldown
29
XOIN0
Input
30, 31,
32
33
34, 35,
36
NPA2, NPA1,
NPA0
VCCA
NPB2, NPB1,
NPB0
Power
37
MP
Input
38,
VCCO_PECL
Power
Input
Input
Description
Loop filter connection pins.
Charge pump current setting pin.
Negative supply pins. Normally connected to ground.
VCXO PLL output divider control pins.
Pullup
LVCMOS/LVTTL interface levels.
Core power supply pins.
Master Reset. When HIGH, resets all internal dividers and
Pulldown LVCMOS outputs are in high impedance.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
VCXO PLL input divider control input.
LVCMOS/LVTTL interface levels.
VCXO PLL input divider control input.
LVCMOS/LVTTL interface levels.
LVPECL output divider control for QA/nQA outputs.
Pulldown
LVCMOS/LVTTL interface levels.
Analog supply pin.
LVPECL output divider control for QB/nQB outputs.
Pulldown
LVCMOS/LVTTL interface levels.
FemtoClock™ circuit clock multiplication control input.
Pulldown When HIGH, selects 28. When LOW, selects 32.
LVCMOS/LVTTL interface levels.
Output power supply pin for LVPECL clock outputs.
Pullup
39, 40
QA, nQA
Output
Differential clock output pair. LVPECL interface levels.
42, 43
QB, nQB
Output
Differential clock output pair. LVPECL interface levels.
44
VCCO_CMOS
Power
Output power supply pin for LVCMOS outputs.
45
LOCK
Output
Lock detect output. LVCMOS/LVTTL interface levels.
46
VCLK
Output
VCXO PLL clock output. LVCMOS/LVTTL interface levels.
47
REF_CLK
Output
Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
4
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED FROM PREVIOUS PAGE)
Number
49, 50,
51, 52,
53, 54,
55, 56,
57, 58,
59. 60
Name
Type
Description
XOFB12:XOFB1
Input
Pulldown
61
XOFB0
Input
Pullup
62, 63
XTAL_OUT,
XTAL_IN
Input
64
VCCA_XO
Power
VCXO feedback divider control input.
LVCMOS/LVTTL interface levels.
VCXO feedback divider control input.
LVCMOS/LVTTL interface levels.
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Analog power supply pin for VCXO.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per LVCMOS output)
Test Conditions
VCC, VCCA, VCCA_XO, VCCO_CMOS,
VCCO_PECL = 3.465V
Minimum Typical
Maximum
Units
4
pF
TBD
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
7
Ω
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
5
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
SECTION 1. FREQUENCY TRANSLATION
➥ Set the QB/nQB output divider control pins,
NPB[2:0] = 010 for divide by 4. This sets the QB/nQB
LVPECL output pair for 155.52MHz.
The ICS843002-31 is a two stage device, a VCXO PLL stage
followed by a low phase noise FemtoClock multiplier stage. The
VCXO uses a pullable crystal to lock to the reference clock and
can provide an output frequency up to 25MHz on the singleended VCLK output. For higher frequencies, the low phase noise
FemtoClock can multiply the VCXO PLL output clock up to
700MHz on 2 differential LVPECL output pairs (QA/nQA, QB/
nQB).
2. T1 to T3. (1.544MHz to two 44.736MHz outputs)
Since 44.736MHz is slightly higher than the maximum VCXO
output frequency, the FemtoClock circuit will have to be used.
➥ Using a pullable 22.368MHz on XTAL_IN/XTAL_OUT,
set the VCXO PLL feedback divider pins, XOFB[12:0]
to 2796 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 22.368MHz
(1.544MHz * 2796/193 = 22.368MHz).
The VCXO PLL stage has a 13-bit input divider and a 13-bit
feedback divider to generate large integer ratios needed for
some frequency translation applications. When configuring
the device is to use pullable crystals in the 17.5MHz – 25MHz
range on the VCXO PLL stage, and ensure that the
FemtoClock PLL is kept within its range of 560MHz to 700MHz.
➥ Set the FemtoClock multiplication control pin, MP, to
28 which sets the VCO at 626.304MHz.
➥ Set the QA/nQA output divider control pins,
NPA[2:0] = 101 for divide by 14. This sets the QA/nQA
LVPECL output pair for 44.736MHz.
Below are 3 examples:
1. 8kHz to 622.08MHz and 155.52MHz
➥ Set the QB/nQB output divider control pins,
NPB[2:0] = 000 for divide by 1. This sets the QB/nQB
LVPECL output pair for 44.736MHz
This frequency translation requires use of both the VCXO PLL
and the FemtoClock circuit. The VCXO PLL can be used to
multiply up to 19.44MHz for use as a reference clock for the
FemtoClock which will do the multiplication from 19.44MHz to
622.08MHz.
3. T1 to E1. (1.544MHz to two 2.048MHz outputs)
The 2.048MHz output frequency requirement is low enough
that the FemtoClock circuit is not required. Only the VCXO stage
is used for this frequency translation.
➥ Using a 19.44MHz pullable crystal on XTAL_IN/
XTAL_OUT, set the VCXO PLL feedback divider pins,
XOFB[12:0], to 2430. This multiplies the 8kHz reference clock to 19.44MHz.
➥ Using a pullable 24.576MHz on XTAL_IN/XTAL_OUT,
set the VCXO PLL feedback divider pins, XOFB[12:0]
to 3072 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 2.048MHz
(1.544MHz * 3072/193 = 24.576MHz).
➥ Set the FemtoClock multiplication control pin, MP, to
0 which sets the multiplication factor to 32. This sets
the FemtoClock VCO to 622.08MHz.
➥ Set the QA/nQA output divider control pins,
NPA[2:0] = 000 for divide by 1. This sets the QA/nQA
LVPECL output pair for 622.08MHz.
➥ Set the VCXO PLL Output Divider control pins,
NV[1:0] = 01 for /12. This divides the 24.576MHz VCXO
PLL frequency down to 2.048MHz.
SECTION 2. FREQUENCY CONFIGURATION
The Frequency Configuration Table Examples (see the following
pages) are intended to show the most common frequency
translation requirements. It is sorted in order of descending
input frequency. It is not intended to be an exhaustive configuration table because that would be impractical with almost 3
billion possible configurations. As far as configuration is
concerned, frequencies 25MHz require the use of the
downstream FemtoClock which can multiply the VCXO PLL
output up to 700MHz. Complex integer ratios are handled with
the VCXO PLL stage and the FemtoClock circuit can be
configured to multiply the VCXO PLL output by 32 or 28. The
following example will illustrate the configuration process.
this means there are 2 viable VCXO PLL crystal choices which
fall within its 17.5MHz – 15MHz range: 22.217143MHz (/28
feedback divider) or 19.44MHz (/32 feedback divider). Use of
the /28 feedback divider for the FemtoClock multiplier will give
slightly better phase noise, but in this case 22.217143/1.544
cannot be exactly achieved with the 13-bit input and feedback
VCXO PLL dividers. Using the x32 setting of the FemtoClock
allows a ratio of 19.44/1.544 = 2430/193 which is easily
achievable. So the FemtoClock would be set for x32 and a
19.44MHz crystal would be used. The VCXO PLL input divider
would be set for 193 and the VCXO PLL feedback divider would
be set for 2430. To double check the solution, perform the
following calculation: 1.544 * 2430 * 32/193 = 622.08MHz.
Assume you have a 1.544MHz T1 clock which needs to be
multiplied up to 622.08MHz (OC12). Obviously, the FemtoClock
multiplier will be needed to achieve 622.08MHz. Since the
FemtoClock has a selectable multiplication factor of 28 or 32,
The 2nd FemtoClock multiplier output, QB/nQB, can be set to equal
the QA/nQA output frequency or a fraction of its frequency. The
following fractional values are available: /1, /2, /4, /8.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
6
ICS843002CY-31 REV. C MAY 16, 2007
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
7
311.04
155.52
77.76
311.04
311.04
311.04
34.368
32.064
2.048
1.544
155.52
77.76
51.84
38.88
19.44
311.04
311.04
311.04
311.04
155.52
155.52
155.52
155.52
155.52
155.52
FemtoClock Output
VCXO Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
FemtoClock Output
44.736
311.04
311.04
19.44
19.44
19.44
19.44
19.44
19.44
8
8
8
8
8
8
2430
405
24.704
1620
32.064
1620
3240
16
24.576
34.368
22.368
19.44
16
16
16
19.44
16
16
19.44
FemtoClock Output
16
16
19.44
19.44
19.44
19.44
4860
24.704
3240
3240
405
19.44
622.08
32
6480
24.576
32.064
34.368
VCXO Output
311.04
19.44
22.368
32
32
19.44
19.44
32
32
32
32
VCXO
Input
Divider
19.44
19.44
19.44
19.44
Required VCXO
Crystal Frequency
(MHz)
FemtoClock Output
19.44
622.08
311.04
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
311.04
38.88
1.544
622.08
311.04
2.048
51.84
32.064
622.08
622.08
311.04
34.368
622.08
VCXO Output
19.44
38.88
44.736
51.84
622.08
622.08
622.08
77.76
622.08
622.08
FemtoClock Output
155.52
622.08
FemtoClock Output
FemtoClock Output
622.08
311.04
622.08
VCXO or
FemtoClock Output
622.08
Output
Frequency
(MHz)
Input
Frequency
(MHz)
1
1
1
1
1
1
193
32
167
179
233
1
1
1
1
1
1
1
1
193
16
167
179
233
1
1
1
1
1
1
1
VCXO
Feedback
Divider
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES, CONTINUED ON NEXT PAGE
N/A
32
N /A
32
32
32
32
N/A
N/A
N/A
N/A
28
32
32
N/A
32
32
32
32
32
N/A
N/A
N/A
N/A
28
N/A
32
32
32
32
32
32
FemtoClock
™
Multiplication
Factor
1
N/A
N/A
N/A
N/A
16
12
1
1
1
1
1
1
N/A
N/ A
N/A
N/A
N/A
16
12
1
1
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
VCXO
Output
Divider
16
622.08
2
N/A
622.08
N/A
12
8
4
N/A
N/ A
N/A
N/A
14
1
1
N/ A
16
12
8
4
2
N/A
622.08
622.08
622.08
N/A
N/A
N/ A
N/A
626.304
622.08
622.08
N/A
622.08
622.08
622.08
622.08
622.08
N/A
N/A
N/A
N /A
N/A
N/A
14
N/A
16
12
8
4
2
1
FemtoClock
Output
Divider
N/A
626.304
N/A
622.08
622.08
622.08
622.08
622.08
622.08
FemtoClock
Output Frequency
(MHz)
155.52 -> 311.04 (SONET)
155.52 -> 19.44 (SONET)
155.52 -> 38.88 (SONET)
155.52 -> 51.84 (OC3 to OC1)
155.52 -> 77.76 (SONET)
155.52 -> 155.52 (OC3)
311.04 -> 1.544 (SONET to T1/J1)
311.04 -> 2.048 (SONET to E1)
311.04 -> 32.064 (SONET to J3)
311.04 -> 34.368 (SONET to E3)
311.04 -> 44.736 (SONET to T3)
311.04 -> 622.08 (SONET)
311.04 -> 622.08 (SONET)
311.04 -> 19.44 (SONET)
311.04 -> 38.88 (SONET)
311.04 -> 51.84 (SONET)
311.04 -> 77.76 (SONET)
311.04 -> 155.52 (SONET)
311.04 -> 311.04 (SONET)
622.08 -> 1.544 (OC12 to T1/J1)
622.08 -> 2.048 (OC12 to E1)
622.08 -> 32.064 (OC12 to J3)
622.08 -> 34.368 (OC12 to E3)
622.08-> 44.736 (OC12 to T3)
622.08 -> 19.44 (SONET)
622.08 -> 38.88 (SONET)
622.08 -> 51.84 (OC12 to OC1)
622.08 -> 77.76 (SONET)
622.08 -> 155.52 (OC12 to OC3)
622.08 -> 311.04 (SONET)
622.08 -> 622.08 (OC12)
Application
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
ICS843002CY-31 REV. C MAY 16, 2007
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
8
2.048
1.544
51.84
38.88
19.44
77.76
51.84
51.84
51.84
VCXO Output
VCXO Output
311.04
622.08
44.736
34.368
32.064
2.048
1.544
44.736
51.84
51.84
51.84
51.84
51.84
51.84
51.84
44.736
FemtoClock Output
VCXO Output
VCXO Output
FemtoClock Output
22.368
24.704
24.576
32.064
34.368
22.368
19.44
19.44
FemtoClock Output
19.44
19.44
19.44
19.44
19.44
24.704
24.576
32.064
34.368
22.368
19.44
19.44
19.44
19.44
19.44
19.44
19.44
2
405
135
270
270
540
8
8
8
8
8
8
8
1215
405
405
405
810
4
4
4
4
4
4
4
1215
405
24.576
24.704
810
810
1620
8
VCXO
Input
Divider
32.064
34.368
22.368
19.44
Required VCXO
Crystal Frequency
(MHz)
FemtoClock Output
FemtoClock Output
51.84
FemtoClock Output
77.76
155.52
51.84
VCXO Output
FemtoClock Output
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
32.064
77.76
77.76
FemtoClock Output
VCXO Output
44.736
77.76
FemtoClock Output
FemtoClock Output
FemtoClock Output
VCXO Output
34.368
622.08
77.76
FemtoClock Output
FemtoClock Output
77.76
155.52
311.04
77.76
19.44
77.76
77.76
51.84
38.88
77.76
77.76
VCXO Output
FemtoClock Output
1.544
77.76
VCXO Output
77.76
2.048
155.52
VCXO Output
VCXO Output
FemtoClock Output
FemtoClock Output
VCXO or
FemtoClock Output
155.52
34.368
32.064
44.736
155.52
155.52
622.08
155.52
155.52
Output
Frequency
(MHz)
Input
Frequency
(MHz)
1
193
64
167
179
233
3
3
3
3
3
3
3
386
128
167
1
16
12
1
1
N/A
N/ A
N/A
28
N/A
N/A
N/A
N/A
28
32
32
32
32
N/A
N/A
32
32
N/A
N/ A
N/A
N/A
28
32
32
32
N/A
32
32
32
N/A
N/ A
N/A
N/A
28
32
FemtoClock
™
Multiplication
Factor
N /A
1
N/A
N/A
16
12
1
1
N/A
233
179
N/A
N/A
N/A
1
N/A
N/A
N/A
16
12
1
1
N/A
N/A
VCXO
Output
Divider
1
1
1
1
1
1
1
193
64
167
179
233
1
VCXO
Feedback
Divider
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES, CONTINUED ON NEXT PAGE
14
N/A
N/A
626.304
N/ A
N/ A
N/ A
14
1
2
4
8
N/ A
16
12
N/ A
N/ A
N/ A
N/A
14
1
2
4
N/A
16
12
8
N/A
N/A
44.736 -> 44.736 (T3)
51.84 -> 1.544 (OC1 to T1/J1)
51.84 -> 2.048 (OC1 to E1)
51.84 -> 32.064 (OC1 to J3)
51.84 -> 34.368 (OC1 to E3)
51.84 -> 44.736 (OC1 to T3)
51.84 -> 622.08 (OC1 to OC12)
51.84 -> 311.04 (SONET)
51.84 -> 155.52 (OC1 to OC3)
51.84 -> 77.76 (SONET)
51.84 -> 19.44 (SONET)
51.84 -> 38.88 (SONET)
51.84 -> 51.84 (SONET)
77.76 -> 1.544 (SONET to T1/E1)
77.76 -> 2.048 (SONET to E1)
77.76 -> 32.064 (SONET to J3)
77.76 -> 34.368 (SONET to E3)
77.76 -> 44.736 (SONET to T3)
77.76 -> 622.08 (SONET)
77.76 -> 311.04 (SONET)
77.76 -> 155.52 (SONET)
77.76 -> 19.44 (SONET)
77.76 -> 38.88 (SONET)
77.76 -> 51.84 (SONET)
77.76 -> 77.76 (SONET)
155.52 -> 1.544 (OC3 to T1/J1)
155.52 -> 2.048 (OC3 to E1)
155.52 -> 32.064 (OC3 to J3)
155.52 -> 34.368 (OC3 to E3)
N/A
N/A
155.52 -> 44.736 (OC3 to T3)
155.52 -> 622.08 (OC3 to OC12)
Application
14
1
FemtoClock
Output
Divider
N/A
N/A
N/A
626.304
622.08
622.08
622.08
622.08
N/A
622.08
622.08
N/A
N/A
N/A
N/A
626.304
622.08
622.08
622.08
N/A
622.08
622.08
622.08
N/A
N/A
N/A
N/A
626.304
622.08
FemtoClock
Output
Frequency
(MHz)
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
ICS843002CY-31 REV. C MAY 16, 2007
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR
9
VCXO Output
VCXO Output
44.736
34.368
32.064
2.048
38.88
38.88
38.88
VCXO Output
VCXO Output
44.736
32.064
19.44
2.048
1.544
32.064
34.368
44.736
34.368
34.368
34.368
34.368
34.368
32.064
32.064
32.064
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
FemtoClock Output
VCXO Output
1.544
34.368
38.88
34.368
VCXO Output
VCXO Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
38.88
FemtoClock Output
FemtoClock Output
622.08
77.76
38.88
VCXO Output
311.04
19.44
38.88
FemtoClock Output
FemtoClock Output
38.88
38.88
38.88
38.88
622.08
44.736
FemtoClock Output
155.52
311.04
44.736
FemtoClock Output
22.368
34.368
32.064
24.704
24.576
19.44
334
167
1
537
179
71 6
179
358
22.368
32.064
1
1215
405
405
405
405
2
2
2
2
2
2
233
179
1
386
128
405
167
233
1
772
256
334
358
233
1
1
1
1
1
1
405
405
932
932
405
405
405
405
179
167
405
128
386
VCXO
Feedback
Divider
932
932
932
932
233
233
932
233
699
VCXO
Input
Divider
34.368
24.704
24.576
32.064
34.368
22.368
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
19.44
FemtoClock Output
FemtoClock Output
19.44
34.368
32.064
19.44
24.576
24.704
Required VCXO
Crystal Frequency
(MHz)
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
VCXO or
FemtoClock Output
38.88
77.76
51.84
44.736
155.52
38.88
44.736
34.368
44.736
44.736
44.736
19.44
32.064
2.048
44.736
44.736
1.544
44.736
44.736
Output
Frequency
(MHz)
Input
Frequency
(MHz)
N/A
1
1
16
12
1
1
N/A
1
16
12
1
1
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
12
16
VCXO
Output
Divider
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES, CONTINUED ON NEXT PAGE
28
N/A
N/A
N/A
N/A
N/A
N/A
28
N/A
N/A
N/A
N/A
N/A
28
N/A
14
N/A
N/A
N/A
N/A
N/A
N/A
14
N/A
N/A
N/A
N/A
N/A
14
1
2
4
8
N/A
16
1
2
4
8
12
16
N/A
N/A
N/A
N/A
N/A
FemtoClock
Output
Divider
626.304
N/A
N/A
N/A
N/A
N/A
626.304
N/A
N/A
N/A
N/A
N/A
626.304
622.08
622.08
32
622.08
622.08
N/ A
622.08
622.08
622.08
622.08
622.08
622.08
622.08
N/ A
N/ A
N/ A
N/A
N/A
FemtoClock
Output
Frequency
(MHz)
32
32
32
N/A
32
32
32
32
32
32
32
N/A
N/A
N/A
N/A
N/A
FemtoClock
™
Multiplication
Factor
32.064 -> 44.736 (J3 to T3)
32.064 -> 34.368 (J3 to E3)
32.064 -> 32.064 (J3)
34.368 -> 1.544 (E3 to T1)
34.368 -> 2.048 (E3 to E1)
34.368 -> 19.44 (E3 to SONET)
34.368 -> 32.064 (E3 to J3)
34.368 > 44.736 (E3 to T3)
34.368 -> 34.368 (E3)
38.88 ->1.544 (SONET to DS1/J1)
38.88 -> 2.048 (SONET to E1)
38.88 -> 32.064 (SONET TO J3)
38.88 -> 34.368 (SONET to E3)
38.88 -> 44.736 (SONET to T3)
38.88 -> 622.08 (SONET to OC12)
38.88 -> 311.04 (SONET)
38.88 -> 155.52 (SONET to OC3)
38.88 -> 77.76 (SONET)
38.88 -> 19.44 (SONET)
38.88 -> 38.88 (SONET)
44.736 -> 622.08 (T3 to OC12)
44.736 -> 311.04 (T3 to SONET)
44.736 -> 155.52 (T3 to OC3)
44.736 -> 77.76 (T3 to SONET)
44.736 -> 51.84 (T3 to OC1)
44.736 -> 38.88 (T3 to SONET)
44.736 -> 34.368 (T3 to E3)
44.736 -> 32.064 (T3 to J3)
44.736 -> 19.44 (T3 to SONET)
44.736 -> 2.048 (T3 to E1)
44.736 -> 1.544 (T3 to T1/J1)
Application
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
ICS843002CY-31 REV. C MAY 16, 2007
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 10
2.048
2.048
2.048
32.064
34.368
44.736
1.544
2.048
19.44
32.064
1.544
1.544
1.544
1.544
0.008
0.008
0.008
0.008
1.544
672.1627119
1.544
669.3265823
19.44
19.44
44.736
666.5142857
19.44
32.064
1.544
19.44
2.048
2.048
19.44
2.048
32.064
19.44
1.544
34.368
19.44
34.368
44.736
19.44
2.048
FemtoClock Output
622.08
19.44
2.048
FemtoClock Output
311.04
19.44
VCXO Output
VCXO Output
VCXO Output
VCXO Output
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
FemtoClock Output
VCXO Output
VCXO Output
32.064
19.44
24.576
24.704
22.368
34.368
32.064
24.576
24.704
22.368
32.064
34.368
24.704
24.576
VCXO Output
VCXO Output
21.00508475
20.9164557
20.82857143
24.704
24.576
32.064
34.368
22.368
19.44
19.44
19.44
19.44
19.44
19.44
19.44
24.704
24.576
Required VCXO
Crystal
Frequency
(MHz)
FemtoClock Output
VCXO Output
VCXO Output
VCXO Output
VCXO Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
77.76
155.52
FemtoClock Output
19.44
51.84
19.44
VCXO Output
FemtoClock Output
19.44
19.44
38.88
19.44
VCXO Output
1.544
32.064
19.44
VCXO Output
2.048
32.064
VCXO or
FemtoClock
Output
Output
Frequency
(MHz)
Input
Frequency
(MHz)
1
1
1
1
193
193
193
193
1
64
32
32
16
1
236
79
14
1215
405
405
405
405
1
1
1
1
1
1
1
501
167
VCXO
Input
Divider
4008
2430
3072
3088
2796
4296
4008
3072
16
699
501
537
193
12
255
85
15
1544
512
668
716
466
1
1
1
1
1
1
1
386
128
VCXO
Feedback
Divider
1
1
12
16
N/A
1
1
12
16
N/A
1
1
16
12
N/A
N/A
N/A
16
12
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
16
12
VCXO
Output
Divider
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES, CONTINUED ON NEXT PAGE
N/A
N/A
N/A
N/A
28
N/A
N/A
N/A
N/A
28
N/A
N/A
N/A
N/A
32
32
32
N/A
N/A
N/A
N/A
28
32
32
32
32
32
32
N/A
N/A
N/A
FemtoClock
™
Multiplication
Factor
N/A
N/A
N/A
N/A
626.304
N/A
N/A
N/A
N/A
626.304
N/A
N/A
N/A
N/A
672.1627119
669.3265823
666.5142857
N/A
N/A
N/A
N/A
626.304
622.08
622.08
622.08
622.08
622.08
622.08
N/A
N/A
N/A
FemtoClock
Output
Frequency
(MHz)
N/A
N/A
N/ A
N/A
14
N/A
N/A
N/A
N/A
14
N/A
N/A
N/A
N/A
1
1
1
N/A
N/A
N/A
N/A
14
1
2
4
8
12
16
N/A
N/A
N/A
FemtoClock
Output
Divider
8KHz -> 32.064MHz (Frame Clock to J3)
8KHz -> 19.44MHz (Frame Clock to SONET)
8KHz -> 2.048MHz (Frame Clock to E1)
8KHz -> 1.544MHz (Frame Clock to T1)
1.544 -> 44.736 (T1/J1 to T3)
1.544 -> 34.368 (T1/J1 to E3)
1.544 -> 32.064 (T1/J1 to J3)
1.544 -> 2.048 (T1 to E1)
1.544 -> 1.54 (T1/J1)
2.048 -> 44.736 (E1 to T3)
2.048 -> 32.064 (E1 to J3)
2.048 -> 34.368 (E1 to E3)
2.048 -> 1.544 (E1 toT1/J1)
2.048 -> 2.048 (E1)
19.44 -> 672.1627119 (255/236 FEC)
19.44 -> 669.3265823 (255/237 FEC)
19.44 -> 666.5142857 (255/238 FEC)
19.44 -> 1.544 (SONET to T1/J1)
19.44 -> 2.048 (SONET to E1)
19.44 -> 32.064 (SONET to J3)
19.44 -> 34.368 (SONET to E3)
19.44 -> 44.736 (SONET to T3)
19.44 -> 622.08 (SONET to OC12)
19.44 -> 311.04 (SONET)
19.44 -> 155.52 (SONET to OC3)
19.44 -> 77.76 (SONET)
19.44 -> 51.84 (SONET to OC1)
19.44 -> 38.88 (SONET)
19.44 -> 19.44 (SONET)
32.064 -> 1.544 (J3 to T1)
32.064 -> 2.048 (J3 to E1)
Application
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
ICS843002CY-31 REV. C MAY 16, 2007
155.52
311.04
622.08
0.008
0.008
0.008
38.88
77.76
44.736
0.008
0.008
34.368
0.008
0.008
Output
Frequency
(MHz)
Input
Frequency
(MHz)
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
FemtoClock Output
VCXO Output
VCXO or
FemtoClock
Output
19.44
19.44
19.44
19.44
19.44
22.368
34.368
Required VCXO
Crystal
Frequency
(MHz)
TABLE 3A. FREQUENCY CONFIGURATION EXAMPLES
1
1
1
1
1
1
1
VCXO
Input
Divider
2430
2430
2430
2430
2430
2796
4296
VCXO
Feedback
Divider
N/ A
N/A
N/ A
N/A
N/ A
1
1
VCXO
Output
Divider
32
32
32
32
32
28
N/A
FemtoClock
™
Multiplication
Factor
622.08
622.08
622.08
622.08
622.08
626.304
N/A
FemtoClock
Output
Frequency
(MHz)
1
2
4
8
16
14
N/A
FemtoClock
Output
Divider
8KHz -> 622.08MHz (Frame Clock to OC12)
8KHz -> 311.04MHz (Frame Clock to SONET)
8KHz ->155.52MHz (Frame Clock to OC3)
8KHz -> 77.76MHz (Frame Clock to SONET)
8KHz -> 38.88MHz (Frame Clock to SONET)
8KHz -> 44.736MHz (Frame Clock to T3)
8KHz -> 34.368MHz (Frame Clock to E3)
Application
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 11
PRELIMINARY
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VCC + 0.5V
Maximum Ratings may cause permanent damage to the
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
Outputs, IO (LVPECL)
Continuous Current
Surge Current
those listed in the DC Characteristics or AC Characteristics is not
50mA
100mA
implied. Exposure to absolute maximum rating conditions for ex-
Package Thermal Impedance, θJA 22.3°C/W (0 lfpm)
Storage Temperature, TSTG
tended periods may affect product reliability.
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA, VCCA_XO
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO_CMOS,
VCCO_PECL
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
395
mA
ICCA
Analog Supply Current
15
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
MP, MR, OE_REF, SEL0, SEL1,
XOIN[12:1], NPA[2:0], NPB[2:0],
Input
High Current CLK1, CLK2, XOFB[12:1]
NV0, NV1, XOIN0, XOFB0
MP, MR, OE_REF, SEL0, SEL1,
XOIN[12:1], NPA[2:0], NPB[2:0],
Input
CLK1, CLK2, XOFB[12:1]
Low Current
NV0, NV1, XOIN0, XOFB0
IIH
IIL
Test Conditions
VOH
Output
High Voltage
REF_CLK, VCLK, LOCK;
NOTE 1
VOL
Output
Low Voltage
REF_CLK, VCLK, LOCK;
NOTE 1
Minimum
Maximum
Units
2
Typical
VCC + 0.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
VCC = 3.465V,
VIN = 0V
-5
µA
VCC = 3.465V,
VIN = 0V
-150
µA
2.6
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO_CMOS/2.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 12
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
Minimum
Typical
Maximum
Units
CLK0
VIN = VCC = 3.465V
150
µA
nCLK0
VIN = VCC = 3.465V
5
µA
CLK0
VIN = 0V, VCC = 3.465V
-150
µA
nCLK0
VIN = 0V, VCC = 3.465V
-5
µA
0.15
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VCC + 0.3V.
1.3
V
VCC - 0.85
V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_PECL = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
NOTE 1: Outputs terminated with 50 Ω to VCCO_PECL - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit".
V
V
TABLE 5. CRYSTAL CHARACTERISTICS
Symbol
Parameter
fN
Nominal Frequency
Test Conditions
Minimum
Typical
Maximum
19.44
Units
MHz
fT
Frequency Tolerance
±TBD
ppm
fS
Frequency Stability
±TBD
ppm
CL
Load Capacitance
Operating Temperature Range
CO
Shunt Capacitance
CO/C1
Pullability Ratio
ESR
Equivalent Series Resistance
0
70
12
4
220
Drive Level
Mode of Operation
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 13
°C
pF
pF
240
50
Ω
1
mW
Fundamental
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCA_XO = VCCO_CMOS = VCCO_PECL = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Maximum
Units
35
700
MHz
QB/nQB
4.375
700
MHz
VCLK
1.1875
25
MHz
200
MHz
QA/nQA
fOUT
Output Frequency
Minimum
Typical
REF_CLK
OC-48 mask (12kHz - 20MHz)
19.44MHz input, into CLK0
622.08MHz output;
NOTE 1, 2
OC-12 mask (250kHz - 5MHz)
19.44MHz input, into CLK0
155.52MHz output;
NOTE 1, 3
t(J)
Timing Jitter
OC-48 mask (12kHz - 20MHz)
8kHz input, into CLK2
622.08MHz output;
NOTE 1, 2
OC-12 mask (250kHz - 5MHz)
8kHz input, into CLK2
155.52MHz output;
NOTE 1, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Random jitter
1.3
ps
Deterministic jitter
0.75
ps
Total jitter
Random jitter
Deterministic jitter
Total jitter
Random jitter
Deterministic jitter
1.5
ps
3.5
mUI
1
ps
0.5
ps
1.1
ps
0.7
mUI
1
ps
0.3
ps
1.1
ps
2.7
mUI
Random jitter
0.9
ps
Deterministic jitter
0.19
ps
0.9
ps
Total jitter
Total jitter
20% to 80%
0.6
200
mUI
700
QA/QB @ 622.08MHz
50
VCLK, REF_CLK @ 19.44MHz
50
PLL Lock Time
100
tLOCK
See Parameter Measurement Information section.
NOTE 1: External crystal is 19.44MHz Eliptek ECX-5451.
NOTE 2: Loop bandwidth (-3dB) = 180Hz; Loop Damping Factor = 5.3 (see Applications Section, Example Loop Filter Component Value,
example case #4).
NOTE 3: Loop bandwidth (-3dB) = 19Hz; Loop Damping Factor = 2.8 (see Applications Section, Example Loop Filter Component Value
example case #2).
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 14
ps
%
%
ms
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
1.65V ± 5%
VCC,
VCCA,
VCCA_XO,
VCCO_PECL
Qx
SCOPE
LVPECL
nQx
SCOPE
VCC,
VCCA,
VCCA_XO,
VCCO_CMOS
LVCMOS
Qx
GND
VEE
-1.65V ± 5%
-1.3V ± 0.165V
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
nQA
V
DDO
VCLK
QA
2
nQB
V
DDO
REF_CLK
QB
2
tsk(o)
tsk(o)
LVPECL OUTPUT SKEW
80%
LVCMOS OUTPUT SKEW
80%
80%
80%
tR
tF
VSW I N G
Clock
Outputs
20%
20%
tR
tF
LVPECL OUTPUT RISE/FALL TIME
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 15
Clock
Outputs
20%
20%
LVCMOS OUTPUT RISE/FALL TIME
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
Phase Noise Plot
Noise Power
nQA, nQB
QA, QB
Phase Noise Mask
t PW
t
f1
Offset Frequency
odc =
f2
PERIOD
t PW
x 100%
t PERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
PHASE JITTER
V
CCO_LVCMOS
VCLK,
REF_CLK
2
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 16
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
APPLICATION INFORMATION
DESCRIPTION OF THE PLL STAGES
The ICS843002-31 is a two stage frequency multiplication device,
a VCXO PLL followed by a low phase noise FemtoClock frequency
multiplier. The VCXO uses an external pullable crystal which can
be pulled ±100ppm by the VCXO PLL circuitry to phase lock it to
the input reference frequency. The output frequency of the VCXO
PLL is equal to that of the external pullable crystal, which is in the
range of 17.5MHz to 25MHz. The loop bandwidth VCXO PLL is
typically set in the range of 10-250Hz which provides attenuation
of input reference clock jitter. Since the VCXO is a high-Q oscillator
circuit, it has low intrinsic output jitter and phase noise. The VCXO
PLL output clock is available from the VCLK pin.
The FemtoClock frequency multiplier has an effective control
bandwidth of about 800kHz which means it will track the VCXO
PLL clock output.
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the setting of the VCXO feedback divider value (XOFB) and
by the external loop filter components. A practical range of loop
bandwidth for many applications is 25Hz to 1kHz. A bandwidth
of less than 10Hz requires careful component selection and
possible metal shielding to prevent clock output wander. A damping factor of 0.7 or greater should be used to ensure loop stability.
When a passband peaking of 1), calculate the value of CP based on
a CS value that would be used for a damping factor of 1. This will
minimize baseband peaking and loop instability that can lead to
output jitter.
In the loop filter schematic diagram, capacitors are shown between
pins 62 to ground and between pins 63 to ground. These are
optional crystal load capacitors which can be used to center tune
the external pullable crystal (the crystal frequency can only be
lowered by adding capacitance, it cannot be raised). Note that
the addition of external load capacitors will decrease the crystal
pull range and the Kvco value.
CP also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A CP value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and CP is too small, the VCXO PLL
input voltage can hit the supply or ground rail resulting in nonlinear loop response.
NOTES ON SETTING CHARGE PUMP CURRENT
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
The recommended range for the charge pump current is 50μA
to 500μA. Below 50μA, loop filter charge leakage, due to PCB
or capacitor leakage, can become a problem. This loop filter
leakage can cause locking problems, output clock cycle slips,
or low frequency phase noise.
As can be seen in the loop bandwidth and damping factor
equations or by using the filter response software available
from ICS, increasing charge pump current (ICP) increases both
bandwidth and damping factor.
RSET
Charge Pump Current (ICP)
17.6K
62.5µA
8.8K
125µA
4.4K
250µA
2.2K
500µA
ICP, Amps
1E-3
100E-6
10E-6
1k
10k
RSET, Ω
100k
FIGURE 2. CHARGE PUMP CURRENT VS. VALUE OF RSET
(EXTERNAL RESISTOR) GRAPH
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 18
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
VCXO GAIN (KO) VS. XTAL FREQUENCY
9000
8000
K VCO
7000
(Hz/V)
6000
5000
4000
16
18
20
22
26
24
XTAL Frequency (MHz)
EXAMPLE LOOP FILTER COMPONENT VALUE
Example
Case
Number
Device Configuration
XTAL
XOIN
XOFB
Frequency
Divider Divider
(MHz)
19.44
1
2430
Loop Filter Component Selection
RSET
RS
CS
CP
Resistor Resistor Cap
Cap
(kΩ )
(kΩ )
(µF)
(µF)
4.5
150
10
0.01
VCXO PLL Performance
Loop BW
Loop
Passband
(-3dB)
Damping Peaking
(MHz)
Factor
(dB)
18
5.8
0.1
1
Input
Reference
Clock
8kHz
2
8kHz
19.44
1
2430
0
4.5
150
2.2
0.01
19
2.8
0.3
3
19.44kHz
19.44
32
32
0
9.09
11
10
0.01
65
2.7
0.3
4
19.44MHz
19.44
8
8
0
9.09
11
10
0.01
180
5.3
0.1
MP
Divider
0
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 19
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002-31 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V CC, V CCA, V CCA_XO, and
VCCO_X should be individually connected to the power supply
plane through vias, and bypass capacitors should be used for
each pin. To achieve optimum jitter performance, power supply
isolation is required. Figure 3 illustrates how a 10Ω resistor
along with a 10μF and a .01μF bypass capacitor should be
connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK0 /nCLK0 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4D show interface
examples for the HiPerClockS CLK0/nCLK0 input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
IDT HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 20
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
DIFFERENTIAL CLOCK INPUT CIRCUIT
USING THE DIFFERENTIAL INTERFACE FOR SINGLE-ENDED CLOCKS
The differential interface (CLK0/nCLK0) can be used as a third
single-ended input to support an LVCMOS or LVTTL clock
driver. The clock input is connected to the CLK0 input pin,
and the nCLK0 pin is left unconnected. To help reduce interference with the internal VCO circuits, an external resistor can be
placed in series with the clock signal near the CLK0 input pin.
Series
Termination
Optional
Series
Filter
Resistor
Combined with the input pin capacitance, this resistor acts as
a low pass signal filter. The typical value of this optional series
filter resistor is 100Ω. This will lower both the amplitude and
edge rate of the clock input signal. In the case of a very short
clock trace a series termination register may not be needed.
3.3V
3.3V
CLK0
CLK
LVTTL
or LVCMOS
Logic Output
51k
nCLK0
nCLK
(no connection)
51k
External Circuitry
51k
Differential
Input Stage
Internal Device Circuitry
FIGURE 5. SINGLE-ENDED CLOCK INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 21
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
THERMAL RELEASE PATH
The exposed metal pad provides heat transfer from the
device to the P.C. board. The exposed metal pad is ground pad
connected to ground plane through thermal via. The exposed pad
on the device to the exposed metal pad on the PCB is contacted
through solder as shown in Figure 6. For further information,
please refer to the Application Note on Surface Mount Assembly
of Amkor’s Thermally /Electrically Enhance Leadframe Base
Package, Amkor Technology.
EXPOSED PAD
SOLDER M ASK
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
THERM AL VIA
(GROUND PAD)
FIGURE 6. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal distortion. Figures 7A and 7B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
VCC - 2V
RTT
FIGURE 7A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 22
Zo = 50Ω
84Ω
84Ω
FIGURE 7B. LVPECL OUTPUT TERMINATION
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 395mA = 1368.67mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 1368.67mW + 60mW = 1428.67mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.429W * 17.2°C/W = 94.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ JA FOR 64-PIN TQFP, E-PAD FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
22.3°C/W
17.2°C/W
15.1°C/W
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 23
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 24
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
64 LEAD TQFP, E-PAD
θJA vs. 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
22.3°C/W
17.2°C/W
15.1°C/W
TRANSISTOR COUNT
The transistor count for ICS843002-31 is: 10,095
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 25
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PACKAGE OUTLINE - Y SUFFIX
FOR
PRELIMINARY
64 LEAD TQFP, EPAD (32 pin package depicted to define Table 9 dimension symbols)
TABLE 9. PACKAGE DIMENSIONS
FOR
64 LEAD TQFP, EPAD
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
ACD-HD
MINIMUM
NOMINAL
MAXIMUM
64
N
A
--
--
1.20
A1
0.05
0.10
0.15
A2
0.95
1.0
1.05
b
0.17
0.22
0.27
c
0.09
--
0.20
D
12.00 BASIC
D1
10.00 BASIC
D2
7.50 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.50 Ref.
0.50 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.08
D3 & E3
4.5
5.0
5.5
Reference Document: JEDEC Publication 95, MS-026
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 26
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843002CY-31
ICS843002CY31
64 Lead TQFP, EPAD
tray
0°C to 70°C
ICS843002CY-31T
ICS843002CY31
64 Lead TQFP, EPAD
500 tape & reel
0°C to 70°C
ICS843002CY-31LF
TBD
64 Lead "Lead-Free" TQFP, EPAD
tray
0°C to 70°C
ICS843002CY-31LFT
TBD
64 Lead "Lead-Free" TQFP, EPAD
500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 27
ICS843002CY-31 REV. C MAY 16, 2007
ICS843002-31
FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
netcom@idt.com
480-763-2056
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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