8430BY-71LFT

8430B-71 700MHZ, Low Jitter, Crystal Interface LVCMOS-to-3.3V LVPECL Frequency Synthesizer GENERAL DESCRIPTION FEATURES The 8430B-71 is a general purpose, dual output Crystal/ LVCMOS-to-3.3V Differential LVPECL High Frequency Synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The 8430B-71 has a selectable crystal oscillator interface or LVCMOS TEST_CLK. The VCO operates at a frequency range of 250MHz to 700MHz. With the output configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved using a 16MHz crystal or test clock. Output frequencies up to 700MHz can be programmed using the serial or parallel interfaces to the configuration logic. The low jitter and frequency range of the 8430B-71 make it an ideal clock generator for most clock tree applications. • Dual differential 3.3V LVPECL outputs Data Sheet • Selectable crystal oscillator interface or LVCMOS TEST_CLK • Output frequency up to 700MHz • Crystal input frequency range: 12MHz to 27MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 9ps (maximum) • Cycle-to-cycle jitter: 25ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Replaces 8430-71 • Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT VCO_SEL PU XTAL_IN nP_LOAD M0 M1 32 31 30 29 28 27 26 25 0 OSC M2 XTAL_IN M3 M4 TEST_CLK PD VCO_SEL XTAL_SEL PU 1 XTAL_OUT ÷16 PLL M5 1 24 XTAL_OUT M6 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA N2 7 18 S_CLOCK VEE 8 17 MR ICS8430B-71 9 10 11 12 13 14 15 16 Phase Detector TEST VEE Configuration Interface Logic nFOUT0 S_DATA PD S_CLOCK PD FOUT0 S_LOAD PD VCCO FOUT0 nFOUT0 nFOUT1 1 ÷2 FOUT0 nFOUT0 FOUT1 ÷N VCC ÷M 0 TEST VCO MR PD 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View nP_LOAD PD M0:M8 N0:N2 ©2015 Integrated Device Technology, Inc 1 November 30, 2015 8430B-71 Data Sheet FUNCTIONAL DESCRIPTION automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The 8430B-71 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 125 ≤ M ≤ 350. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the 8430B-71 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will T1 T0 TEST Output 0 0 LOW 0 1 S_Data clocked into register 1 0 Output of M divider 1 1 CMOS Fout FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS ©2015 Integrated Device Technology, Inc 2 November 30, 2015 8430B-71 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name 1, 2, 3, M5, M6, M7, 28, 29, 30 M0, M1, M2, M3, 31, 32 M4 4 M8 Type Input Input Description Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_ LOAD input. LVCMOS / LVTTL interface levels. Pullup 5, 6 N0, N1 Input 7 N2 Input Pulldown Determines output divider value as defined in Table 3C Pullup Function Table. LVCMOS / LVTTL interface levels. 8, 16 VEE Power 9 TEST Output 10 VCC Power Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core power supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master reset. When logic HIGH, the internal dividers are reset causing the true outputs (FOUTx) to go low and the inverted out17 MR Input Pulldown puts (nFOUTx) to go high. When Logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register 18 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_ 19 S_DATA Input Pulldown CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS 20 S_LOAD Input Pulldown / LVTTL interface levels. 21 VCCA Power Analog supply pin. Selects between the crystal oscillator or test clock as the 22 XTAL_SEL Input Pullup PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS interface levels. 24, XTAL_OUT, Crystal oscillator interface. XTAL_IN is the input. Input 25 XTAL_IN XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded 26 nP_LOAD Input Pulldown into the M divider, and when data present at N2:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 27 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ©2015 Integrated Device Technology, Inc 3 November 30, 2015 8430B-71 Data Sheet TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) 125 256 M8 0 128 M7 0 64 M6 1 32 M5 1 16 M4 1 8 M3 1 4 M2 1 2 M1 0 1 M0 1 252 126 0 0 1 1 1 1 1 1 0 254 127 0 0 1 1 1 1 1 1 1 256 128 0 1 0 0 0 0 0 0 0 • • • • • • • • • • • • • • • • • • • • • • 696 348 1 0 1 0 1 1 1 0 0 698 349 1 0 1 0 1 1 1 0 1 VCO Frequency (MHz) M Divide 250 700 350 1 0 1 0 1 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 16MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value FOUT0, nFOUT0 Output Frequency (MHz) Minimum Maximum 125 350 N2 0 N1 0 N0 0 2 0 0 1 4 0 1 0 8 31.25 87.5 0 1 1 16 15.625 43.75 1 0 0 1 250 700 1 0 1 2 125 350 1 1 0 4 62.5 175 1 1 1 8 31.25 87.5 ©2015 Integrated Device Technology, Inc 4 62.5 175 November 30, 2015 8430B-71 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Minimum Typical Maximum Units VCC Symbol Core Supply Voltage Parameter Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 140 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical TEST_CLK; NOTE 1 VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current VCO_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, MR, M0:M8, N0:N2, XTAL_SEL Maximum Units 2.35 VCC + 0.3 V 2 VCC + 0.3 V -0.3 0.8 V M0-M7, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD VCC = VIN = 3.465V 150 µA M8, N2, XTAL_SEL, VCO_SEL VCC = VIN = 3.465V 5 µA TEST_CLK VCC = VIN = 3.465V 200 µA M0-M7, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD VCC = 3.465V, VIN = 0V -5 µA TEST_CLK, M8, N2, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2.6 V Output TEST; NOTE 2 High Voltage Output VOL TEST; NOTE 2 Low Voltage NOTE 1: Characterized with 1ns input edge rate. NOTE 2: Outputs terminated with 50Ω to VCCO/2. VOH 0.5 V TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50W to VCCO - 2V. See “Parameter Measurement Information” section, “3.3V Output Load Test Circuit” figure. ©2015 Integrated Device Technology, Inc 5 November 30, 2015 8430B-71 Data Sheet TABLE 5. INPUT CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol fIN tr_input Parameter Test Conditions Input Frequency Input Rise Time Minimum TEST_CLK; NOTE 1 XTAL_IN, XTAL_OUT; NOTE 1 S_CLOCK Maximum Units 12 Typical 27 MHz 12 27 MHz 50 MHz 5 ns TEST_CLK NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466. Using the maximum frequency of 27MHz, valid values of M are 75 ≤ M ≤ 207. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 27 MHz Equivalent Series Resistance (ESR) 12 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FMAX Output Frequency Test Conditions tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3 tjit(per) Period Jitter, RMS; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time tS tH odc tLOCK Setup Time Hold Time Maximum Units 700 MHz fOUT > 87.5MHz 25 ps fOUT ≤ 87.5MHz 45 ps 9 ps 15 ps 700 ps 20% to 80% Minimum Typical 200 M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle N ≠ div-by-1 48 52 % N = div-by-1, fOUT ≤ 400MHz 45 55 % N = div-by-1, 400MHz < fOUT 630MHz 40 60 % 1 ms PLL Lock Time See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. ©2015 Integrated Device Technology, Inc 6 November 30, 2015 8430B-71 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW PERIOD JITTER CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2015 Integrated Device Technology, Inc 7 November 30, 2015 8430B-71 Data Sheet APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 8430B-71 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ©2015 Integrated Device Technology, Inc 8 November 30, 2015 8430B-71 Data Sheet CRYSTAL INPUT INTERFACE A crystal can be characterized for either series or parallel mode operation. The 8430B-71 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 2. FIGURE 2. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro Rs .1uf Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE ©2015 Integrated Device Technology, Inc 9 November 30, 2015 8430B-71 Data Sheet TERMINATION FOR LVPECL OUTPUTS lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4A. LVPECL OUTPUT TERMINATION ©2015 Integrated Device Technology, Inc FIGURE 4B. LVPECL OUTPUT TERMINATION 10 November 30, 2015 8430B-71 Data Sheet LAYOUT GUIDELINE The schematic of the 8430B-71 layout example used in this layout guideline is shown in Figure 5A. The 8430B-71 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_IN VCC ICS8430B-71 X_OUT TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE M5 M6 M7 M8 N0 N1 N2 VEE 9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16 U1 1 2 3 4 5 6 7 8 C2 X1 32 31 30 29 28 27 26 25 C1 system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. C14 0.1u C15 0.1u VCC 24 23 22 21 20 19 18 17 REF_IN XTAL_SEL S_LOAD S_DATA S_CLOCK R7 10 VCCA C11 0.01u C16 10u VCC Zo = 50 Ohm R1 125 R3 125 IN+ TL1 Zo = 50 Ohm + IN- TL2 R2 84 R4 84 FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT ©2015 Integrated Device Technology, Inc 11 November 30, 2015 8430B-71 Data Sheet The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. • The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. • Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. • Make sure no other signal trace is routed between the clock trace pair. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. CLOCK TRACES AND TERMINATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. FIGURE 5B. PCB BOARD LAYOUT FOR 8430B-71 ©2015 Integrated Device Technology, Inc 12 November 30, 2015 8430B-71 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 8430B-71. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8430B-71 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 485mW + 60mW = 545mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.545Ω * 42.1°C/W = 93°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ©2015 Integrated Device Technology, Inc 13 November 30, 2015 8430B-71 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2015 Integrated Device Technology, Inc 14 November 30, 2015 8430B-71 Data Sheet RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8430B-71 is: 3948 ©2015 Integrated Device Technology, Inc 15 November 30, 2015 8430B-71 Data Sheet PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 10. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL N MAXIMUM 32 A 1.60 A1 0.05 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.15 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 e 0.80 BASIC L 0.45 θ 0° 0.60 0.75 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ©2015 Integrated Device Technology, Inc 16 November 30, 2015 8430B-71 Data Sheet TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package 8430BY-71LF ICS8430BY71L 8430BY-71LFT ICS8430BY71L ©2015 Integrated Device Technology, Inc Shipping Packaging Temperature 32 lead “Lead Free” LQFP Tray 0°C to +70°C 32 lead “Lead Free” LQFP Tape and Reel 0°C to +70°C 17 November 30, 2015 8430B-71 Data Sheet REVISION HISTORY SHEET Rev Table Page A T11 17 A Description of Change Date Ordering Information Table - corrected “Temperature” column 11/20/06 Updated data sheet format. 11/30/15 ©2015 Integrated Device Technology, Inc 18 November 30, 2015 8430B-71 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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