84321AYLF

ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES • Dual differential 3.3V LVPECL outputs The ICS84321 is a general purpose, dual output Crystal-to3.3V Differential LVPECL High Frequency Synthesizer. The ICS84321 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 103.3MHz to 260MHz • Crystal input frequency range: 14MHz to 40MHz • VCO range: 620MHz to 780MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 3ps (typical) • RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.5ps (typical) Phase noise: 155.52MHz Offset Noise Power 100Hz ..................-84.1 dBc/Hz 1kHz ................-109.8 dBc/Hz 10kHz ................-126.3 dBc/Hz 100kHz ................-128.7 dBc/Hz • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Lead-Free package RoHS compliant • Use replacement part 8T49N004-dddNLGI BLOCK DIAGRAM 84321AY PIN ASSIGNMENT www.idt.com 1 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: The ICS84321 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 25 ≤ M ≤ 31. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84321 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set T1 T0 TEST Output 0 0 LOW 0 1 S_DATA, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 84321AY www.idt.com 2 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 M5 Input Type Description 2, 3, 4, 28, 29, 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input M divider inputs. Data latched on LOW-to-HIGH transition Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. 5, 6 N0, N1 Input Pulldown 7 nc Unused 8, 16 VEE Power Negative supply pins. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. 10 VCC Power Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Pullup Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Differential output for the synthesizer. LVPECL interface levels. 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power 22 XTAL_SEL Input 23 TEST_CLK Input 24, 25 XTAL_OUT, XTAL_IN Input 26 nP_LOAD Input 27 VCO_SEL Input Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low, and the inverted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_ CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Pullup Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Pulldown Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded Pulldown into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 84321AY Test Conditions www.idt.com 3 Minimum Typical Maximum Units REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑= Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 1 1 0 0 1 26 0 0 0 0 1 1 0 1 0 27 0 0 0 0 1 1 0 1 1 • • • • • • • • • • • 775 31 0 0 0 0 1 1 1 1 1 VCO Frequency (MHz) M Divide 625 25 650 675 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz. 84321AY www.idt.com 4 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 3 206.7 260 0 1 4 155 195 1 0 5 124 156 1 1 6 103.3 130 TABLE 3D. COMMONLY USED CONFIGURATION FUNCTION TABLE Input Output Frequency (MHz) Crystal (MHz) M Divider Value N Divider Value 19.44 32 4 155.52 19.53125 32 4 156.25 25 25 4 156.25 25 25 5 125 25.50 25 3 212.50 25.50 25 4 159.375 25.50 25 6 106.25 38.88 16 4 155.52 84321AY www.idt.com 5 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC VCCA Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 178 mA ICCA Analog Supply Current 26 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL Parameter Test Conditions Minimum Typical Maximum Units Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 2 VCC + 0.3 V TEST_CLK 2 VCC + 0.3 V Input Low Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 -0.3 0.8 V TEST_CLK -0.3 1.3 V Input High Current Input Low Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD VCC = VIN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL VCC = VIN = 3.465V 5 µA M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD VCC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2.6 V VOH Output High Voltage TEST; NOTE 1 VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO/2. 84321AY www.idt.com 6 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See “Parameter Measurement Information” section, “3.3V Output Load Test Circuit”. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol fIN Parameter Test Conditions Input Frequency Minimum Typical TEST_CLK; NOTE 1 14 40 MHz XTAL_IN, XTAL_OUT; NOTE 1 14 40 MHz 50 MHz S_CLOCK NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 620MHz to 780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 ≤ M ≤ 55. Using the maximum frequency of 40MHz, valid values of M are 16 ≤ M ≤ 19. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 14 40 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions FOUT Output Frequency tjit(per) Period Jitter, RMS; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time tS tH Setup Time Hold Time Minimum Typical 103.3 3 20% to 80% 200 Maximum Units 260 MHz 4.5 ps 15 ps 700 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle tLOCK PLL Lock Time 45 55 % 1 ms See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 84321AY www.idt.com 7 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE 0 -10 25MHz Input -20 RMS Phase Noise Jitter 12K to 20MHz = 3.0ps (typical) -30 -40 -60 -70 Z H ) (dBc PHASE NOISE -50 -80 -90 -100 156.25MHz 125MHz -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 0 -10 25.5MHz Input -20 RMS Phase Noise Jitter 12K to 20MHz = 3.0ps (typical) -30 -40 -60 -70 Z H ) (dBc PHASE NOISE -50 -80 -90 212.5MHz -100 -110 -120 -130 -140 -150 106.25MHz 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 84321AY www.idt.com 8 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW PERIOD JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84321AY www.idt.com 9 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FIGURE 2A. LVPECL OUTPUT TERMINATION FIGURE 2B. LVPECL OUTPUT TERMINATION CRYSTAL INPUT INTERFACE values will tune any 18pF parallel resonant crystal over the frequency range of 14MHz to 40MHz providing the other parameters specified in Table 6, Crystal Characteristics, are satisfied. The ICS84321 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p FIGURE 3. CRYSTAL INPUt INTERFACE 84321AY www.idt.com 10 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84321 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 4 illustrates how a 24Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC 24Ω .01μF VCCA 10 μF .01μF FIGURE 4. POWER SUPPLY FILTERING LAYOUT GUIDELINE The schematic of the ICS84321 layout example used in this layout guideline is shown in Figure 5A. The ICS84321 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_IN VCC ICS84321 X_OUT T_CLK nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE M5 M6 M7 M8 N0 N1 nc VEE 9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16 U1 1 2 3 4 5 6 7 8 C2 X1 32 31 30 29 28 27 26 25 C1 layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. C14 0.1u C15 0.1u VCC 24 23 22 21 20 19 18 17 REF_IN XTAL_SEL S_LOAD S_DATA S_CLOCK R7 10 VCCA C11 0.01u C16 10u VCC Zo = 50 Ohm R1 125 R3 125 + Zo = 50 Ohm R2 84 R4 84 FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT 84321AY www.idt.com 11 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: • The differential 50Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES AND TERMINATION • The matching termination resistors should be located as close to the receiver input pins as possible. Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL_IN) and 24 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. FIGURE 5B. PCB BOARD LAYOUT FOR ICS84321 84321AY www.idt.com 12 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84321. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84321 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 178mA = 616.8mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 616.8W + 60mW = 676.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.677W * 42.1°C/W = 98.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84321AY www.idt.com 13 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω) * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 84321AY www.idt.com 14 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84321 is: 3744 84321AY www.idt.com 15 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 10. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL N MAXIMUM 32 A -- A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 -- D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 1.60 0.80 BASIC L 0.45 θ 0° -- 7° ccc -- -- 0.10 0.60 0.75 Reference Document: JEDEC Publication 95, MS-026 84321AY www.idt.com 16 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 84321AYLF ICS84321AYLF 32 Lead “Lead-Free” LQFP tray 0°C to 70°C 84321AYLFT ICS84321AYLF 32 Lead “Lead-Free” LQFP tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 84321AY www.idt.com 17 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change A 1 Features section - RMS period jitter bullet, corrected typo from 2.5ps to 3ps. A 1 10 17 Features section - add Lead-Free bullet. Updated LVPECL Output Termination drawings. Ordering Information table - added Lead-Free part number. Removed sentence from General Description. Updated Figure 1. Crystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free note. Rename XTAL1/2 to XTAL_IN/XTAL_OUT throughout the datasheet. LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4C. B T11 T6 T11 4C 1 2 7 17 7 13 - 14 C C T11 D D 84321AY T11 Date 10/8/03 2/11/05 6/9/05 4/10/07 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added LF marking. Added Contact Page. 7/27/10 1 Product Discontinuation Notice - Last Time Buy Expires (OCTOBER 28, 2014) PDN# CQ-13-03 11/6/13 17 Ordering Information - removed leaded devices per PDN CQ-13-03 2/25/15 17 19 www.idt.com 18 REV. D 2/25/15 ICS84321 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 clocks@idt.com © 2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 84321AY www.idt.com 19 REV. D 2/25/15