84330CVT

700MHz, Low Jitter, Crystal-to-3.3V Differential LVPECL Frequency Synthesizer ICS84330C DATA SHEET General Description Features The ICS84330C is a general purpose, single output high frequency synthesizer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as 250kHz to 2MHz can be achieved using a 16MHz crystal depending on the output divider settings. • • • • • • Fully integrated PLL, no external loop filter requirements • • • • • RMS period jitter: 5ps (maximum) FREF_EXT 6 19 M6 XTAL_SEL 7 18 M5 8 M4 26 18 N1 S_DATA 27 17 N0 VCCA FREF_EXT XTAL_SEL Block Diagram XTAL1 ICS84330C 16 28 Lead PLCC V Package 15 1 11.6mm x 11.4mm x 4.1mm 14 2 package body Top View 13 3 28 4 12 XTAL1 1 7 ÷ 16 M5 M4 TEST Pullup Pullup ICS84330CV REVISION D JULY 17, 2009 3 VCCA 4 VCCA 5 FREF_EXT 6 XTAL_SEL 7 XTAL1 8 ICS84330C 32 Lead LQFP Y Package 7mm x 7mm x 1.4mm package body Top View 9 1 24 nc 23 N1 22 N0 21 M8 20 M7 19 M6 18 M5 17 M4 10 11 12 13 14 15 16 nc CONFIGURATION INTERFACE LOGIC 2 S_LOAD M3 ÷2 0 S_DATA XTAL2 ÷M M0:M8 N0:N1 M7 M6 10 11 M2 VCO FOUT nFOUT 1 M1 1 ÷2 ÷4 ÷8 ÷1 S_CLOCK nP_LOAD PHASE DETECTOR Pulldown Pulldown Pulldown Pullup 9 M8 32 31 30 29 28 27 26 25 PLL S_LOAD S_DATA S_CLOCK nP_LOAD nFOUT VCC XTAL_SEL Pullup 0 OE Pulldown FOUT XTAL2 FREF_EXT 8 M0 OSC 6 OE 5 Pullup XTAL2 OE S_CLOCK S_LOAD nc M3 M2 M0 M1 nP_LOAD 10 11 12 13 14 15 16 OE 17 9 XTAL2 XTAL1 25 24 23 22 21 20 19 M3 M7 VEE 20 M2 5 TEST VCCA Pin Assignments VCC M8 M0 21 M1 N0 4 VCC 22 VCCA ICS84330C 32 Lead VFQFN K Package 5mm x 5mm x 0.925mm package body Top View Available in both standard (RoHS 5) and lead-free (RoHS 6) packages VEE 3 0°C to 70°C ambient operating temperature TEST S_LOAD 3.3V supply voltage VEE N1 Cycle-to-cycle jitter: 40ps (maximum) VCC nc 23 Parallel or serial interface for programming M and N dividers during power-up FOUT 24 2 VCO range: 250MHz to 700MHz nFOUT 1 S_DATA Output frequency range: 31.25MHz to 700MHz VCC S_CLOCK Crystal oscillator interface: 10MHz to 25MHz VEE 32 31 30 29 28 27 26 25 One differential 3.3V LVPECL output nP_LOAD VEE TEST VCC VCC VEE VCC FOUT Pin Assignment nFOUT ICS ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Functional Description NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1. The ICS84330C features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fXTAL x 2M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 125 ≤ M ≤ 350. The frequency out is defined as follows: fout = fVCO = fXTAL x 2M N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of the TEST output as follows in the table below: The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84330C support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST Output Shift Register Out HIGH PLL Reference XTAL ÷16 (VCO ÷ M)/2 (non 50% Duty Cycle M Divider) fOUT, LVCMOS Output Frequency < 200MHz LOW (S_CLOCK ÷ M)/2 (non 50% Duty Cycle M Divider) fOUT ÷ 4 fOUT fOUT fOUT fOUT fOUT fOUT fOUT S_CLOCK ÷ N Divider fOUT SERIAL LOADING S_CLOCK T2 S_DATA t S_LOAD S t T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 H t nP_LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t H nP_LOAD Time Figure 1. Parallel & Serial Load Operations ICS84330CV REVISION D JULY 17, 2009 2 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Name Type Description Power VCCA Analog supply pin. XTAL1, XTAL2 Crystal oscillator interface. XTAL1 is an oscillator input, XTAL2 is an oscillator output. XTAL_SEL Input Pullup Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW. LVCMOS / LVTTL interface levels. OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. nP_LOAD Input Pullup Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. M0, M1, M2 M3, M4, M5 M6, M7, M8 Input Pullup M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pullup Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. VEE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. Single-ended LVPECL interface levels. VCC Power Core supply pins. nFOUT, FOUT Output Differential output for the synthesizer. 3.3V LVPECL interface levels. nc Unused No connect. FREF_EXT Input Pulldown PLL reference input. LVCMOS / LVTTL interface levels. S_CLOCK Input Pulldown Clocks the serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS84330CV REVISION D JULY 17, 2009 Test Conditions Minimum Typical 4 3 Maximum Units pF ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Function Tables Table 3A. Parallel and Serial Mode Function Table Inputs nP_LOAD M N S_LOAD S_CLOCK S_DATA Conditions X X X X X X Reset. M and N bits are all set HIGH. L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST mode 000. ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. H X X L ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. H X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. H X X ↓ L Data M divider and N output divider values are latched. H X X L X X H X X H ↑ Data Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition Table 3B. Programmable VCO Frequency Function Table 256 128 64 32 16 8 4 2 1 M Divide M8 M7 M6 M5 M4 M3 M2 M1 M0 125 0 0 1 1 1 1 1 0 1 252 126 0 0 1 1 1 1 1 1 0 254 127 0 0 1 1 1 1 1 0 1 256 128 0 1 0 0 0 0 0 1 0 • • • • • • • • • • • VCO Frequency (MHz) 250 • • • • • • • • • • • 696 348 1 0 1 0 1 1 1 0 0 698 349 1 0 1 0 1 1 1 0 1 700 350 1 0 1 0 1 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. Table 3C. Programmable Output DividerFunction Table Inputs Output Frequency (MHz) N1 N0 N Divider Value Minimum Maximum 0 0 2 125 350 0 1 4 62.5 175 1 0 8 31.25 87.5 1 1 1 250 700 ICS84330CV REVISION D JULY 17, 2009 4 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 28 Lead PLCC 32 Lead LQFP 32 Lead VFQFN 37.8°C/W (0 lfpm) 47.9°C/W (0 lfpm) 37.0°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 160 mA ICCA Analog Supply Current 16 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V M0-M8, N0, N1, OE, nP_LOAD, XTAL_SEL VCC = VIN = 3.465V 5 µA S_LOAD, S_CLOCK FREF_EXT, S_DATA VCC = VIN = 3.465V 150 µA M0-M8, N0, n1, OE, nP_LOAD, XTAL_SEL VCC = 3.465V, VIN = 0V -150 µA S_LOAD, S_CLOCK FREF_EXT, S_DATA VCC = 3.465V, VIN = 0V -5 µA Table 4C. LVPECL DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC -2V. ICS84330CV REVISION D JULY 17, 2009 5 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 25 MHz Fundamental Frequency 10 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Table 6. Input Frequency Characteristics, VCC = 3V±5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions fIN Input Frequency XTAL; NOTE 1 Minimum Typical 10 S_CLOCK FREF_EXT; NOTE 2 Maximum Units 25 MHz 50 MHz 10 MHz NOTE 1: For the crystal frequency range, the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz to 700MHz. Using the minimum input frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511. Using the maximum input frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224. NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information Section for recommendations on optimizing the performance using the FREF_EXT input. AC Electrical Characteristics Table 7. AC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 700 MHz tjit(per) Period Jitter, RMS; NOTE 1. 2 5 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 40 ps tR / tF Output Rise/Fall Time 600 ns tS Setup Time 20% to 80% 200 S_DATA to S_CLOCK 20 ns S_CLOCK to S_LOAD 20 ns M, N to nP_LOAD 20 ns S_DATA to S_CLOCK 20 ns M, N to nP_LOAD 20 tH Hold Time tL PLL Lock Time odc Output Duty Cycle 45 ns 10 ms 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information section. NOTE: Characterized using 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications section. ICS84330CV REVISION D JULY 17, 2009 6 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 2V VOH VREF VCC, VCCA Qx SCOPE VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements LVPECL nQx Histogram Reference Point Mean Period (Trigger Edge) VEE (First edge after trigger) -1.3V±0.165V Period Jitter 3.3/3.3V LVPECL Output Load AC Test Circuit nFOUT nFOUT FOUT FOUT ➤ tcycle n ➤ tcycle n+1 t PW ➤ t ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles odc = PERIOD t PW x 100% t PERIOD Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period nFOUT 80% 80% VSW I N G FOUT 20% 20% tR tF Output Rise/Fall Time ICS84330CV REVISION D JULY 17, 2009 7 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS84330C provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω .01µF 10µF VCCA Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins TEST Output All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. The unused TEST output can be left floating. There should be no trace attached. LVPECL Outputs The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS84330CV REVISION D JULY 17, 2009 8 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals VCC the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN R2 Zo = Ro + Rs XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface Cycle-to-Cycle Jitter (ps) 50 40 30 Spec Limit N=1 20 10 0 200 300 400 500 600 700 Output Frequency (MHz) Figure 4. Cycle-to-Cycle Jitter vs. fOUT (using a 16MHz crystal) ICS84330CV REVISION D JULY 17, 2009 9 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω R1 50Ω _ LVPECL R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 84Ω RTT Figure 5A. 3.3V LVPECL Output Termination ICS84330CV REVISION D JULY 17, 2009 Input Zo = 50Ω Figure 5B. 3.3V LVPECL Output Termination 10 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Layout Guideline The schematic of the ICS84330C layout example used in this layout guideline is shown in Figure 6A. The ICS84330C recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. SP C1 X1 C2 SP M3 M2 M1 M0 nPLOAD OE 16MHz, 18pF SP = Space (i.e. not intstalled) M [8:0]= 110010000 (400) N[1:0] =00 (Divide by 2) 12 13 14 15 16 17 18 M4 M5 M6 M7 M8 N0 N1 X_IN XTAL_SEL FREF_EXT VCCA S_LOAD S_DATA S_CLOCK 19 20 21 22 23 24 25 U1 ICS84330 VCC VCC RD0 1K RD1 1K RD7 SP RD8 SP RU10 1K RD9 1K RU11 SP nPLoad RD10 SP RU12 1K R7 10 VCCA C11 0.01u C16 10u C3 0.1uF Zo = 50 Ohm C4 0.1u Fout = 200 M Hz + Zo = 50 Ohm - OE N0 RU9 SP N1 RU8 1K M8 RU7 1K M7 RU1 SP M1 M0 RU0 SP 4 3 2 1 28 27 26 VEE TEST VCC VEE nFOUT FOUT VCC M4 M5 M6 M7 M8 N2 N1 VCC=3.3V M3 M2 M1 M0 nP_LOAD OE X_OUT 11 10 9 8 7 6 5 VCC RD6 1K R2 50 RD12 SP R1 50 R3 50 Figure 6A. ICS84330C Schematic of Recommended Layout ICS84330CV REVISION D JULY 17, 2009 11 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: length. All the resistors and capacitors are size 0603. Power and Grounding • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Place the decoupling capacitors C3 and C4, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. Clock Traces and Termination • The matching termination resistors should be located as close to the receiver input pins as possible. Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. Crystal The crystal X1 should be located as close as possible to the pins 4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. • The differential 50Ω output traces should have the same X1 C1 C2 U1 GND VCC PIN 2 C11 PIN 1 C16 VCCA VCCA R7 VIA Signals Traces C3 C4 50 Ohm Traces Figure 6B. ICS84330C PCB Board Layout for ICS84330C ICS84330CV REVISION D JULY 17, 2009 12 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS84330C. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84330C is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 176mA = 609.8mW • Power (outputs)MAX=30mW/Loaded Output Pair Total Power_MAX (3.465V, with all outputs switching) = 609.8mW + 30mW = 639.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.640W * 31.1°C/W = 89.9°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 8A. Thermal Resistance θJA for 28 Lead PLCC, Forced Convection θJA by Velocity Linear Feet per Minute 0 200 500 37.8°C/W 31.1°C/W 28.3°C/W 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W Multi-Layer PCB, JEDEC Standard Test Boards Table 8B. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection θJA by Velocity Linear Feet per Minute NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS84330CV REVISION D JULY 17, 2009 13 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 8C. Thermal Resistance θJA for 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC - 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX -0.9V (VCC_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX -1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V -0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX -2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS84330CV REVISION D JULY 17, 2009 14 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Reliability Information Table 9A. θJA vs. Air Flow Table for a 28 Lead PLCC θJA vs. Air Flow Linear Feet per Minute 0 200 500 37.8°C/W 31.1°C/W 28.3°C/W 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W Multi-Layer PCB, JEDEC Standard Test Boards Table 9B. θJA vs. Air Flow Table for a 32 Lead LQFP θJA vs. Air Flow Linear Feet per Minute NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 9C. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W Transistor Count The transistor count for ICS84330C is: 4498 Pin compatible with the MC12430 ICS84330CV REVISION D JULY 17, 2009 15 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Package Outline and Package Dimensions Package Outline - V Suffix for 28 Lead PLCC Table 10A. Package Dimensions for 28 Lead PLCC JEDEC Variation All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D/E 12.32 12.57 D1/E1 11.43 11.58 D2/E2 5.21 5.46 Reference Document: JEDEC Publication 95, MS-018 ICS84330CV REVISION D JULY 17, 2009 16 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Package Outline - Y Suffix for 32 Lead LQFP Table 10B. Package Dimensions for 32 Lead LQFP JEDEC Variation: BBA All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 θ 0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ICS84330CV REVISION D JULY 17, 2009 17 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e D2 2 N &N Odd 0. 08 C Th er mal Ba se D2 C NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 10C below. Table 10C. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS84330CV REVISION D JULY 17, 2009 18 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Ordering Information Table 11. Ordering Information Part/Order Number 84330CV 84330CVT 84330CVLN 84330CVLNT 84330CY 84330CYT 84330CYLN 84330CYLNT 84330CKLF 84330CKLFT Marking ICS84330CV ICS84330CV ICS84330CVLN ICS84330CVLN ICS84330CY ICS84330CY ICS84330CYLN ICS84330CYLN ICS84330CKL ICS84330CKL Package 28 Lead PLCC 28 Lead PLCC “Lead-Free” 28 Lead PLCC “Lead-Free” 28 Lead PLCC 32 Lead LQFP 32 Lead LQFP “Lead-Free/Annealed” 32 Lead LQFP “Lead-Free/Annealed” 32 Lead LQFP “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tube 500 Tape & Reel Tube 500 Tape & Reel Tube 1000 Tape & Reel Tube 1000 Tape & Reel Tray 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LN" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS84330CV REVISION D JULY 17, 2009 19 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Revision History Sheet Rev Table Page T1 2 3 Description of Change Date T5 6 8 Updated Parallel & Serial Load Operations Diagram. Pin Description Table - description to TEST output should read Single-ended LVPECL interface levels instead of LVCMOS/LVTTL interface levels. LVCMOS Table - VOH/VOL levels added TEST pin and changed VOH min. from 2.6V to VCC - 1.4V; changed VOL max. from 0.5V to VCC - 1.7V. Crystal Characteristics Table - changed ESR from 70Ω max. to 50Ω max. Updated LVPECL Output Termination diagrams. B T4B 5 Deleted VOH & VOL row entries from LVCMOS Table. 9/10/03 B T12 18 Added Lead-Free/Annealed to the Part Ordering Information Table. 6/1/04 T12 1 18 Features Section added Lead-Free bullet. Ordering Information Table - added PLCC Lead-Free part number. 10/5/04 1 Features Section - corrected Output Frequency Range from 25MHz to 31.25MHz 12/7/04 T3A 4 T4C 5 Parallel & Serial Mode Function Table - corrected 3rd line in S_LOAD column from “X” to “L”. LVPECL DC Characteristics Table - corrected VOH max. from VCC -1.0V to VCC -0.9V. Power Considerations - corrected power dissipation to reflect VOH max. in Table 4C. 4/10/07 B B T4B B C 5 13 - 14 C D 8/28/03 T10A 8 17 Added Recommendations for Unused Input and Output Pins. Package Dimension Table - D2/E2 changed the min. from 4.85 to 5.21 and the max. from 5.56 to 5.46. 1/28/09 T10C T11 1 5 18 19 Added 32 VFQFN Pin Assignment. Absolute Maximum Ratings - add 32 VFQFN Package Thermal Impedance. Added 32 VFQFN Package Dimensions and Diagram. Ordering Information Table - added 32 VFQFN ordering information. 7/17/09 ICS84330CV REVISION D JULY 17, 2009 20 ©2009 Integrated Device Technology, Inc. ICS84330C Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.