FemtoClock® Crystal-to-LVDS Frequency
Synthesizer w/Integrated Fanout Buffer
ICS844246DI
DATA SHEET
General Description
Features
The ICS844246DI is a Crystal-to-LVDS Clock Synthesizer/Fanout
Buffer designed for Fibre Channel frequencies and Gigabit Ethernet
applications. The output frequency can be set using the frequency
select pins and a 25MHz crystal for Ethernet frequencies, or a
26.5625MHz crystal for a Fibre Channel. The low phase noise
characteristics of the ICS844246DI make it an ideal clock for these
demanding applications.
•
•
•
•
•
Six LVDS output pairs
•
•
•
Full 3.3V or mixed 3.3V core, 2.5V output supply modes
Crystal oscillator interface
Output frequency range: 53.125MHz to 333.3333MHz
Crystal input frequency range: 25MHz to 33.333MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.416ps (typical)
-40°C to 85°C ambientoperating temperature
Available in lead-free (RoHS 6) package
Select Function Table
Inputs
Function
FB_SEL
N_SEL1
N_SEL0
M Divide
N Divide
M/N
0
0
0
20
2
10
0
0
1
20
4
5
0
1
0
20
5
4
0
1
1
20
8
2.5 (default)
1
0
0
24
3
8
1
0
1
24
4
6
1
1
0
24
6
4
1
1
1
24
12
2
Block Diagram
Pin Assignment
Q0
nQ0
PLL_BYPASS
Pullup
Q1
1
XTAL_IN
OSC
PLL
0
N
Output
Divider
XTAL_OUT
nQ1
Q2
nQ2
nQ3
Q4
Pulldown
N_SEL0
Pullup
N_SEL1
Pullup
ICS844246DGI REVISION A NOVEMBER 28, 2012
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
GND
GND
N_SEL0
XTAL_OUT
XTAL_IN
Q3
M
Feedback
Divider
FB_SEL
VDDO
VDDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
VDDA
VDD
FB_SEL
nQ4
Q5
ICS844246DI
24-Lead TSSOP, E-Pad
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
nQ5
1
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
1, 2
VDDO
Power
Type
Output supply pins.
Description
3, 4
nQ2, Q2
Output
Differential output pair. LVDS interface levels.
5, 6
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
7, 8
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
9
PLL_BYPASS
Input
10
VDDA
Power
LVCMOS / LVTTL interface levels.
Analog supply pin.
11
VDD
Power
Core supply pin.
Selects between the PLL and crystal inputs as the input to the dividers.
Pullup
Pulldown
When LOW, selects PLL. When HIGH, bypasses the PLL.
12
FB_SEL
Input
13
14
XTAL_IN,
XTAL_OUT
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Input
15, 18
N_SEL0,
N_SEL1
Input
16, 17
GND
Power
Power supply ground.
19, 20
nQ5, Q5
Output
Differential output pair. LVDS interface levels.
21, 22
nQ4, Q4
Output
Differential output pair. LVDS interface levels.
23, 24
nQ3, Q3
Output
Differential output pair. LVDS interface levels.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
ICS844246DGI REVISION A NOVEMBER 28, 2012
Test Conditions
2
Minimum
Typical
Maximum
Units
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Function Tables
Table 3. Crystal Function Table
Inputs
Function
XTAL (MHz)
FB_SEL
N_SEL1
N_SEL0
M
VCO (MHz)
N
Output Frequency (MHz)
25
0
0
0
20
500
2
250
25
0
0
1
20
500
4
125
25
0
1
0
20
500
5
100
25
0
1
1
20
500
8
62.5
25
1
0
0
24
600
3
200
25
1
0
1
24
600
4
150
25
1
1
0
24
600
6
100
25
1
1
1
24
600
12
50
26.5625
0
1
0
20
531.25
5
106.25
26.5625
1
0
0
24
637.5
3
212.5
26.5625
1
0
1
24
637.5
4
159.375
26.5625
1
1
0
24
637.5
6
106.25
26.5625
1
1
1
24
637.5
12
53.125
30
0
0
0
20
600
2
300
30
0
0
1
20
600
4
150
30
0
1
0
20
600
5
120
30
0
1
1
20
600
8
75
31.25
0
0
0
20
625
2
312.5
31.25
0
0
1
20
625
4
156.25
31.25
0
1
0
20
625
5
125
31.25
0
1
1
20
625
8
78.125
33.3333
0
0
0
20
666.6667
2
333.3333
33.3333
0
0
1
20
666.6667
4
166.6667
33.3333
0
1
0
20
666.6667
5
133.3333
33.3333
0
1
1
20
666.6667
8
83.3333
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
32.1C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.10
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
170
mA
IDDA
Analog Supply Current
10
mA
IDDO
Output Supply Current
100
mA
Table 4B. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.10
3.3
VDD
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
165
mA
IDDA
Analog Supply Current
10
mA
IDDO
Output Supply Current
98
mA
ICS844246DGI REVISION A NOVEMBER 28, 2012
Test Conditions
4
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VDD = 3.465V
VIL
Input Low Voltage
VDD = 3.465V
IIH
Input
High Current
IIL
Input
Low Current
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
N_SEL[1:0],
PLL_BYPASS
VDD = VIN = 3.465V or 2.625V
5
µA
FB_SEL
VDD = VIN = 3.465V or 2.625V
150
µA
N_SEL[1:0],
PLL_BYPASS
VDD = 3.465V or 2.625V, VIN = 0V
-150
µA
FB_SEL
VDD = 3.465V or 2.625V, VIN = 0V
-5
µA
Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
454
mV
100
mV
1.50
V
120
mV
Maximum
Units
33.333
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
247
1.10
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
25
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
AC Electrical Characteristics
Table 6. LVDS AC Characteristics, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
Test Conditions
Minimum
PLL_BYPASS = 0
50
Typical
In bypass mode with 25MHz Crystal,
PLL_BYPASS = 1 (default)
3.125
125MHz, Integration Range:
1.875MHz – 20MHz
0.416
20% to 80%
Maximum
Units
333.33
MHz
MHz
0.560
ps
45
ps
220
380
ps
45
55
%
25
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: See Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Typical Phase Noise at 125MHz
Gb Ethernet Filter
Raw Phase Noise Data
Noise Power dBc
Hz
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.416ps (typical)
Phase Noise Result by adding a
Gb Ethernet filter to raw data
Offset Frequency (Hz)
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Parameter Measurement Information
3.3V±5%
2.5V±5%
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
VDD,
VDDO
VDD
Qx
SCOPE
Qx
VDDA
VDDO
VDDA
+ +
nQx
nQx
3.3V Core/3.3V LVDS Output Load AC Test Circuit
–
POWER
SUPPLY
Float GND
3.3V Core/2.5V LVDS Output Load AC Test Circuit
nQ0:nQ5
nQx
Q0:Q5
Qx
t PW
t
nQy
Qy
odc =
PERIOD
t PW
x 100%
t PERIOD
tsk(o)
Output Skew
Output Duty Cycle/Pulse Width/Period
Noise Power
Phase Noise Plot
nQ0:nQ5
80%
80%
VOD
Q0:Q5
Phase Noise Mask
20%
20%
tR
tF
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Output Rise/Fall Time
ICS844246DGI REVISION A NOVEMBER 28, 2012
RMS Phase Jitter
8
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Parameter Measurement Information, continued
VDD
out
DC Input
LVDS
100
out
Differential Output Voltage Setup
VDD
out
DC Input
LVDS
out
VOS/Δ VOS
ä
Offset Voltage Setup
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Applications Information
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any transmissionline reflection issues, the components should be surface mounted
and must be placed as close to the receiver as possible. IDT offers a
full line of LVDS compliant devices with two types of output structures:
current source and voltage source. The standard termination
LVDS
Driver
schematic as shown in Figure 2A can be used with either type of
output structure. Figure 2B, which can also be used with both output
types, is an optional termination with center tap capacitance to help
filter common mode noise. The capacitor value should be
approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these outputs
are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
ZT
LVDS
Receiver
Figure 2A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 2B. Optional Termination
LVDS Termination
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern and
the inner edges of pad pattern for the leads to avoid any shorts.
dependent upon the package power dissipation as well as electrical
conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number
needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is
recommended to use as many vias connected to ground as possible.
It is also recommended that the via diameter should be 12 to 13mils
(0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable
to avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/slug and
the thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, refer to the Application Note on the Surface Mount
Assembly of Amkor’s Thermally/Electrically Enhance Leadframe
Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the
surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) are application specific and
SOLDER
PIN
PIN PAD
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 3. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Schematic Layout
Figure 4 shows an example of ICS844246DI-08 application
schematic. The schematic example focuses on functional
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS844246DI provides
separate VDD, VDDA and VDDO pins to isolate any high speed
switching noise at the outputs from coupling into the internal PLL.
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure the
logic control inputs are properly set. Input and output
terminations shown are intended as examples only and may
not represent the exact user configuration.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
In this example an 18pF parallel resonant 25MHz crystal is used with
load caps C7 = C6 = 22pF. The load caps are recommended for
frequency accuracy, but these may be adjusted for different board
layouts. Crystals with different load capacities may be used, but the
load capacitors will have to be changed accordingly. If different
crystal types are used, please consult IDT for recommendations.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example shows two different LVDS output
terminations; the standard termination 100 shunt termination for an
LVDS compliant receiver and an AC coupled termination for a
non-LVDS differential receiver. The AC coupled termination requires
that the designer select the values of R4 and R6 in order to center the
LVDS swing within the common mode range of the receiver. In
addition the designer must make sure that the target receiver will
operate reliably with the LVDS swing, which is reduced relative to
other logic families such as HCSL or LVPECL.
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Logic Control Input Examples
VD D
Set Logic
Input to '1'
Set Logic
Input to '0'
VDD
RU1
1K
RU 2
No t I nstall
To Logic
Input
pins
3. 3V
To Logic
Input
pins
RD1
N ot Inst all
F B1
2
RD 2
1K
1
BLM18BB221SN 1
R 5 10
C2
10uF
C1
0.1uF
C3
10 uF
VD D
P l ac e 0 .1 u F b yp a ss c a ps
d i re c tl y a dj a ce n t to th e
c o rr e sp on d in g V D D an d V D DA
p i ns .
12
F B_SEL
PLL_BYPASS
9
15
18
N _SEL0
N _SEL1
10
3. 3V
C5
0.1uF
VDDA
VDD
U1
11
C4
0. 1uF
VDD A
F B2
2
1
BLM18BB221SN 1
VDD O
VDD O
C9
10uF
1
2
F B_ SEL
C14
0.1uF
PLL_BYPASS
C 11
0.1uF
N_SEL0
N_SEL1
C8
0.1uF
P l ac e 0 .1 u F b yp as s c a p d ir e ct ly
a d ja ce n t t o t he V D DO pi n s.
Z o = 50 O hm
8
Q0
7
nQ 0
6
Q1
5
nQ 1
4
Q2
3
nQ 2
24
Q3
23
nQ 3
22
Q4
21
nQ 4
20
Q5
19
nQ 5
Q0
nQ0
R1
100
+
Z o = 50 O hm
-
13
Q1
XTAL_IN
nQ1
25MHz (18pf )
14
LVDS Termination
XTAL_OU T
X1
C7
22pF
LVD S R eceiv er
Q2
C6
22pF
nQ2
Q3
nQ3
Q4
nQ4
Q5
VC C _Receiv er
0.1u
R4
C10
0. 01uF
R2
50
+
-
R6
R3
50
C 13
R eceive r
Z o = 50 O hm
0.1u
EPAD
GND
Z o = 50 O hm
(Select R4 and R6 to center the LVDS swing in the
common mode center of the Receiver.)
25
17
16
GND
nQ5
C 12
Alte rnat e AC cou pled LVD S Te rmin atio n
to n on-L VDS Rece iver .
Figure 4. ICS844246DI Application Schematic
ICS844246DGI REVISION A NOVEMBER 28, 2012
14
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844246DI.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844246DI is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (170mA + 10mA) = 623.7mW
•
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 100mA = 346.5mW
Total Power_MAX = 623.7mW + 346.5mW = 970.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.970W * 32.1°C/W = 116.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 24 Lead TSSOP, E-Pad Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS844246DGI REVISION A NOVEMBER 28, 2012
0
1
2.5
32.1°C/W
25.5°C/W
24.0°C/W
15
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Reliability Information
Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP, E-Pad
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
32.1°C/W
25.5°C/W
24.0°C/W
Transistor Count
The transistor count for ICS844246DI is: 3887
ICS844246DGI REVISION A NOVEMBER 28, 2012
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©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP, E-Pad
Table 9. Package Dimensions for 24 Lead TSSOP, E-Pad)
Symbol
N
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
P
P1
bbb
All Dimensions in Millimeters
Minimum
Nominal
24
0.05
0.85
0.19
0.19
0.09
0.09
7.70
4.30
0.50
5.0
3.0
0°
Maximum
0.90
0.22
0.127
6.40 Basic
4.40
0.65 Basic
0.60
1.10
0.15
0.95
0.30
0.25
0.20
0.16
7.90
4.50
0.70
5.5
3.2
8°
0.076
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS844246DGI REVISION A NOVEMBER 28, 2012
17
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Ordering Information
Table 10. Ordering Information
Part/Order Number
844246DGILF
844246DGILFT
Marking
ICS844246DGIL
ICS844246DGIL
ICS844246DGI REVISION A NOVEMBER 28, 2012
Package
“Lead-Free” 24 Lead TSSOP, E-Pad
“Lead-Free” 24 Lead TSSOP, E-Pad
18
Shipping Packaging
Tube
Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
Revision History Sheet
Rev
A
Table
Page
7
Description of Change
Date
Phase Noise Plot - corrected font arrow characters.
ICS844246DGI REVISION A NOVEMBER 28, 2012
19
11/28/2012
©2012 Integrated Device Technology, Inc.
ICS844246DI Data Sheet
FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER
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