844246DGLF

FemtoClock® Crystal-to-LVDS Frequency Synthesizer w/Integrated Fanout Buffer ICS844246D DATA SHEET General Description Features The ICS844246D is a Crystal-to-LVDS Clock Synthesizer/Fanout Buffer designed for Fibre Channel frequencies and Gigabit Ethernet applications. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 26.5625MHz crystal for a Fibre Channel. The low phase noise characteristics of the ICS844246D make it an ideal clock for these demanding applications. • • • • • Six LVDS output pairs • • • Full 3.3V or mixed 3.3V core, 2.5V output supply modes Crystal oscillator interface Output frequency range: 50MHz to 333.3333MHz Crystal input frequency range: 25MHz to 33.333MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.416ps (typical) 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Select Function Table Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0 0 0 20 2 10 0 0 1 20 4 5 0 1 0 20 5 4 0 1 1 20 8 2.5 (default) 1 0 0 24 3 8 1 0 1 24 4 6 1 1 0 24 6 4 1 1 1 24 12 2 Pin Assignment Block Diagram Q0 nQ0 PLL_BYPASS Pullup Q1 1 XTAL_IN OSC PLL 0 N Output Divider XTAL_OUT nQ1 Q2 nQ2 Q3 M Feedback Divider nQ3 Q4 FB_SEL Pulldown nQ4 N_SEL0 Pullup Q5 N_SEL1 Pullup ICS844246DG REVISION A OCTOBER 20, 2011 VDDO VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS VDDA VDD FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 GND GND N_SEL0 XTAL_OUT XTAL_IN ICS844246D 24-Lead TSSOP, E-Pad 4.4mm x 7.8mm x 0.925mm package body G Package Top View nQ5 1 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Table 1. Pin Descriptions Number Name 1, 2 VDDO Power Type Description Output supply pins. 3, 4 nQ2, Q2 Output Differential output pair. LVDS interface levels. 5, 6 nQ1, Q1 Output Differential output pair. LVDS interface levels. 7, 8 nQ0, Q0 Output Differential output pair. LVDS interface levels. 9 PLL_BYPASS Input 10 VDDA Power Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, bypasses the PLL. LVCMOS / LVTTL interface levels. Analog supply pin. 11 VDD Power Core supply pin. Pullup 12 FB_SEL Input 13 14 XTAL_IN, XTAL_OUT Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Input 15, 18 N_SEL0, N_SEL1 Input 16, 17 GND Power Power supply ground. 19, 20 nQ5, Q5 Output Differential output pair. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS844246DG REVISION A OCTOBER 20, 2011 Test Conditions 2 Minimum Typical Maximum Units ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Function Tables Table 3. Crystal Function Table Inputs Function XTAL (MHz) FB_SEL N_SEL1 N_SEL0 M VCO (MHz) N Output Frequency (MHz) 25 0 0 0 20 500 2 250 25 0 0 1 20 500 4 125 25 0 1 0 20 500 5 100 25 0 1 1 20 500 8 62.5 25 1 0 0 24 600 3 200 25 1 0 1 24 600 4 150 25 1 1 0 24 600 6 100 25 1 1 1 24 600 12 50 26.5625 0 1 0 20 531.25 5 106.25 26.5625 1 0 0 24 637.5 3 212.5 26.5625 1 0 1 24 637.5 4 159.375 26.5625 1 1 0 24 637.5 6 106.25 26.5625 1 1 1 24 637.5 12 53.125 30 0 0 0 20 600 2 300 30 0 0 1 20 600 4 150 30 0 1 0 20 600 5 120 30 0 1 1 20 600 8 75 31.25 0 0 0 20 625 2 312.5 31.25 0 0 1 20 625 4 156.25 31.25 0 1 0 20 625 5 125 31.25 0 1 1 20 625 8 78.125 33.3333 0 0 0 20 666.6667 2 333.3333 33.3333 0 0 1 20 666.6667 4 166.6667 33.3333 0 1 0 20 666.6667 5 133.3333 33.3333 0 1 1 20 666.6667 8 83.3333 ICS844246DG REVISION A OCTOBER 20, 2011 3 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 32.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.10 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 170 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 100 mA Table 4B. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.10 3.3 VDD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 165 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 98 mA ICS844246DG REVISION A OCTOBER 20, 2011 Test Conditions 4 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VDD = 3.465V VIL Input Low Voltage VDD = 3.465V IIH Input High Current IIL Input Low Current Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V N_SEL[0:1], PLL_BYPASS VDD = VIN = 3.465V or 2.625V 5 µA FB_SEL VDD = VIN = 3.465V or 2.625V 150 µA N_SEL[0:1], PLL_BYPASS VDD = 3.465V or 2.625V, VIN = 0V -150 µA FB_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical 247 1.10 Maximum Units 454 mV 100 mV 1.50 V 120 mV Maximum Units 454 mV 100 mV 1.50 V 120 mV Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical 247 1.10 Table 5. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 33.333 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Mode of Oscillation Typical Fundamental Frequency 25 NOTE: Characterized using an 18pF parallel resonant crystal. ICS844246DG REVISION A OCTOBER 20, 2011 5 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER AC Electrical Characteristics Table 6A. LVDS AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK PLL Lock Time Test Conditions Minimum PLL_BYPASS = 0 50 Typical 25MHz crystal, PLL_BYPASS = 1 (default) 3.125 125MHz, Integration Range: 1.875MHz – 20MHz 0.416 20% to 80% Maximum Units 333.33 MHz MHz 0.56 ps 45 ps 220 380 ps 45 55 % 25 ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: See Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. Table 6B. LVDS AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK PLL Lock Time Test Conditions Minimum PLL_BYPASS = 0 50 Typical 25MHz crystal, PLL_BYPASS = 1 (default) 3.125 125MHz, Integration Range: 1.875MHz – 20MHz 0.416 20% to 80% Maximum Units 333.33 MHz MHz 0.56 ps 45 ps 220 380 ps 45 55 % 25 ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: See Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. ICS844246DG REVISION A OCTOBER 20, 2011 6 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Noise Power dBc Hz Typical Phase Noise at 125MHz Offset Frequency (Hz) ICS844246DG REVISION A OCTOBER 20, 2011 7 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Parameter Measurement Information 3.3V±5% 2.5V±5% SCOPE 3.3V±5% POWER SUPPLY + Float GND – VDD, VDDO VDD Qx SCOPE Qx VDDA + + VDDO VDDA nQx – POWER SUPPLY Float GND nQx 3.3V Core/2.5V LVDS Output Load AC Test Circuit 3.3V Core/3.3V LVDS Output Load AC Test Circuit nQ0:nQ5 nQx Q0:Q5 Qx t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Skew Noise Power Phase Noise Plot nQ0:nQ5 80% 80% VOD Q0:Q5 20% 20% tR tF f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter Output Rise/Fall Time ICS844246DG REVISION A OCTOBER 20, 2011 8 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Parameter Measurement Information, continued VDD VDD out 100 ➤ DC Input LVDS VOD/∆ VOD out out ➤ LVDS ➤ DC Input ➤ out ➤ VOS/∆ VOS ➤ Offset Voltage Setup Differential Output Voltage Setup Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. ICS844246DG REVISION A OCTOBER 20, 2011 9 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and changing R2 to 50Ω. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS844246DG REVISION A OCTOBER 20, 2011 10 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 2A can be used with either type of output structure. Figure 2B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO • Z T ZT LVDS Receiver Figure 2A. Standard Termination LVDS Driver Z O • ZT C ZT 2 LVDS ZT Receiver 2 Figure 2B. Optional Termination LVDS Termination ICS844246DG REVISION A OCTOBER 20, 2011 11 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD Figure 3. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) ICS844246DG REVISION A OCTOBER 20, 2011 12 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Schematic Layout Figure 4 shows an example of ICS844246D schematic. In this example, the device is operated at VDD = VDDO = 3.3V. An 18pF parallel resonant 25MHz to 33.33MHz crystal is used. The load capacitance C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. 0.1uf capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844246D provides separate power supplies to isolate noise from coupling into the internal PLL. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the VD DO V DDO C6 0.1uF V DD VD DA R2 10 C 3 10uF C4 0. 1u V DD U1 1 2 nQ2 3 Q2 4 nQ1 5 Q1 6 nQ0 7 Q0 8 PLL_BY PASS 9 10 11 FB_SEL 12 Q0 VD DO VD DO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BY PAS S VD DA VD D FB _SE L Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 GN D GN D N_SEL0 XTAL_OU T XTAL_I N 24 23 22 21 20 19 18 17 16 15 14 13 1 2 muRat a, B LM18BB221SN 1 C9 C8 0. 1uF VD D 10uF FB2 1 2 muRat a, B LM18BB221S N1 C11 C10 0. 1uF - N_SEL0 25MH z -33.33MH z X1 3.3V FB1 nQ0 C1 22pF C2 22pF Q5 VDD O Zo_D if f = 100 Ohm 10uF Logic Control Input Examples Set Logic Input to '1' V DD RU1 1K Set Logic Input to '0' V DD RD1 Not I nst all R3 50 C12 0. 1uF R4 50 nQ5 + - Alternate LVDS Termination R U2 N ot I nst all To Logic Input pins R1 100 LVDS Terminat ion 25 3.3V Zo_D if f = 100 Ohm N_SEL1 F p 8 1 C5 0. 1uF + Q3 nQ3 Q4 nQ4 VDD= VDDO=3.3V GND C7 0. 1uF To Logic Input pins R D2 1K Figure 4. ICS844246D Application Schematic ICS844246DG REVISION A OCTOBER 20, 2011 13 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS844246D. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844246D is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (170mA + 10mA) = 623.7mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 100mA = 346.5mW Total Power_MAX = 623.7mW + 346.5mW = 970.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.970W * 32.1°C/W = 101.14°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 24 Lead TSSOP, E-Pad Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS844246DG REVISION A OCTOBER 20, 2011 0 1 2.5 32.1°C/W 25.5°C/W 24.0°C/W 14 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Reliability Information Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP, E-Pad θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.1°C/W 25.5°C/W 24.0°C/W Transistor Count The transistor count for ICS844246D is: 3887 ICS844246DG REVISION A OCTOBER 20, 2011 15 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 9. Package Dimensions for 24 Lead TSSOP, E-Pad Symbol N A A1 A2 b b1 c c1 D E E1 e L P P1 α ααα bbb All Dimensions in Millimeters Minimum Nominal Maximum 24 1.10 0.05 0.15 0.85 0.90 0.95 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.127 0.16 7.70 7.90 6.40 Basic 4.30 4.40 4.50 0.65 Basic 0.50 0.60 0.70 5.0 5.5 3.0 3.2 0° 8° 0.076 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS844246DG REVISION A OCTOBER 20, 2011 16 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER Ordering Information Table 10. Ordering Information Part/Order Number 844246DGLF 844246DGLFT Marking ICS844246DGLF ICS844246DGLF Package “Lead-Free” 24 Lead TSSOP, E-Pad “Lead-Free” 24 Lead TSSOP, E-Pad Shipping Packaging Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS844246DG REVISION A OCTOBER 20, 2011 17 ©2011 Integrated Device Technology, Inc. ICS844246D Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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