848004AGILF

PRELIMINARY ICS848004I FEMTOCLOCKS™ LVCMOS/CRYSTAL-TOSSTL_2 FREQUENCY SYNTHESIZER General Description Features The ICS848004I is a 4 output SSTL_2 Synthesizer optimized to generate Fibre Channel reference clock HiPerClockS™ frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz. The ICS848004I uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS848004I is packaged in a small 24-pin TSSOP package. • • Four SSTL_2 differential clock output pairs • Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz • • VCO range: 560MHz – 680MHz • SSTL operating voltage supply ranges: VDD / VDDO 3.0V – 3.6V / 3.0V to 3.6V 2.3V – 3.6V / 2.3V – 2.7V 2.3V – 3.6V / 1.7V – 1.9V • • -40°C to 85°C ambient operating temperature ICS Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (637kHz – 10MHz): 0.80ps (typical) Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Frequency Select Function Table Inputs Input Frequency (MHz) F_SEL1 F_SEL0 M Div. Value N Div. Value M/N Div. Value Output Frequency (MHz) 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 23.4375 0 0 24 3 8 187.5 Block Diagram Pin Assignment 2 F_SEL[1:0] Pulldown nPLL_SEL Pulldown Q0 TEST_CLK Pulldown 1 F_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 1 26.5625MHz XTAL_IN OSC 0 VCO 637.5MHz Phase Detector (w/26.5625MHz Reference) XTAL_OUT nQ0 Q1 nQ1 0 Q2 nXTAL_SEL Pulldown M = 24 (fixed) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VDDO Q3 nQ3 GND nc nXTAL_SEL TEST_CLK GND XTAL_IN XTAL_OUT nQ2 ICS848004I Q3 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View nQ3 MR Pulldown nQ1 Q1 VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD F_SEL1 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT™ / ICS™ SSTL_2 FREQUENCY SYNTHESIZER 1 ICS848004AGI REV. B MAY 8, 2008 ICS848004I FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER PRELIMINARY Table 1. Pin Descriptions Number Name Type Description 1, 2 nQ1, Q1 Output Differential output pair. SSTL_2 interface levels. 3, 22 VDDO Power Output supply pins. 4, 5 Q0, nQ0 Output Differential output pair. SSTL_2 interface levels. 6 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go LOW and the inverted outputs nQx to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 7 nPLL_SEL Input Pulldown Selects between the PLL and TEST_CLK as input to the dividers. When LOW, selects PLL (PLL enabled). When HIGH, deselects the reference clock (PLL bypassed). LVCMOS/LVTTL interface levels. 8, 18 nc Unused 9 VDDA Power 10, 12 F_SEL0. F_SEL1 Input 11 VDD Power Core supply pin. 13, 14 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. 15, 19 GND Power Power supply ground. 16 TEST_CLK Input Pulldown Single-ended test clock input. LVCMOS/LVTTL interface levels. 17 nXTAL_SEL Input Pulldown Selects between the single-ended TEST_CLK or crystal interface as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects crystal inputs. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. SSTL_2 interface levels. 23, 24 Q2, nQ2 Output Differential output pair. SSTL_2 interface levels. No connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ IDT™ / ICS™ SSTL_2 FREQUENCY SYNTHESIZER Test Conditions 2 Minimum Typical Maximum Units ICS848004AGI REV. B MAY 8, 2008 ICS848004I FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD O + 0.5V Package Thermal Impedance, θJA 82.3°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 10%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.97 3.3 3.63 V VDDA Analog Supply Voltage 2.97 3.3 3.63 V VDDO Output Supply Voltage 2.97 3.3 3.63 V IDD Power Supply Current 65 mA IDDA Analog Supply Current 7 mA IDDO Output Supply Current 12 mA Table 3B. Power Supply DC Characteristics, VDD = 3.3V ± 10% or 2.5V ± 10%, VDDO = 2.5V ± 10%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Core Supply Voltage 2.25 3.3 3.63 V VDDA Analog Supply Voltage 2.25 3.3 3.63 V VDDO Output Supply Voltage 2.25 2.5 2.75 V IDD Power Supply Current 64 mA IDDA Analog Supply Current 7 mA IDDO Output Supply Current 12 mA IDT™ / ICS™ SSTL_2 FREQUENCY SYNTHESIZER Test Conditions 3 ICS848004AGI REV. B MAY 8, 2008 ICS848004I FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER PRELIMINARY Table 3C. Power Supply DC Characteristics, VDD = 3.3V ± 10% or 2.5V ± 10%, VDDO = 1.8V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.25 3.3 3.63 V VDDA Analog Supply Voltage 2.25 3.3 3.63 V VDDO Output Supply Voltage 1.71 1.8 1.89 V IDD Power Supply Current 62 mA IDDA Analog Supply Current 7 mA IDDO Output Supply Current 12 mA Table 3D. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VDD = 3.3V VIL Input Low Voltage IIH Input High Current TEST_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL VDD = VIN = 3.63V or 2.75V IIL Input Low Current TEST_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL VDD = 3.63V or 2.75V, VIN = 0V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 150 µA -5 µA Table 3E. Differential DC Characteristics, VDD = VDDO = 3.3V ± 10%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Output Differential Voltage 0.7 VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1 0.5 VDDO – 0.85 V VOH Output High Voltage; NOTE 2 >2.1 V VOL Output Low Voltage; NOTE 2 1.77 V VOL Output Low Voltage; NOTE 2 1.19 V VOL Output Low Voltage; NOTE 2