ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock
Generator. The device has 2 banks of 4 outputs and each
bank can be independently selected for ÷1 or ÷2 frequency
operation. Each bank also has its own power supply pins so
that the banks can operate at the following different voltage
levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/
LVTTL outputs are designed to drive 50Ω series or parallel
terminated transmission lines.
• Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)
• Selectable differential CLK1, nCLK1 or
LVCMOS clock input
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types:
LVCMOS, LVTTL
The divide select inputs, DIV_SELA and DIV_SELB, control the
output frequency of each bank. The output banks can be
independently selected for ÷1 or ÷2 operation. The bank enable
inputs, CLK_ENA and CLK_ENB, support enabling and disabling
each bank of outputs individually. The CLK_ENA and CLK_ENB
circuitry has a synchronizer to prevent runt pulses when
enabling or disabling the clock outputs. The master reset
input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the
active and high impedance states of all outputs. This pin has
an internal pull-up resistor and is normally used only for test
purposes or in systems which use low power modes.
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Glitchless, asynchronous clock enable/disable
• Output skew: 105ps (maximum) @ 3.3V core/3.3V output
• Bank skew: 70ps (maximum) @ 3.3V core/3.3V output
• 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating
supply
• -40°C to 85°C ambient operating temperature
The ICS87008I is characterized to operate with the core at 3.3V
or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,
output, and part-to-part skew characteristics make the 87008I
ideal for those clock applications demanding well-defined
performance and repeatability.
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
nMR/OE
DIV_SELA
CLK1
nCLK1
1
÷1
1
CLK0
0
÷2
0
4
QA0:QA3
LE
CLK_ENA
D
CLK_SEL
1
4
24
23
22
21
20
19
18
17
16
15
14
13
CLK0
CLK_SEL
VDDOB
QB0
QB1
GND
QB2
QB3
VDDOB
DIV_SELB
CLK_ENB
nMR/OE
LE
ICS87008I
D
24-Lead TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
DIV_SELB
87008AGI
1
2
3
4
5
6
7
8
9
10
11
12
QB0:QB3
0
CLK_ENB
CLK1
nCLK1
VDDOA
QA0
QA1
GND
QA2
QA3
VDDOA
DIV_SELA
CLK_ENA
VDD
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1
REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
CLK1
Input
Pulldown Non-inver ting differential clock input.
2
nCLK1
Input
Pullup/
Inver ting differential clock input. VDD/2 default when left floating.
Pulldown
VDDOA
Power
Output Bank A supply pins.
Output
Bank A outputs. LVCMOS / LVTTL interface levels.
Power
3, 9
Type
Description
6, 19
QA0, QA1,
QA2, QA3
GND
10
DIV_SELA
Input
Pullup
11
CLK_ENA
Input
Pullup
12
VDD
Power
13
nMR/OE
Input
Pullup
14
CLK_ENB
Input
Pullup
15
DIV_SELB
Input
Pullup
16, 22
VDDOB
QB3, QB2,
QB1, QB0
Power
Supply ground.
Controls frequency division for Bank A outputs.
LVCMOS / LVTTL interface levels.
Output enable for Bank A outputs. Active HIGH.
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Power supply pin.
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the
outputs to high impedance. LVCMOS / LVTTL interface levels.
Output enable for Bank B outputs. Active HIGH.
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS / LVTTL interface levels..
Output Bank B supply pins.
Output
Bank B outputs. LVCMOS / LVTTL interface levels.
4, 5, 7, 8
17, 18, 20, 21
23
CLK_SEL
Input
24
CLK0
Input
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
Power Dissipation
Capacitance (per output)
CPD
51
18
pF
VDD, VDDOx = 2.625V; NOTE 1
20
pF
VDD = 3.465, VDDOx = 2.625V; NOTE 1
20
pF
VDD = 3.465, VDDOx = 1.89V; NOTE 1
30
pF
20
pF
VDD = 2.625, VDDOx = 1.89V; NOTE 1
Output Impedance
ROUT
kΩ
VDD, VDDOx = 3.465V; NOTE 1
7
Ω
NOTE 1: VDDOx denotes VDDOA and VDDOB.
TABLE 3. FUNCTION TABLE
nMR/OE
0
Inputs
CLK_ENx
X
DIV_SELx
X
Bank X
Hi Z
1
1
1
1
1
0
0
1
X
Active
Active
Low
87008AGI
Outputs
Qx Frequency
N/A
fIN/2
fIN
N/A
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
70°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Power Supply Voltage
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
2.375
2.5
2.625
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
1.71
1.8
VDDOA,
VDDOB
Output Supply Voltage; NOTE 1
1.89
V
IDD
Power Supply Current
54
mA
IDDOA, IDDOB
Output Supply Current; NOTE 2
6.5
mA
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
VIH
VIL
IIH
Input
High Voltage
Input
Low Voltage
Input
High Current
Test Conditions
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE, CLK_SEL
CLK0
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE, CLK_SEL
CLK0
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE
CLK0, CLK_SEL
IIL
VOH
Input
Low Current
Minimum Typical
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
5
µA
150
µA
VDD = VIN = 3.465V,
VDD = VIN = 2.625V
VDD = VIN = 3.465V,
VDD = VIN = 2.625V
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE
VDD = 3.465V, VIN = 0V
VDD = 2.625V, VIN = 0V
-150
µA
CLK0, CLK_SEL
VDD = 3.465V, VIN = 0V
VDD = 2.625V, VIN = 0V
-5
µA
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IOZL
Output Tristate Current Low
VDDOx = 3.3V ± 5%; NOTE 2
2.6
V
VDDOx = 2.5V ± 5%; NOTE 2
1.8
V
VDDOx = 1.8V ± 5%; NOTE 2
1.5
V
VDDOx = 3.3V ± 5%; NOTE 2
0.5
V
VDDOx = 2.5V ± 5%; NOTE 2
0.5
V
VDDOx = 1.8V ± 5%; NOTE 2
0.4
-5
V
µA
Output Tristate Current High
5
µA
IOZH
NOTE 1: Outputs terminated with 50Ω to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuits.
NOTE 2: VDDOx denotes VDDOA, and VDDOB.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDD = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
nCLK1
IIH
Input High Current
CLK1
nCLK1
IIL
Input Low Current
CLK1
Minimum
Typical
VIN = VDD = 3.465V,
VIN = VDD = 2.625V
VIN = VDD = 3.465V,
VIN = VDD = 2.625V
VIN = 0V, VDD = 3.465V,
VIN = 0V, VDD = 2.625V
VIN = 0V, VDD = 3.465V,
VIN = 0V, VDD = 2.625V
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Units
5
µA
150
µA
-150
µA
-5
µA
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VCMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
VPP
Maximum
1.3
V
VDD - 0.85
V
REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
X
Symbol Parameter
fMAX
Output Frequency
tpLH
Propagation Delay,
Low to High
t sk(b)
Test Conditions
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Bank Skew; NOTE 2, 6
Minimum
Typical
Maximum
Units
250
MHz
1.9
3.5
5.1
ns
3.0
3.7
4.5
ns
70
ps
t sk(o)
Output Skew; NOTE 3, 6
105
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 4, 6
650
ps
tR / tF
Output Rise/Fall Time
20% to 80%
300
1100
ps
odc
Output Duty Cycle
f ≤ 133MHz
45
55
%
tEN
Output Enable Time; NOTE 5
10
ns
tDIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
ns
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
X
Symbol Parameter
fMAX
Output Frequency
tpLH
Propagation Delay,
Low to High
t sk(b)
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Bank Skew; NOTE 2, 6
t sk(o)
Output Skew; NOTE 3, 6
t sk(pp)
Par t-to-Par t Skew; NOTE 4, 6
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
2.0
3.8
5.5
ns
3
4
5
ns
35
ps
130
ps
1
ns
tR / tF
Output Rise/Fall Time
20% to 80%
300
1000
ps
odc
Output Duty Cycle
f ≤ 125MHz
45
55
%
tEN
Output Enable Time; NOTE 5
10
ns
tDIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
ns
87008AGI
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
X
Symbol Parameter
fMAX
Output Frequency
tpLH
Propagation Delay,
Low to High
t sk(b)
Test Conditions
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Bank Skew; NOTE 2, 6
Minimum
Typical
Maximum
Units
250
MHz
2.25
3.6
5.0
ns
3.1
3.8
4.4
ns
60
ps
t sk(o)
Output Skew; NOTE 3, 6
130
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 4, 6
900
ps
tR / tF
Output Rise/Fall Time
20% to 80%
290
950
ps
odc
Output Duty Cycle
f ≤ 133MHz
45
55
%
tEN
Output Enable Time; NOTE 5
10
ns
tDIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
ns
TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±5%, TA = -40°C TO 85°C
X
Symbol Parameter
fMAX
Output Frequency
tpLH
Propagation Delay,
Low to High
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
t sk(b)
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Bank Skew; NOTE 2, 6
3.0
4.5
4.9
ns
3.3
4.1
5.0
ns
55
ps
t sk(o)
Output Skew; NOTE 3, 6
150
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 4, 6
1.1
ns
tR / tF
Output Rise/Fall Time
20% to 80%
280
850
ps
odc
Output Duty Cycle
f ≤ 133MHz
45
55
%
tEN
Output Enable Time; NOTE 5
10
ns
tDIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
ns
87008AGI
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±5%, TA = -40°C TO 85°C
X
Symbol Parameter
fMAX
Test Conditions
Minimum
Typical
Output Frequency
Maximum
Units
250
MHz
t sk(b)
CLK0; NOTE 1A
Propagation Delay,
CLK1, nCLK1;
Low to High
NOTE 1B
Bank Skew; NOTE 2, 6
t sk(o)
Output Skew; NOTE 3, 6
t sk(pp)
Par t-to-Par t Skew; NOTE 4, 6
1.2
ns
tR / tF
Output Rise/Fall Time
20% to 80%
325
900
ps
odc
Output Duty Cycle
f ≤ 100MHz
45
55
%
tEN
Output Enable Time; NOTE 5
tpLH
2.6
4.1
5.6
ns
3.3
4.4
5.4
ns
45
ps
150
ps
10
ns
tDIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
ns
87008AGI
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.25V±5%
1.65V±5%
SCOPE
VDD,
VDDOA, VDDOB
LVCMOS
Qx
Qx
LVCMOS
GND
GND
-1.25V±5%
-1.65V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
SCOPE
VDD,
VDDOA, VDDOB
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V±5% +0.9V±5%
1.25V±5%
SCOPE
VDD
VDDOA, VDDOB
LVCMOS
SCOPE
V DD
VDDOA, VDDOB
Qx
GND
GND
-0.9V±5%
-1.25V±5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V±5% +0.9V±5%
VDD
SCOPE
V DD
VDDOA, VDDOB
LVCMOS
Qx
LVCMOS
nCLK1
V
Qx
PP
Cross Points
V
CMR
CLK1
GND
GND
-0.9V±5%
2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
87008AGI
DIFFERENTIAL INPUT LEVEL
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PART 1
V
V
DDOX
DDOX
Qx
Qx
2
PART 2
V
V
DDOX
DDOX
Qy
2
Qy
2
t sk(pp)
2
t sk(o)
OUTPUT SKEW
PART-TO-PART SKEW
VDD
2
CLK0
nCLK1
VDDOX
2
QX0:QX0
CLK1
VDDOX
2
QX0:QX0
VDDOX
2
QAx,QBx,
QCx, QDx
t sk(b)
➤
BANK SKEW (where X denotes outputs in the same bank)
tPD
➤
PROPAGATION DELAY
V
80%
DDOX
80%
QAx, QBx,
QCx, QDx
Clock
Outputs
20%
20%
tR
2
t PW
t
tF
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
87008AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
VCC
R1
1K
Single Ended Clock Input
R1
1K
CLK
CLK_IN
+
V_REF
nCLK
V_REF
C1
0.1u
R2
1K
C1
0.1uF
-
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can
be tied from PCLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet
the VPP and VCMR input requirements. Figures 2A to 2E show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
nCLK
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
LVPECL
HiPerClockS
Input
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 2A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 2B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
R3
125
3.3V
R4
125
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
Zo = 50 Ohm
nCLK
Receiv er
R2
84
FIGURE 2C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
87008AGI
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
70°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
200
63°C/W
500
60°C/W
TRANSISTOR COUNT
The transistor count for ICS87008I is: 1262
87008AGI
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ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
FOR
24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
24
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
87008AGI
ICS87008AGI
24 Lead TSSOP
tray
-40°C to 85°C
87008AGIT
ICS87008AGI
24 Lead TSSOP
1000 tape & reel
-40°C to 85°C
87008AGILF
ICS87008AGILF
24 Lead "Lead-Free" TSSOP
tray
-40°C to 85°C
87008AGILFT
ICS87008AGILF
24 Lead "Lead-Free" TSSOP
1000 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
T8
14
10
14
Ordering Information Table - added "T" (for tape and reel) Part/Order Number.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking, and note.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
9/10/04
A
B
87008AGI
T8
T8
14
16
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15
2/21/06
7/31/10
REV. B JULY 31, 2010
ICS87008I
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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