8702BYLFT

ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8702 is a low skew, ÷1, ÷2 Differential-toLVCMOS Clock Generator and a member of the HiPerClockS™ HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS/LVTTL levels. True or inverting, single-ended to LVCMOS translation can be achieved with a resistor bias on the nCLK or CLK inputs, respectively. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. • Twenty LVCMOS outputs, 7Ω typical output impedance ICS • One differential clock input pair • CLK, nCLK supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Translates any differential input signal (LVPECL, LVHSTL, LVDS) to LVCMOS levels without external bias networks • Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously. • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 200ps (maximum) • Bank skew: 150ps (maximum) • Part-to-part skew: 650ps (maximum) The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability. • Multiple frequency skew: 250ps (maximum) • 3.3V or mixed 3.3V input, 2.5V output operating supply modes • 0°C to 70°C ambient operating temperature • Other divide values available on request • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM ÷1 1 ÷2 0 GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND CLK nCLK PIN ASSIGNMENT QA0:QA4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4 DIV_SELA 1 QB0:QB4 0 DIV_SELB 1 QC0:QC4 0 DIV_SELC 1 QD0:QD4 0 ICS8702 QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0 DIV_SELA DIV_SELB CLK nCLK VDD BANK_EN0 GND BANK_EN1 VDD nMR/OE DIV_SELC DIV_SELD DIV_SELD nMR/OE BANK_EN0 BANK_EN1 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Bank Enable Logic 48-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View 8702BY www.icst.com/products/hiperclocks.com 1 REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Description Number Name Type 2, 5, 11, 26, 32, 35, 41, 44 VDDO Power Output supply pins. Output power supply. 7, 9, 18, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 GND Power VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK Power 21 nCLK Output Output Output Output Input Input Positive supply pins. Bank A outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. Bank B outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. Bank C outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. Bank D outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Controls frequency division for Bank D outputs. 13 DIV_SELD Input Pullup LVCMOS/LVTTL interface levels. Controls frequency division for Bank C outputs. 14 DIV_SELC Input Pullup LVCMOS/LVTTL interface levels. Controls frequency division for Bank B outputs 23 DIV_SELB Input Pullup LVCMOS/LVTTL interface levels. Controls frequency division for Bank A outputs. Pullup 24 DIV_SELA Input LVCMOS/LVTTL interface levels. Enables and disables outputs by banks. BANK_EN1, Pullup 17, 19 Input LVCMOS/LVTTL interface levels. BANK_EN0 Master Reset and output enable. When HIGH, output drivers are enabled. When LOW, output drivers are in HiZ and dividers are 15 nMR/OE Input Pullup reset. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP RPULLDOWN Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance CPD ROUT 8702BY Test Conditions Minimum Typical Maximum 4 51 51 VDD = VDDO = 3.465V www.icst.com/products/hiperclocks.com 2 pF kΩ kΩ 15 7 Units pF Ω REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 3A. CONTROL INPUT FUNCTION TABLE nMR/OE 0 1 1 1 1 1 1 1 1 Inputs BANK_EN1 BANK_EN0 X X 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0:QA4 Hi Z Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled QB0:QB4 Hi Z Hi Z Enabled Enabled Enabled Hi Z Enabled Enabled Enabled Outputs QC0:QC4 Hi Z Hi Z Hi Z Enabled Enabled Hi Z Hi Z Enabled Enabled QD0:QD4 Hi Z Hi Z Hi Z Hi Z Enabled Hi Z Hi Z Hi Z Enabled Qx Frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN TABLE 3B. CLOCK INPUT FUNCTION TABLE nMR/OE 1 Inputs CLK 0 nCLK 1 Outputs Qx0:Qx4 LOW Input to Output Mode Polarity Differential to Single Ended Non Inver ting 1 1 0 HIGH Differential to Single Ended Non Inver ting 1 0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inver ting 1 1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inver ting 1 Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inver ting 1 Biased; NOTE 1 1 LOW Single Ended to Single Ended Inver ting NOTE 1: Please refer to the Application Information section, which discusses "Wiring the Differential Input to Accept Single Ended Levels". 8702BY www.icst.com/products/hiperclocks.com 3 REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C Symbol VDD VDDO Parameter Positive Supply Voltage Output Supply Voltage IDD Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 Units V V 95 mA Maximum 3.465 2.625 Units V V 95 mA Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol VDD VDDO Parameter Positive Supply Voltage Output Supply Voltage IDD Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 TABLE 4C. LVCMOS /LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH VOL 8702BY Test Conditions DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE Minimum VDD = VIN = 3.465V Typical VDD = 3.465V, VIN = 0V -150 µA Output High Voltage VDD = VDDO = 3.135V IOH = -36mA 2.6 V Output Low Voltage VDD = VDDO = 3.135V IOL = 36mA www.icst.com/products/hiperclocks.com 4 0.5 V REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage VOL Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 µA VDD = 3.135V VDDO = 2.375V 1.9 V IOL = -27mA VDD = 3.135V VDDO = 2.375V IOL = 27mA Output Low Voltage 0.5 V Maximum Units TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA =0°C TO 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical CLK VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 nCLK VDD = 3.465V, VIN = 0V -150 www.icst.com/products/hiperclocks.com 5 µA 0.15 1.3 V 1.8 2.4 V 1.3 V DCM, LVHSTL, LVDS, SSTL Levels 0.31 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V. 8702BY µA REV. D OCTOBER 28, 2008 Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum f ≤ 200MHz Typical Maximum Units 250 MHz tPD Propagation Delay; NOTE 1 3.5 ns t sk(b) Bank Skew; NOTE 2, 7 Measured on rising edge atVDDO/2 150 ps t sk(o) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge atVDDO/2 200 ps Measured on rising edge atVDDO/2 250 ps Measured on rising edge atVDDO/2 650 ps t sk(w) t sk(pp) 2.2 tR Output Rise Time; NOTE 6 30% to 70% 280 850 ps tF Output Fall Time; NOTE 6 30% to 70% Output Duty Cycle 850 tCYCLE/2 + 0.5 3 ps odc 280 tCYCLE/2 - 0.5 2 f ≤ 200MHz tCYCLE/2 f = 200MHz 2.5 Output Enable Time; tEN f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 8702BY www.icst.com/products/hiperclocks.com 6 ns ns ns ns REV. D OCTOBER 28, 2008 Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum f ≤ 200MHz Typical Maximum Units 250 MHz tPD Propagation Delay; NOTE 1 3.6 ns t sk(b) Bank Skew; NOTE 2, 7 Measured on rising edge atVDDO/2 150 ps t sk(o) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge atVDDO/2 200 ps Measured on rising edge atVDDO/2 250 ps Measured on rising edge atVDDO/2 700 ps t sk(w) t sk(pp) 2.3 tR Output Rise Time; NOTE 6 30% to 70% 280 850 ps tF Output Fall Time; NOTE 6 30% to 70% Output Duty Cycle 850 tCYCLE/2 + 0.5 3 ps odc 280 tCYCLE/2 - 0.5 2 f ≤ 200MHz f = 200MHz tCYCLE/2 2.5 Output Enable Time; f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. tEN 8702BY www.icst.com/products/hiperclocks.com 7 ns ns ns ns REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDO Qx LVCMOS SCOPE VDD, VDDO Qx LVCMOS GND GND -1.165V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT VDD V DDO Qx 2 nCLK V Cross Points PP V V CMR DDO CLK Qy 2 tsk(o) GND DIFFERENTIAL INPUT LEVEL Part 1 OUTPUT SKEW nCLK V DDO Qx 2 CLK Part 2 V QA0:QA4, QB0:QB4, QC0:QC4, QD0:QD4 DDO Qy 2 tsk(pp) PART-TO-PART SKEW QA0:QA4, QB0:QB4, QC0:QC4, QD0:QD4 PD PROPAGATION DELAY VDDO VDDO VDDO 2 2 2 t PW Clock Outputs t PERIOD odc = 70% 70% tR tF 30% 30% t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIIOD 8702BY VDDO 2 t OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.com 8 REV. D OCTOBER 28, 2008 Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 8702BY www.icst.com/products/hiperclocks.com 9 REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR POWER CONSIDERATIONS For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer. DRIVER TERMINATION For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination. RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 48 LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8702 is: 1746 8702BY www.icst.com/products/hiperclocks.com 10 REV. D OCTOBER 28, 2008 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX FOR 48 LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL 8702BY MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.com 11 REV. D OCTOBER 28, 2008 Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number 8702BY 8702BYT 8702BYLF 8702BYLFT NOTE: Par ts that are ordered Marking Package Shipping Packaging Temperature ICS8702BY 48 Lead LQFP tray 0°C to 70°C ICS8702BY 48 Lead LQFP 1000 tape & reel 0°C to 70°C ICS8702BYLF 48 Lead "Lead-Free" LQFP tray 0°C to 70°C ICS8702BYLF 48 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8702BY www.icst.com/products/hiperclocks.com 12 REV. D OCTOBER 28, 2008 Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev C Table 4A 4D 4B 4E C 1 B Page 4 6 4 6 11 2 10 1 2 D 8702BY T2 9 12 Description of Change Revised IDD row from 70mA Maximum to 95mA Maximum. Revised IDD row from 70mA Maximum to 95mA Maximum. Revised VIH row from 3.8 Maximum to VDD + 0.3 Maximum. Revised VIH row from 3.8 Maximum to VDD + 0.3 Maximum. Added Power Dissipation and Driver Termination notes. Pin Description Table revised nMR/OE description. Updated Output Rise/Fall Time Diagram. Format changes. Features Section added Lead-Free bullet. Pin Characteristics Table - changed CIN 4pF max to 4pF typical. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free par t number, marking, and note. Updated datasheet layout. www.icst.com/products/hiperclocks.com 13 Date 8/2/01 11/28/01 8/21/02 1/17/06 REV. D OCTOBER 28, 2008