87339AMI-11LFT

ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87339I-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock GenHiPerClockS™ erator/Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87339I-11 has one differential clock input pair. The CLK, nCLK pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS87339I-11 ideal for clock distribution applications demanding well defined performance and repeatability. • Output skew: 35ps (maximum) ICS • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input • Part-to-part skew: 385ps (maximum) • Bank skew: Bank A - 20ps (maximum) Bank B - 20ps (maximum) • Propagation delay: 2.1ns (maximum) • LVPECL mode operating voltage supply range: VCC = 3V to 3.6V, VEE = 0V • Available in both standard (RoHS5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT DIV_SELA QA0 nQA0 nCLK_EN D ÷2, ÷4 Q R LE QA1 nQA1 CLK nCLK QB0 nQB0 ÷4, ÷5, ÷6 R QB1 nQB1 MR VCC nCLK_EN DIV_SELB0 CLK nCLK RESERVED MR VCC DIV_SELB1 DIV_SELA 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 VEE ICS87339I-11 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View DIV_SELB0 20-Lead SOIC, 300MIL 7.5mm x 12.8mm x 2.25mm package body M Package Top View DIV_SELB1 87339AGI-11 1 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 8, 20 VCC Power 2 nCLK_EN Input 3 DIV_SELB0 Input 4 CLK Input 5 6 nCLK RESERVED Input Reser ve Description Positive supply pins. Pulldown Clock enable. LVCMOS / LVTTL interface levels. See Table 3. Selects divide value for Bank B outputs as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Reser ve pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go 7 MR Input Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects divide value for Bank B outputs as described in Table 3. 9 DIV_SELB1 Input Pulldown LVCMOS / LVTTL interface levels. Selects divide value for Bank A outputs as described in Table 3. 10 DIV_SELA Input Pulldown LVCMOS / LVTTL interface levels. Power Negative supply pin. 11 VEE 12, 13 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 18, 19 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 87339AGI-11 Test Conditions 2 Minimum Typical Maximum Units REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs Outputs MR nCLK_EN DIV_SELA DIV_SELB0 DIV_SELB1 QA0, QA1 nQA0, nQA1 QB0, QB1 nQB0, nQB1 1 X X X X 0 1 X X X 0 0 0 0 0 LOW Not Switching ÷2 HIGH Not Switching ÷2 LOW Not Switching ÷4 HIGH Not Switching ÷4 0 0 0 0 1 ÷2 ÷2 ÷5 ÷5 0 0 0 1 0 ÷2 ÷2 ÷6 ÷6 0 0 0 1 1 ÷2 ÷2 ÷5 ÷5 0 0 1 0 0 ÷4 ÷4 ÷4 ÷4 0 0 1 0 1 ÷4 ÷4 ÷5 ÷5 0 0 1 1 0 ÷4 ÷4 ÷6 ÷6 0 0 1 1 1 ÷4 ÷4 ÷5 ÷5 NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge. CLK tRR MR Q (÷n) FIGURE 1A. MR TIMING DIAGRAM Enabled Disabled CLK nCLK nCLK_EN QAx, QBx nQAx, nQBx FIGURE 1B. NCLK_EN TIMING DIAGRAM 87339AGI-11 3 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 20 Lead TSSOP 20 Lead SOIC 73.2°C/W (0 lfpm) 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical 3.0 3.3 Maximum Units 3.6 V 105 mA Maximum Units 2 VCC + 0.3 V -0.3 0.8 V 150 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions nCLK_EN, MR, DIV_SELA, DIV_SELBx nCLK_EN, MR, DIV_SELA, DIV_SELBx Minimum Typical VIN = VCC = 3.6V VIN = 0V, VCC = 3.6V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions nCLK Minimum Typical VIN = VCC = 3.6V Units 5 µA 150 µA CLK VIN = VCC = 3.6V nCLK VIN = 0V, VCC = 3.6V -150 µA CLK VIN = 0V, VCC = 3.6V -5 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 87339AGI-11 Maximum 4 1.3 V VCC - 0.85 V REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Output High Voltage; NOTE1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V VOH NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter fCLK Clock Input Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 5 t sk(b) Bank Skew; NOTE 3, 5 t sk(pp) Par t-to-Par t Skew; NOTE 4, 5 Test Conditions Minimum CLK to Q (Diff) 1. 6 Typical 15 Maximum Units 1 GHz 2.1 ns 35 ps Bank A 10 20 ps Bank B 10 20 ps 385 ps tS Setup Time nCLK_EN to CLK 350 ps tH Hold Time CLK to nCLK_EN 100 ps t RR Reset Recover y Time tPW Minimum Pulse Width tR / tF Output Rise/Fall Time 400 CLK 550 20% to 80% 100 odc Output Duty Cycle 48 All data taken with outputs ÷4. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points NOTE 3: Defined as skew within a bank of outputs and with equal load conditions. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 87339AGI-11 5 ps ps 600 ps 52 % REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V V CC VCC, VCCO Qx SCOPE nCLK V LVPECL V Cross Points PP CMR CLK nQx VEE VEE -1.3V ± 0.3V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nQAx 80% 80% QAx VSW I N G Clock Outputs nQBx 20% 20% tF tR QBx tsk(b) OUTPUT RISE/FALL TIME BANK SKEW nCLK nQAx, nQBx CLK nQAx, nQBx QAx, QBx QAx, QBx Pulse Width t t odc = PD PERIOD t PW t PERIOD PROPAGATION DELAY 87339AGI-11 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 6 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 87339AGI-11 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION 7 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 87339AGI-11 BY 8 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS87339I-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS87339I-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 105mA = 378mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.6V, with all outputs switching) = 378mW + 120mW = 498mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.498W * 66.6°C/W = 118.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6A. Thermal Resistance θJA for 20-pin TSSOP, Forced Convection θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 6B. Thermal Resistance θJA for 20-pin SOIC, Forced Convection θ by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W 200 500 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 87339AGI-11 9 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 87339AGI-11 10 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TSSOP TABLE θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW SOIC TABLE θ by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W 200 500 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87339I-11 is: 1745 Compatible with MC10EP139, MC100EP139 87339AGI-11 11 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP PACKAGE OUTLINE - M SUFFIX Millimeters MIN N 20 LEAD SOIC TABLE 8B. PACKAGE DIMENSIONS TABLE 8A. PACKAGE DIMENSIONS SYMBOL FOR Millimeters SYMBOL Minimum MAX N 20 A Maximum 20 -- 2.65 A -- 1.20 A1 0.05 0.15 A1 0.10 -- 2.05 2.55 0.33 0.51 A2 0.80 1.05 A2 b 0.19 0.30 B c 0.09 0.20 C 0.18 0.32 6.60 D 12.60 13.00 E 7.40 7.60 D 6.40 E E1 6.40 BASIC 4.30 e e 4.50 H 0.65 BASIC 1.27 BASIC 10.00 10.65 L 0.45 0.75 h 0.25 0.75 α 0° 8° L 0.40 1.27 aaa -- 0.10 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 Reference Document: JEDEC Publication 95, MO-153 87339AGI-11 12 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS87339AGI-11 ICS87339AI11 20 lead TSSOP Tube -40°C to 85°C ICS87339AGI-11T ICS87339AI11 20 lead TSSOP 2500 Tape & Reel -40°C to 85°C ICS87339AGI-11LF ICS7339AI11L 20 Lead "Lead-Free" TSSOP Tube -40°C to 85°C ICS87339AGI-11LFT ICS7339AI11L 20 Lead "Lead-Free" TSSOP 2500 Tape & Reel -40°C to 85°C ICS87339AMI-11 ICS87339AMI-11 20 lead SOIC Tube -40°C to 85°C ICS87339AMI-11T ICS87339AMI-11 20 lead SOIC 1000 Tape & Reel -40°C to 85°C ICS87339AMI-11LF ICS7339AI11L 20 Lead "Lead-Free" SOIC Tube -40°C to 85°C ICS87339AMI-11LFT ICS7339AI11L 20 Lead "Lead-Free" SOIC 1000 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 87339AGI-11 13 REV. A March 3, 2009 ICS87339I-11 LOW SKEW, ÷2/4,÷4/5/6, DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table A T1 Page 1 2 T9 T9 1 13 13 A A 87339AGI-11 Description of Change Pin Assignment - changed pin 6, "nc" to "reser ved". Pin Description table - corrected pin 6 to read reser ved to coordinate with Pin Assignment. Features section - corrected Output skew and Par t-to-Par t skew bullets. Ordering Information table - added Lead-Free note. Ordering Information table - added Lead-Free markings 14 Date 3/10/05 4/12/05 12/19/07 REV. A March 3, 2009