8735AM-21LF

ICS8735-21 700MHz, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Features • One differential 3.3V LVPECL output pair One differential feedback output pair • • Differential CLK/nCLK input pair • • • • Output frequency range: 31.25MHz to 700MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • • • • • Cycle-to-cycle jitter: 25ps (maximum) CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Input frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz External feedback for “zero delay” clock regeneration with configurable frequencies Static phase offset: 50ps ± 100ps Full 3.3V supply voltage 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignments CLK nCLK MR VCC nFB_IN FB_IN SEL2 VEE nQFB QFB Block Diagram nc PLL FB_IN Pulldown nFB_IN Pullup 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 nc QFB nQFB nc 1 nc SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCCO Q nQ ICS8735-21 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View VEE CLK Pulldown nCLK Pullup 0 20 19 18 17 16 15 14 13 12 11 SEL3 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 Q nQ 1 2 3 4 5 6 7 8 9 10 VCCA PLL_SEL Pullup VCC The ICS8735-21 is a highly versatile 1:1 DifferentialICS to-3.3V LVPECL clock generator and a member of HiPerClockS™ the HiPerClockS™family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS8735-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. PLL_SEL General Description 32 31 30 29 28 27 26 25 SEL0 SEL1 nc nc SEL0 Pulldown CLK SEL1 Pulldown nCLK 1 24 ICS8735-21 23 32-Lead VFQFN 3 22 5mm x 5mm x 0.925mm 4 21 package body 5 20 K Package 6 19 Top View 2 VCCO nc Q nQ QFB nQFB 7 18 nc MR 8 17 VCCO IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 1 nc nc VEE SEL2 FB_IN 10 11 12 13 14 15 16 nFB_IN MR Pulldown 9 nc nc SEL3 Pulldown VCC SEL2 Pulldown ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Name CLK Type Input Pulldown Description Non-inverting differential clock input. nCLK Input Pullup Inverting differential clock input. nFB_IN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with “zero delay.” FB_IN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks with “zero delay.” MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output nQ to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. SEL0, SEL1, SEL2, SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. PLL_SEL Input Pullup PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. nQ, Q Output Differential output pair. LVPECL interface levels. nQFB, QFB Output Differential feedback output pair. LVPECL interface levels. VEE Power Negative supply pin. VCC Power Core supply pins. VCCA Power Analog supply pin. VCCO Power Output supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 2 Minimum Typical Maximum Units ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Function Tables Table 3A. Control Input Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q/nQ, QFB/nQFB 0 0 0 0 250 - 700 ÷1 0 0 0 1 125 - 350 ÷1 0 0 1 0 62.5 - 175 ÷1 0 0 1 1 31.25 - 87.5 ÷1 0 1 0 0 250 - 700 ÷2 0 1 0 1 125 - 350 ÷2 0 1 1 0 62.5 - 175 ÷2 0 1 1 1 250 - 700 ÷4 1 0 0 0 125 - 350 ÷4 1 0 0 1 250 - 700 ÷8 1 0 1 0 125 - 350 x2 1 0 1 1 62.5 - 175 x2 1 1 0 0 31.25 - 87.5 x2 1 1 0 1 62.5 - 175 x4 1 1 1 0 31.25 - 87.5 x4 1 1 1 1 31.25 - 87.5 x8 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 3 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q/nQ, QFB/nQFB 0z 0 0 0 ÷4 0 0 0 1 ÷4 0 0 1 0 ÷4 0 0 1 1 ÷8 0 1 0 0 ÷8 0 1 0 1 ÷8 0 1 1 0 ÷16 0 1 1 1 ÷16 1 0 0 0 ÷32 1 0 0 1 ÷64 1 0 1 0 ÷2 1 0 1 1 ÷2 1 1 0 0 ÷4 1 1 0 1 ÷1 1 1 1 0 ÷2 1 1 1 1 ÷1 IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 4 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 20 Lead SOIC 32 Lead VFQFN 46.2°C/W (0 lfpm) 37.0°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 150 mA ICCA Analog Supply Current 15 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V SEL[0:3], MR VCC = VIN = 3.465V 150 µA PLL_SEL VCC = VIN = 3.465V 5 µA SEL[0:3], MR VCC = 3.465V, VIN = 0V -5 µA PLL_SEL VCC = 3.465V, VIN = 0V -150 µA IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 5 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Table 4C. Differential DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units CLK, FB_IN VCC = VIN = 3.465V 150 µA nCLK, nFB_IN VCC = VIN = 3.465V 5 µA CLK, FB_IN VCC = 3.465V, VIN = 0V -5 µA nCLK, nFB_IN VCC = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V VEE + 0.5 VCC – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO – 1.4 VCCO – 0.9 V VCCO – 2.0 VCCO – 1.7 V 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. Table 5. Input Frequency Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter fIN Input Frequency Test Conditions Minimum PLL_SEL = 1 31.25 Typical Maximum Units 700 MHz 700 MHz CLK, nCLK IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR PLL_SEL = 0 6 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR AC Electrical Characteristics Table 6. AC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tsk(Ø) Static Phase Offset; NOTE 3, 4 tjit(cc) Test Conditions PLL_SEL = 0V, f ≤ 700MHz Minimum Typical 3.0 PLL_SEL = 0V Maximum Units 700 MHz 4.2 ns 20 ps 150 ps Cycle-to-Cycle Jitter; NOTE 3, 5 25 ps tjit(θ) Phase Jitter; NOTE 3, 5, 6 ±50 ps tL PLL Lock Time tR / tF Output Rise/Fall Time; NOTE 7 odc Output Duty Cycle PLL_SEL = 3.3V 20% to 80% @ 50MHz -50 50 1 ms 300 700 ps 47 53 % NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 5: Characterized at VCO frequency of 622MHz. NOTE 6: Phase jitter is dependent on the input source used. IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 7 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 2V VCC VCC, VCCA, VCCO Qx SCOPE nCLK V V Cross Points PP CMR CLK LVPECL nQx VEE VEE 1.3V± 0.165V Differential Input Level 3.3V Output Load AC Test Circuit nCLK VOH nQx CLK VOL Qx nFB_IN VOH FB_IN VOL Qy ➤ ➤ t(Ø) nQy tsk(o) Output Skew Phase Jitter and Static Phase Offset nQ, nQFB 80% 80% VSW I N G Q, QFB ➤ tcycle n ➤ tcycle n+1 Clock Outputs ➤ ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Cycle-to-Cycle Jitter IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 20% 20% tR tF Output Rise/Fall Time 8 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued nQ, nQFB nCLK Q, QFB t PW CLK t PERIOD nQ, nQFB odc = t PW x 100% Q, QFB t PERIOD tPD Output Duty Cycle/Pulse Width/Period Propagation Delay Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. FB_IN/nFB_IN Inputs For applications not requiring the use of the differential input, both FB_IN and nFB_IN can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from FB_IN to ground. IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 9 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8735-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VCC .01µF 10Ω .01µF 10µF VCCA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 10 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK HiPerClockS Input LVPECL R1 84 R2 84 Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Zo = 50Ω Receiver LVDS Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 11 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FOUT 50Ω VCC - 2V Zo = 50Ω RTT 84Ω Figure 4A. 3.3V LVPECL Output Termination IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR FIN 84Ω Figure 4B. 3.3V LVPECL Output Termination 12 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Schematic Example Figure 5 shows a schematic example of the ICS8735-21. In this example, the input is driven by an HCSL driver. The zero delay buffer is configured to operate at 155.52MHz input and 77.75MHz output. The logic control pins are configured as follows: SEL [3:0] = 0101; PLL_SEL = 1 The decoupling capacitors should be physically located near the power pin. For ICS8735-21. 3.3V R7 Zo = 50 Ohm U1 (155.5 MHz) 1 2 3 4 5 6 7 8 9 10 VCC Zo = 50 Ohm SEL2 HCSL R8 50 R9 50 VCC VCCA CLK nCLK MR VCCI nFB_IN FB_IN SEL2 VEE nQFB QFB nc SEL1 SEL0 VCCI PLL_SEL VCCA SEL3 VCCO Q nQ 20 19 18 17 16 15 14 13 12 11 C11 0.01u SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCC 10 C16 10u Zo = 50 Ohm + Zo = 50 Ohm VCC RU3 1K R1 50 RU4 1K RU5 SP RU6 1K RD4 SP RD5 1K RD6 SP ICS8735-21 - (77.75 MHz) RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 RD3 SP R2 50 RD7 1K SP = Space (i.e. not intstalled) LVPECL_input R4 50 R3 50 Bypass capacitors located near the power pins (U1-4) VCC VCC=3.3V C1 0.1uF SEL[3:0] = 0101, Divide by 2 (U1-17) C2 0.1uF R5 50 R6 50 (U1-13) C3 0.1uF Figure 5. ICS8735-21 LVPECL Buffer Schematic Example IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 13 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 14 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS8735-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8735-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 150mA = 519.8mW • Power (outputs)MAX = 30mW/Loaded output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX = (3.465V, with all outputs switching) = 519.8mW + 60mW = 579.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 83.2°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.580W * 83.2°C/W = 118.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7A. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection θJA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 7B. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W 15 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 16 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Reliability Information Table 8A. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 8B. θJA vs. Air Flow Table for a 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W Transistor Count The transistor count for ICS8735-21 is: 2969 Package Outline and Package Dimensions Package Outline - M Suffix for 20 Lead SOIC Table 9A. Package Dimensions for 20 Lead SOIC 300 Millimeters All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 Basic H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 7° Reference Document: JEDEC Publication 95, MS-013, MS-119 IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 17 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e D2 2 N &N Odd 0. 08 C Th er mal Ba se D2 C The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9B below. Table 9B. Package Dimensions for 32 Lead VFQFN JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 18 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 8735AM-21 8735AM-21T 8735AM-21LF 8735AM-21LFT 8735AK-21LF 8735AK-21LFT Marking ICS8735AM-21 ICS8735AM-21 ICS8735AM-21LF ICS8735AM-21LF ICS8735A21L ICS8735A21L Package 20 Lead SOIC 20 Lead SOIC “Lead-Free” 20 Lead SOIC “Lead-Free” 20 Lead SOIC “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Tray 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 19 ICS8735AM-21 REV. A JULY 31, 2008 ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA