8735-31
1:5, Differential-to-3.3V LVPECL Zero
Delay Clock Generator
Data Sheet
General Description
Features
The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL
Clock Generator. The 8735-31 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 15.625MHz to 350MHz. The reference
divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
•
•
•
Five differential 3.3V LVPECL output pairs
•
•
•
•
Output frequency range: 15.625MHz to 350MHz
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
•
•
•
•
•
Cycle-to-cycle jitter: 60ps (maximum)
Selectable differential clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Input frequency range: 15.625MHz to 350MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Output skew: 35ps (maximum)
Static phase offset: 55ps ± 125ps
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
PLL
nQ4
CLK_SEL Pulldown
FB_IN Pulldown
nFB_IN Pullup
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0 Pulldown
SEL1 Pulldown
VCCO
nQ4
Q4
VEE
SEL3
23
CLK0
3
22
nQ3
nCLK0
4
21
Q2
CLK1
5
20
nQ2
nCLK1
6
19
Q1
CLK_SEL
7
18
nQ1
MR
8
17
VCCO
9
10 11 12 13 14 15 16
8735-31
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
©2016 Integrated Device Technology, Inc
SEL1
VCCO
Q3
nQ3
Q4
Q0
1
VCCO
Q3
nQ0
1
24
2
VEE
CLK1 Pulldown
nCLK1 Pullup
nQ2
1
SEL2
0
32 31 30 29 28 27 26 25
SEL0
FB_IN
nCLK0
nQ1
Q2
0
nFB_IN
÷2, ÷4, ÷8, ÷16,
÷32, ÷64, ÷128
VCC
CLK0 Pulldown
Pullup
VCC
nQ0
Q1
PLL_SEL Pullup
PLL_SEL
Q0
VCCA
Pin Assignment
Block Diagram
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Revision B January 27, 2016
8735-31 Data Sheet
Table 1. Pin Descriptions
Number
Name
1, 2,
12, 29
SEL0, SEL1,
SEL2, SEL3
Type
Input
Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
Description
3
CLK0
Input
Pulldown
Non-inverting differential clock input.
4
nCLK0
Input
Pullup
Inverting differential clock input.
5
CLK1
Input
Pulldown
6
nCLK1
Input
Pullup
Non-inverting differential clock input.
7
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1/nCLK1. When LOW, selects
CLK0/nCLK0. LVCMOS / LVTTL interface levels.
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Inverting differential clock input.
8
MR
Input
9, 32
VCC
Power
10
nFB_IN
Input
Pullup
11
FB_IN
Input
Pulldown
13, 28
VEE
Power
Negative supply pins.
14, 15
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks
with “zero delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with
“zero delay.”
16, 17, 24, 25
VCCO
Power
Output supply pins.
18, 19
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
20, 21
nQ2, Q2
Output
Differential output pair. LVPECL interface levels..
22, 23
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
26, 27
nQ4, Q4
Output
Differential output pair. LVPECL interface levels.
30
VCCA
Power
Analog supply pin.
31
PLL_SEL
Input
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
©2016 Integrated Device Technology, Inc
Test Conditions
2
Minimum
Typical
Maximum
Units
Revision B January 27, 2016
8735-31 Data Sheet
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)
Q0:Q4, nQ0:nQ4
0
0
0
0
125 - 350
÷1
0
0
0
1
62.5 - 175
÷1
0
0
1
0
31.25 - 87.5
÷1
0
0
1
1
15.625 - 43.75
÷1
0
1
0
0
125 - 350
÷2
0
1
0
1
62.5 - 175
÷2
0
1
1
0
31.25 - 87.5
÷2
0
1
1
1
125 - 350
÷4
1
0
0
0
62.5 - 175
÷4
1
0
0
1
125 - 350
÷8
1
0
1
0
62.5 - 175
x2
1
0
1
1
31.25 - 87.5
x2
1
1
0
0
15.625 - 43.75
x2
1
1
0
1
31.25 - 87.5
x4
1
1
1
0
15.625 - 43.75
x4
1
1
1
1
15.625 - 43.75
x8
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0:Q4, nQ0:nQ4
0
0
0
0
÷8
0
0
0
1
÷8
0
0
1
0
÷8
0
0
1
1
÷16
0
1
0
0
÷16
0
1
0
1
÷16
0
1
1
0
÷32
0
1
1
1
÷32
1
0
0
0
÷64
1
0
0
1
÷128
1
0
1
0
÷4
1
0
1
1
÷4
1
1
0
0
÷8
1
1
0
1
÷2
1
1
1
0
÷4
1
1
1
1
÷2
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
47.9C/W (0 lfpm)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
150
mA
ICCA
Analog Supply Current
15
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
CLK_SEL,
SEL[0:3], MR
VCC = VIN = 3.465V
150
µA
PLL_SEL
VCC = VIN = 3.465V
5
µA
CLK_SEL,
SEL[0:3], MR
VCC = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VCC = 3.465V, VIN = 0V
-150
µA
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Table 4C. Differential DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
IIH
IIL
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
FB_IN,
CLK0, CLK1
VCC = VIN = 3.465V
150
µA
nFB_IN,
nCLK0, nCLK1
VCC = VIN = 3.465V
5
µA
Input High Current
FB_IN,
CLK0, CLK1
VCC = 3.465V,
VIN = 0V
-5
µA
nFB_IN,
nCLK0, nCLK1
VCC = 3.465V,
VIN = 0V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.15
1.3
V
VEE + 0.5
VCC – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
V
VCCO – 2.0
VCCO – 1.7
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO – 2V.
Table 5. Input Frequency Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
fIN
Input Frequency
CLK0/nCLK0,
CLK1/nCLK1
©2016 Integrated Device Technology, Inc
Test Conditions
Minimum
PLL_SEL = 1
15.625
PLL_SEL = 0
6
Typical
Maximum
Units
350
MHz
700
MHz
Revision B January 27, 2016
8735-31 Data Sheet
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 3
tsk(Ø)
Static Phase Offset; NOTE 3, 4
Test Conditions
Minimum
PLL_SEL = 0, f 350MHz
3.8
PLL_SEL = 1
-70
Typical
55
Maximum
Units
350
MHz
5.1
ns
35
ps
+180
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3
60
ps
tL
PLL Lock Time
1
ms
tR / tF
Output Rise/Fall Time
200
750
ps
odc
Output Duty Cycle
47
53
%
20% to 80%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions,
when the PLL is locked and the input reference frequency is stable.
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Parameter Measurement Information
2V
VCC
VCC,
VCCA,
VCCO
Qx
SCOPE
nCLK0,
nCLK1
V
PP
Cross Points
V
CMR
CLK0,
CLK1
nQx
VEE
VEE
1.3V± 0.165V
3.3V Output Load AC Test Circuit
Differential Input Level
nCLK0,
nCLK1
CLK0,
CLK1
VOH
nQx
VOL
Qx
nFB_IN
VOH
FB_IN
VOL
Qy
➤
➤ t(Ø)
nQy
Phase Jitter and Static Phase Offset
Output Skew
nQ[0:4]
nQ[0:4]
Q[0:4]
tcycle n
tcycle n+1
Q[0:4]
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Cycle-to-Cycle Jitter
©2016 Integrated Device Technology, Inc
Output Rise/Fall Time
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Revision B January 27, 2016
8735-31 Data Sheet
Parameter Measurement Information, continued
nQ[0:4]
nCLK0,
nCLK1
Q[0:4]
CLK0,
CLK1
nQ[0:4]
Q[0:4]
tPD
Output Duty Cycle/Pulse Width/Period
Propagation Delay
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
FB_IN/nFB_IN Inputs
For applications not requiring the use of the differential input, both
FB_IN and nFB_IN can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from FB_IN to
ground.
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform- ance,
power supply isolation is required. The 8735-31 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VCC, VCCA and VCCO should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the VCCA pin. The 10 resistor can also be replaced by
a ferrite bead.
3.3V
VCC
0.01µF
VCCA
0.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
3.3V
2.5V
3.3V
3.3V
2.5V
R3
120Ω
*R3
R4
120Ω
Zo = 60Ω
CLK
CLK
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
Differential
Input
SSTL
R1
120Ω
Differential
Input
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
©2016 Integrated Device Technology, Inc
R2
120Ω
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Revision B January 27, 2016
8735-31 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 4A. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc
R2
84
Figure 4B. 3.3V LVPECL Output Termination
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Revision B January 27, 2016
8735-31 Data Sheet
Layout Guideline
guideline. The layout in the actual system will depend on the
selected component types, the density of the components, the
density of the traces, and the stacking of the P.C. board.
The schematic of the 8735-31 layout example is shown in Figure 5A.
The 8735-31 recommended PCB board layout for this example is
shown in Figure 5B. This layout example is used as a general
Figure 5A. 8735-31 LVPECL Zero Delay Buffer Schematic Example
VCC
SP = Space (i.e. not intstalled)
R7
RU2
SP
RU3
1K
RU4
1K
RU5
SP
RU6
1K
SEL[3:0] = 0101,
Divide by 2
10
C11
0.01u
CLK_SEL
PLL_SEL
SEL0
SEL1
SEL2
SEL3
RD4
SP
RD5
1K
RD6
SP
Zo = 50 Ohm
RD7
1K
+
SEL3
RD3
SP
C16
10u
(77.76 MHz)
PLL_SEL
RD2
1K
VCC
VCCA
RU7
SP
VCC
-
VCCO
Zo = 50 Ohm
SEL0
SEL1
Zo = 50 Ohm
CLK_SEL
R9
50
8735-31
VCCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
24
23
22
21
20
19
18
17
R6
50
Output
Termination
Example
Bypass capacitor located near the power pins
(U1-9)
VCC
(U1-32)
VCC=3.3V
C1
0.1uF
R10
50
R4
50
9
10
11
12
13
14
15
16
R8
50
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VCC
nFB_IN
FB_IN
SEL2
VEE
nQ0
Q0
VCCO
3.3V PECL Driv er
1
2
3
4
5
6
7
8
R5
50
32
31
30
29
28
27
26
25
(155.52 MHz)
VCC
PLL_SEL
VCCA
SEL3
VEE
Q4
nQ4
VCCO
U1
3.3V
Zo = 50 Ohm
LVPECL_input
C6
0.1uF
VCCO=3.3V
SEL2
(U1-16)
R2
50
VCCO
(U1-17)
(U1-24)
(U1-25)
R1
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
R3
50
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
clock signal traces should be routed first and should be locked
prior to routing other signal traces.
The following component footprints are used in this layout
example. All the resistors and capacitors are size 0603.
Power and Grounding
• The differential 50 output traces should have the
same length.
Place the decoupling capacitors C1, C6, C2, C4, C5, and C7, as
close as possible to the power pins. If space allows, placement of
the decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces.
Placement of vias on the traces can affect the trace
characteristic impedance and hence degrade signal
integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VCCA pin as possible.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the
board and the component location. While routing the traces, the
• Make sure no other signal traces are routed between
the clock trace pair.
• The matching termination resistors should be located
as close to the receiver input pins as possible.
GND
R7
C16
C11
C7
VCCO
C6
C5
VCC
U1
Pin 1
VCCA
VIA
50 Ohm
Traces
C4
C1
C2
Figure 5B. PCB Board Layout for 8735-31
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8735-31.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 8735-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 150mA = 519.75mW
•
Power (outputs)MAX = 30mW/Loaded output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_MAX = (3.465V, with all outputs switching) = 519.75mW + 150mW = 669.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.670W * 42.1°C/W = 98.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead LQFP, Forced Convection
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
©2016 Integrated Device Technology, Inc
16
Revision B January 27, 2016
8735-31 Data Sheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead LQFP
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for 8735-31 is: 2969
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Package Outline and Package Dimensions
Package Outline - M Suffix for 32 Lead LQFP
Table 6. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
0.20
D&E
9.00 Basic
D1 & E1
7.00 Basic
D2 & E2
5.60 Ref.
e
0.80 Basic
L
0.45
0.60
0.75
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
©2016 Integrated Device Technology, Inc
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Revision B January 27, 2016
8735-31 Data Sheet
Ordering Information
Table 10. Ordering Information
Part/Order Number
8735AY-31LF
8735AY-31LFT
Marking
ICS8735AY31LF
ICS8735AY31LF
©2016 Integrated Device Technology, Inc
Package
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
19
Shipping Packaging
Tray
Tape & Reel
Temperature
0C to 70C
0C to 70C
Revision B January 27, 2016
8735-31 Data Sheet
Revision History Sheet
Rev
Table
Page
A
T10
16
Ordering Information Table - added Lead-Free marking.
12/19/07
Added Recommendations for Unused Input and Output Pins section.
Updated Differential Clock input Interface section.
Ordering Information Table - deleted “ICS” from Part/Order Number.
2/11/08
T10
9
11
19
1
Pin Assignment -due to format conversion dated February 11, 2008 datasheet,
corrected typo on pin 19 from nQ1 to Q1 and, pin 10 from FB_IN to nFB_IN.
2/18/09
T10
19
Ordering Information - removed leaded devices.
Updated datasheet format.
7/16/15
T10
1
19
Features Section - removed reference to leaded packages.
Ordering Information - Deleted LF note below table.
Updated header and footer.
1/27/16
A
B
B
B
Description of Change
©2016 Integrated Device Technology, Inc
Date
20
Revision B January 27, 2016
8735-31 Data Sheet
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