ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8735-01 is a highly versatile 1:5 Differential-to3.3V LVPECL clock generator. The ICS8735-01 has a fully
integrated PLL and can be configured as zero delay buffer,
multiplier or divider, and has an output frequency range of
31.25MHz to 700MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows
the device to achieve “zero delay” between the input clock
and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
• Five differential 3.3V LVPECL outputs
• Selectable differential clock inputs
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: 50ps ± 100ps
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
Q3
nQ3
PLL
CLK_SEL
FB_IN
nFB_IN
Q4
nQ4
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
VCCO
1
nQ4
1
Q4
CLK1
nCLK1
Q2
nQ2
VEE
0
Q1
nQ1
SEL3
÷16, ÷32, ÷64
CLK0
nCLK0
0
VCCA
÷1, ÷2, ÷4, ÷8,
VCC
PLL_SEL
PLL_SEL
Q0
nQ0
32 31 30 29 28 27 26 25
SEL0
1
24
VCCO
SEL1
2
23
Q3
CLK0
3
22
nQ3
nCLK0
4
21
Q2
CLK1
5
20
nQ2
nCLK1
6
19
Q1
CLK_SEL
7
18
nQ1
MR
8
17
VCCO
ICS8735-01
9 10 11 12 13 14 15 16
VCCO
Q0
nQ0
VEE
SEL2
SEL2
FB_IN
SEL1
nFB_IN
VCC
SEL0
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
SEL3
MR
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
SEL0
Type
Input
Description
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
2
SEL1
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
3
CLK0
Input
Pulldown Non-inver ting differential clock input.
4
nCLK0
Input
5
CLK1
Input
6
nCLK1
Input
7
CLK_SEL
Input
8
MR
Input
9, 32
VCC
Power
10
nFB_IN
Input
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
Pulldown
When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go high.
Pulldown
When logic LOW, the internal dividers and the otuputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
11
FB_IN
Input
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
12
SEL2
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
13, 28
VEE
Power
Negative supply pins.
14, 15
16, 17,
24, 25
18, 19
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
VCCO
Power
Output supply pins.
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
20, 21
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
22, 23
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
26, 27
nQ4, Q4
Output
29
SEL3
Input
30
VCCA
Power
31
PLL_SEL
Input
Differential output pair. LVPECL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pullup
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
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Test Conditions
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2
Minimum
Typical
Maximum
Units
REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
0
0
0
0
250 - 700
÷1
0
0
0
1
125 - 350
÷1
0
0
1
0
62.5 - 175
÷1
0
0
1
1
31.25 - 87.5
÷1
0
1
0
0
250 - 700
÷2
0
1
0
1
125 - 350
÷2
0
1
1
0
62.5 - 175
÷2
Inputs
0
1
1
1
250 - 700
÷4
1
0
0
0
125 - 350
÷4
1
0
0
1
250 - 700
÷8
1
0
1
0
125 - 350
x2
1
0
1
1
62.5 - 175
x2
1
1
0
0
31.25 - 87.5
x2
1
1
0
1
62.5 - 175
x4
1
1
1
0
31.25 - 87.5
x4
1
1
1
1
31.25 - 87.5
x8
*NOTE: VCO frequency range for all configurations above is 250 to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
SEL3
SEL2
SEL1
SEL0
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
0
0
0
0
÷4
0
0
0
1
÷4
0
0
1
0
÷4
0
0
1
1
÷8
0
1
0
0
÷8
0
1
0
1
÷8
0
1
1
0
÷ 16
0
1
1
1
÷ 16
1
0
0
0
÷ 32
1
0
0
1
÷ 64
1
0
1
0
÷2
1
0
1
1
÷2
1
1
0
0
÷4
1
1
0
1
÷1
1
1
1
0
÷2
1
1
1
1
÷1
Inputs
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VCC + 0.5 V
Maximum Ratings may cause permanent damage to the
Outputs, VO
-0.5V to VCCO + 0.5V
Package Thermal Impedance, θJA
32 Lead LQFP
47.9°C/W (0 lfpm)
32 Lead VFQFN
34.8°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
VCCO
Output Supply Voltage
3.465
V
IEE
Power Supply Current
150
mA
ICCA
Analog Supply Current
15
mA
Maximum
Units
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VIN = VCC = 3.465V
150
µA
VIN = VCC = 3.465V
5
µA
IIH
IIL
Input High Current
Input Low Current
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
VIN = 0V, VCC = 3.465V
-5
µA
PLL_SEL
VIN = 0V, VCC = 3.465V
-150
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Units
CLK0, CLK1, FB_IN
VIN = VCC = 3.465V
150
µA
nCLK0, nCLK1, nFB_IN
VIN = VCC = 3.465V
5
µA
IIH
Input
High Current
IIL
Input
Low Current
VPP
Peak-to-Peak Input Voltage
CLK0, CLK1, FB_IN
VIN = 0V, VCC = 3.465V
-5
nCLK0, nCLK1, nFB_IN
VIN = 0V, VCC = 3.465V
-150
0.15
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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Maximum
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4
µA
µA
1.3
V
VCC - 0.85
V
REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fIN
Input Frequency
Test Conditions
Minimum
PLL_SEL = 1
31.25
Typical
700
MHz
700
MHz
Maximum
Units
700
MHz
4.2
150
ns
ps
Output Skew; NOTE 3, 5
25
ps
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
25
±50
ps
ps
CLK0, nCLK0,
CLK1, nCLK1
PLL_SEL = 0
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
t(Ø)
t sk(o)
t jit(cc)
t jit(θ)
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Test Conditions
PLL_SEL = 0V, f ≤ 700MHz
PLL_SEL = 3.3V
Minimum
3.4
-50
Typical
50
tL
PLL Lock Time
1
ms
tR
Output Rise Time
20% to 80% @ 50MHz
300
700
ps
tF
Output Fall Time
20% to 80% @ 50MHz
300
700
ps
odc
Output Duty Cycle
47
53
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC ,
VCCA,
VCCO
Qx
V CC
SCOPE
nCLK0,
nCLK1
LVPECL
V
VEE
V
Cross Points
PP
nQx
CMR
CLK0,
CLK1
-1.3V ± 0.165V
VEE
DIFFERENTIAL INPUT LEVEL
nQx
nQ0:nQ4
Qx
Q0:Q4
➤
nQy
tcycle
➤
3.3V OUTPUT LOAD AC TEST CIRCUIT
➤
n
tcycle n+1
➤
Qy
t jit(cc) = tcycle n –tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQ0:nQ4
80%
80%
Q0:Q4
VSW I N G
Clock
Outputs
Pulse Width
20%
20%
tR
t
tF
odc =
PERIOD
t PW
t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ4
nCLK0,
nCLK1
CLK0,
CLK1
VOH
nFB_IN
VOH
VOL
VOL
FB_IN
➤
➤ t(Ø)
Q0:Q4
tPD
tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter
t (Ø) mean = Static Phase Offset
(where t (Ø) is any random sample, and t (Ø) mean is the average
of the sampled cycles measured on controlled edges)
PROPAGATION DELAY
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PHASE JITTER & STATIC PHASE OFFSET
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
84Ω
FIGURE 1B. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet
the VPP and VCMR input requirements. Figures 3A to 3D show
interface examples for theCLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 3B.CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
Receiv er
R2
84
FIGURE 3C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
8735AY-01
nCLK
Zo = 50 Ohm
FIGURE 3D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8735-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 4 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
10Ω
.01μF
V CCA
10μF
.01μF
FIGURE 4. POWER SUPPLY FILTERING
LAYOUT GUIDELINE
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
The schematic of the ICS8735-01 layout example is shown in
Figure 5A. The ICS8735-01 recommended PCB board layout
for this example is shown in Figure 5B. This layout example is
used as a general guideline. The layout in the actual system will
VCC
SP = Space (i.e. not intstalled)
R7
RU2
SP
RU3
1K
RU4
1K
RU5
SP
RU6
1K
SEL[3:0] = 0101,
Divide by 2
10
C11
0.01u
CLK_SEL
PLL_SEL
SEL0
SEL1
SEL2
SEL3
RD4
SP
RD5
1K
RD6
SP
Zo = 50 Ohm
RD7
1K
+
SEL3
RD3
SP
C16
10u
(77.76 MHz)
PLL_SEL
RD2
1K
VCC
VCCA
RU7
SP
VCC
-
VCCO
Zo = 50 Ohm
SEL0
SEL1
Zo = 50 Ohm
CLK_SEL
R9
50
8735-01
VCCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
24
23
22
21
20
19
18
17
R6
50
Output
Termination
Example
Bypass capacitor located near the power pins
(U1-9)
VCC
(U1-32)
VCC=3.3V
C1
0.1uF
R10
50
R4
50
9
10
11
12
13
14
15
16
R8
50
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VCC
nFB_IN
FB_IN
SEL2
VEE
nQ0
Q0
VCCO
3.3V PECL Driver
1
2
3
4
5
6
7
8
R5
50
32
31
30
29
28
27
26
25
(155.52 MHz)
VCC
PLL_SEL
VCCA
SEL3
VEE
Q4
nQ4
VCCO
U1
3.3V
Zo = 50 Ohm
LVPECL_input
C6
0.1uF
VCCO=3.3V
SEL2
(U1-16)
R2
50
VCCO
(U1-17)
(U1-24)
(U1-25)
R1
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
R3
50
FIGURE 5A. ICS8735-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
The following component footprints are used in this layout
example:
of the trace and the trace delay might be restricted by the
available space on the board and the component location.
While routing the traces, the clock signal traces should be routed
first and should be locked prior to routing other signal traces.
All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
• The differential 50Ω output traces should have same
length.
Place the decoupling capacitors C1, C6, C2, C4, C5, and C7,
as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is
preferred. This can reduce unwanted inductance between the
decoupling capacitor and the power pin caused by the via.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge
or excessive ring back can cause system failure. The shape
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
R7
C16
C11
C7
VCCO
C6
C5
VCC
U1
Pin 1
VCCA
VIA
50 Ohm
Traces
C4
C1
C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8735-01
8735AY-01
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10
REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8735-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8735-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 520mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_MAX (3.465V, with all outputs switching) = 520mW + 150mW = 670mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.670W * 42.1°C/W = 98.2°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7A. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
8735AY-01
34.8C/W
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
CCO_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CCO_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
))/R ] * (V
OH_MAX
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8735AY-01
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8A. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP PACKAGE
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8C/W
TRANSISTOR COUNT
The transistor count for ICS8735-01 is: 2969
8735AY-01
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
FOR
32 LEAD LQFP
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
--ccc
Reference Document: JEDEC Publication 95, MS-026
8735AY-01
MAXIMUM
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14
0.10
REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE - K SUFFIX
FOR
32 LEAD VFQFN
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
32
N
A
0.80
1. 0
A1
0
0.05
0.25 Reference
A3
b
0.18
0.30
e
0.50 BASIC
ND
8
NE
8
5.0
D
D2
3.0
3.30
5.0
E
E2
3.0
3.30
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
8735AY-01
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REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8735AY-01
ICS8735AY-01
32 lead LQFP
tray
0°C to 70°C
8735AY-01T
ICS8735AY-01
32 lead LQFP
1000 tape & reel
0°C to 70°C
8735AY-01LF
ICS8735AY01L
32 lead "Lead Free" LQFP
tray
0°C to 70°C
8735AY-01LFT
ICS8735AY01L
32 lead "Lead Free" LQFP
1000 tape & reel
0°C to 70°C
8735AK-01
ICS8735AK-01
32 lead VFQFN
tray
0°C to 70°C
8735AK-01T
ICS8735AK-01
32 lead VFQFN
2500 tape & reel
0°C to 70°C
8735AK-01LF
ICS8735A01L
32 lead "Lead Free" VFQFN
tray
0°C to 70°C
8735AK-01LFT
ICS8735A01L
32 lead "Lead Free" VFQFN
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
8735AY-01
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16
REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
B
T5
5
C
T4 A
4
t(Ø) row changed Parameter name from PLL Reference Zero Delay to
Static Phase Offset.
tjit(θ) row changed 85 Max. to ±50 Max.
Added ICCA row.
T3A
T6
Figure 11
1
3
5
10
Updated Block Diagram.
Added note at end of the table.
Added Note 6.
Revised Figure 11, LVPECL Zero Delay Buffer Schematic Example
10
2
6
Added Termination for LVPECL Outputs section
Pin Description Table - revised MR description.
3.3V Output Load Test Circuit Diagram, revised VEE equation from
"-1.3V ± 0.135V" to " -1.3V ± 0.165V".
Revised Output Rise/Fall Time Diagram.
C
C
C
C
T2
C
D
E
E
10/30/01
11/1/01
11/19/01
12/3/01
6/3/02
8/19/02
8
5
T6
5
AC Table - changed tPD from 3.6 min. to 3.4 min, deleted 3.9 typical.
T1
2
Updated VCC pin description to read Core supply pins from Positive supply pins.
T4A
4
Updated VCC to read Core Supply Voltage from Positive Supply Voltage.
IEE, deleted 100mA typical and added 150mA Maximum.
T1
2
8
T2
F
T10
2
8
1
16
T4D
5
G
11 - 12
T10
16
T9B
15
18
G
LVPECL table - corrected VSWING from 0.9 max. to 1.0 max.
9/17/02
12/3/02
Updated format.
Pin Description Table - updated MR description.
1/31/03
Corrected LVPECL Zero Delay Buffer Schematic Example.
Add 32 Lead VFQFN package throughout data sheet.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added Differential Clock Input Interface Application Section.
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free par t number.
11/12/04
12/22/04
LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO
- 0.9V.
Power Considerations - corrected power dissipation to reflect VOH max in Table
4D.
Updated datasheet's header/footer with IDT from ICS.
Ordering Information Table - removed ICS prefix from Par t/Order Number
column. Added lead-free VFQFN marking.
VFQFN Package Dimensions Table - corrected dimensions D2/E2.
Added Contact Page.
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17
Date
10/12/01
T4D
F
8735AY-01
Description of Change
tPD row changed the Test Condtions from 0MHz < f ≤ 700MHz to f ≤ 700MHz.
4/13/07
11/12/10
REV. G NOVEMBER 12, 2010
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
8735AY-01
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