Low Skew, 1-to-5, Differential-to-3.3V
LVPECL/ECL Fanout Buffer
8735BI-01
DATA SHEET
General Description
Features
The 8735BI-01 is a highly versatile 1:5 Differential- to-3.3V LVPECL
clock generator. The 8735BI-01 has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is
routed around the PLL and into the internal output dividers.
Block Diagram
•
•
•
Five differential 3.3V LVPECL output pairs
•
•
•
•
Output frequency range: 31.25MHz to 700MHz
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
•
•
•
•
•
Static phase offset: 200ps (maximum)
Selectable differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: 50ps (maximum)
Output skew: 55ps (maximum)
3.3V output operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Q0
nQ0
Q1
PLL_SEL Pullup
CLK0 Pulldown
nCLK0 Pullup
CLK1 Pulldown
nCLK1 Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
nQ1
Q2
0
0
nQ2
1
Q3
nQ3
Q4
1
PLL
nQ4
CLK_SEL Pulldown
FB_IN Pulldown
nFB_IN Pullup
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1: 8
SEL0 Pulldown
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
8735BI-01 REVISION 1 04/02/15
1
©2015 Integrated Device Technology, Inc.
8735BI-01 DATA SHEET
VCC
PLL_SEL
VCCA
SEL3
VEE
Q4
nQ4
VCCO
VCC
PLL_SEL
VCCA
SEL3
VEE
Q4
nQ4
VCCO
Pin Assignments
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
SEL0
1
24
VCCO
SEL0
1
24
VCCO
SEL1
2
23
Q3
SEL1
2
23
Q3
CLK0
3
22
nQ3
CLK0
3
22
nQ3
nCLK0
4
21
Q2
nCLK0
4
21
Q2
CLK1
5
20
nQ2
CLK1
5
20
nQ2
nCLK1
6
19
Q1
nCLK1
6
19
Q1
CLK_SEL
7
18
nQ1
CLK_SEL
7
18
nQ1
MR
8
17
VCCO
MR
8
17
VCCO
nFB_IN
FB_IN
SEL2
VEE
nQ0
Q0
VCCO
16
VCCO
16
15
Q0
15
14
nQ0
14
13
VEE
13
12
SEL2
12
11
FB_IN
11
10
nFB_IN
10
9
VCC
9
VCC
8735BI-01
8735BI-01
32-pin, 5mm x 5mm VFQFN Package
32-pin, 7mm x 7mm LQFP Package
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
Name
1
SEL0
Input
Type
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Description
2
SEL1
Input
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
3
CLK0
Input
Pulldown
Non-inverting differential clock input.
4
nCLK0
Input
Pullup
5
CLK1
Input
Pulldown
6
nCLK1
Input
Pullup
7
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
8
MR
Input
9
VCC
Power
10
nFB_IN
Input
Pullup
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
11
FB_IN
Input
Pulldown
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
12
SEL2
Input
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
13
VEE
Power
Negative power supply pins.
14
nQ0
Output
Differential output pair. LVPECL interface levels.
15
Q0
Output
Differential output pair. LVPECL interface levels.
16
VCCO
Power
Output supply pins.
Core supply pins.
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
2
REVISION 1 04/02/15
8735BI-01 Data Sheet
Number
Name
Type
Description
17
VCCO
Power
Output supply pins.
18
nQ1
Output
Differential output pair. LVPECL interface levels.
19
Q1
Output
Differential output pair. LVPECL interface levels.
20
nQ2
Output
Differential output pair. LVPECL interface levels.
21
Q2
Output
Differential output pair. LVPECL interface levels.
22
nQ3
Output
Differential output pair. LVPECL interface levels.
23
Q3
Output
Differential output pair. LVPECL interface levels.
24
VCCO
Power
Output supply pins.
25
VCCO
Power
Output supply pins.
26
nQ4
Output
Differential output pair. LVPECL interface levels.
27
Q4
Output
Differential output pair. LVPECL interface levels.
28
VEE
Power
Negative power supply pins.
29
SEL3
Input
30
VCCA
Power
31
PLL_SEL
Input
32
VCC
Power
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Core supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
REVISION 1 04/02/15
Test Conditions
3
Minimum
Typical
Maximum
Units
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1;
PLL Enable Mode;
Q[0:4], nQ[0:4]
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range
(MHz)*
0
0
0
0
250 - 700
÷1
0
0
0
1
125 - 350
÷1
0
0
1
0
62.5 - 175
÷1
0
0
1
1
31.25 - 87.5
÷1
0
1
0
0
250 - 700
÷2
0
1
0
1
125 - 350
÷2
0
1
1
0
62.5 - 175
÷2
0
1
1
1
250 - 700
÷4
1
0
0
0
125 - 350
÷4
1
0
0
1
250 - 700
÷8
1
0
1
0
125 - 350
x2
1
0
1
1
62.5 - 175
x2
1
1
0
0
31.25 - 87.5
x2
1
1
0
1
62.5 - 175
x4
1
1
1
0
31.25 - 87.5
x4
1
1
1
1
31.25 - 87.5
x8
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Table 3B. PLL Bypass Function Table
Inputs
Outputs
SEL3
SEL2
SEL1
SEL0
PLL_SEL = 0;
PLL Bypass Mode;
Q[0:4], nQ[0:4]
0
0
0
0
÷4
0
0
0
1
÷4
0
0
1
0
÷4
0
0
1
1
÷8
0
1
0
0
÷8
0
1
0
1
÷8
0
1
1
0
÷16
0
1
1
1
÷16
1
0
0
0
÷32
1
0
0
1
÷64
1
0
1
0
÷2
1
0
1
1
÷2
1
1
0
0
÷4
1
1
0
1
÷1
1
1
1
0
÷2
1
1
1
1
÷1
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
4
REVISION 1 04/02/15
8735BI-01 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC+ 0.5V
Junction Temperature, TJ
125C
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
155
mA
ICCA
Analog Supply Current
17
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High
Current
IIL
Input Low
Current
REVISION 1 04/02/15
Test Conditions
Minimum
Typical
SEL[3:0], MR,
CLK_SEL
VCC = VIN = 3.465V
150
µA
PLL_SEL
VCC = VIN = 3.465V
5
µA
SEL[3:0], MR,
CLK_SEL
VCC = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VCC = 3.465V, VIN = 0V
-150
µA
5
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Table 4C. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
IIH
Input High
Current
IIL
Input Low
Current
Test Conditions
Minimum
Typical
Maximum
Units
FB_IN,
CLK[0:1]
VCC = VIN = 3.465V
150
µA
nFB_IN,
nCLK[0:1]
VCC = VIN = 3.465V
5
µA
FB_IN,
CLK[0:1]
VCC = 3.465V, VIN = 0V
-5
µA
nFB_IN,
nCLK[0:1]
VCC = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage;
NOTE 1
VCMR
Common Mode Input
Voltage; NOTE 1, 2
0.15
1.3
V
VEE + 0.5
VCC – 0.85
V
Maximum
Units
NOTE 1: VIL should not be less than -0.3V.
NOTE 2. Common mode voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage;
NOTE 1
VCCO – 1.4
VCCO – 0.9
V
VOL
Output Low Voltage;
NOTE 1
VCCO – 2.1
VCCO – 1.7
V
VSWING
Peak-to-Peak Output
Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50 to VCCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit.
Table 5. Input Frequency Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fIN
Input
Frequency
Test Conditions
Minimum
CLK[0:1],
nCLK[0:1]
PLL_SEL = 1
31.25
CLK[0:1],
nCLK[0:1]
PLL_SEL = 0
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
6
Typical
Maximum
Units
700
MHz
700
MHz
REVISION 1 04/02/15
8735BI-01 Data Sheet
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tPD
Propagation Delay; NOTE 1
t(Ø)
Static Phase Offset; NOTE 2, 4
tsk(o)
Test Conditions
Minimum
Typical
Maximum
Units
700
MHz
PLL_SEL = 0V, fOUT 700MHz
2.8
4.9
ns
PLL_SEL = 3.3V
-100
200
ps
Output Skew; NOTE 3, 4
55
ps
tjit(cc)
Cycle-to-Cycle Jitter: NOTE 4, 5
50
ps
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
20% to 80%
200
700
ps
fOUT 250MHz
47
53
%
1
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Characterized at VCO frequency of 622MHz.
REVISION 1 04/02/15
7
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Parameter Measurement Information
2V
VCC
VCC,
VCCA,
Qx
SCOPE
nCLK[0:1]
V
VCCO
V
Cross Points
PP
CMR
CLK[0:1]
nQx
VEE
VEE
-1.3V ± 0.165V
Differential Input Level
3.3V LVPECL Output Load AC Test Circuit
nCLK[0:1]
nQ[0:4]
CLK[0:1]
Q[0:4]
nQ[0:4]
tcycle n
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Q[0:4]
tPD
Cycle-to-Cycle Jitter
Propagation Delay
nQx
nCLK0, nCLK1
VOH
CLK0, CLK1
VOL
nFB_IN
VOH
Qx
nQy
VOL
FB_IN
➤
➤ t(Ø)
Qy
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the
average of the sampled cycles measured on controlled edges)
Static Phase Offset
Output Skew
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
tcycle n+1
8
REVISION 1 04/02/15
8735BI-01 Data Sheet
Parameter Measurement Information
nQ[0:4]
nQ[0:4]
Q[0:4]
Q[0:4
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
PLL Lock Time
REVISION 1 04/02/15
9
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V1in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set V1 at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be
100. The values of the resistors can be increased to reduce the
loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full
rail LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
10
REVISION 1 04/02/15
8735BI-01 Data Sheet
Differential Clock Input Interface
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figure 2A to Figure 2E show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
*R4
Differential
Input
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2C. CLK/nCLK Input Driven by a 3.3V LVDS Driver
REVISION 1 04/02/15
11
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
FB_IN/nFB_IN Inputs
For applications not requiring the use of the differential feedback
input, both FB_IN and nFB_IN can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
FB_IN to ground.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figure 3A and Figure 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 3A. Figure 4A. 3.3V LVPECL Output Termination
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
R2
84
Figure 3B. Figure 4B. 3.3V LVPECL Output Termination
12
REVISION 1 04/02/15
8735BI-01 Data Sheet
Schematic Layout
Figure 4 (next page) shows an example 8735BI-01 application
schematic in which the device operates at VCC = 3.3V.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
VCCA bead and the 0.01uF capacitor in each power pin filter should
be placed on the device side. The other components can be on the
opposite side of the PCB. Pull-up and pull-down resistors to set
configuration pins can all be placed on the PCB side opposite the
device side to free up device side area if necessary.
This example focuses on functional connections is shown configured
as a zero delay buffer. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set for the application.
In addition to the standard LVDS termination shown for CLK0,
nCLK0, this example shows four different LVPECL terminations; the
standard Thevenin equivalent termination on Q0, a T or Wye
termination on CLK1, nCLK1, the PI or Wye equivalent of the T on
Q3, nQ3 and an AC coupled termination to the standard IDT CLK,
nCLK clock buffer input biased by a 51k resistor on the CLK input
and either a 51k pull down on nCLK or a 51k pull-down and a
51k pull-up on nCLK.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8735BI-01 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
REVISION 1 04/02/15
For additional layout recommendations and guidelines, contact
clocks@idt.com.
13
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
+3.3V
VC C
C2
0.01uF
FB 2
1
2
16
V CCO
30
VC C A
B LM18BB221SN 1 C 4
+3. 3V
VC C
U1
V CC
9
32
C1
0. 01uF
C3
0. 01uF
VC C A
C5
10uF
17
0. 01uF
MR
C LK_SE L
PLL_SE L
V CCO
8
7
31
C6
0.01uF
MR
C LK_S EL
PLL_S EL
Place each 0.01uF bypass
cap directly adjacent
to its corresponding
VCC, VCCA or VCCO pin.
24
V CCO
1
2
12
29
SE L0
SE L1
SE L2
SE L3
C7
0.01uF
SE L0
SE L1
SE L2
SE L3
V CCO
25
3.3V
C8
3
Zo = 50 Ohm
0.01uF
C LK0
R2
130
R4
R3
130
Z o = 50 Ohm
Zo = 50 Ohm
100
Q0
15
+
4
nC LK0
Z o = 50 Ohm
LV D S D r iv er
nQ0
14
-
Zo = 50 Ohm
C LK1
Q1
nQ1
nC LK1
Q2
nQ2
5
R 14 50
Zo = 50 Ohm
6
R 15 50
+3. 3V PE C L D riv er
R 16
50
19
18
Q1
nQ1
21
20
Q2
nQ2
+3. 3V P EC L R ec eiv er
R5
82
R6
82
Z o = 50 Ohm
23
Q3
+
R9
137
+3. 3V
Z o = 50 Ohm
nQ3
-
22
R 11
187
R 17
130
R 12
187
+3. 3V LV PEC L R ec eiv er
11
FB _I N
+3.3V
R 13
82
Z o = 50 Ohm
Q4
Logic Contr ol Input Exam ples
Set Logic
Input to '0'
To Logic
Input
pins
E PA D
R 19
82
33
To Logic
Input
pins
Z o = 50 Ohm
V EE
RU2
N ot I ns tall
RD1
N ot I ns tall
nQ4
VE E
RU1
1k
V CC
26
nFB _IN
28
Set Logic
Input to '1'
10
13
V CC
R 18
130
27
RD2
1k
Figure 4. 8735BI-01 Schematic Example
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
14
REVISION 1 04/02/15
8735BI-01 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8735BI-01.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 8735BI-01 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCCO = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
The maximum current at 85°C is as follows:
IEE_MAX = 155mA
•
Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 155mA = 537.075mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_MAX (3.465V, with all outputs switching) = 537.075mW + 150mW = 687.075mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 47.9°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.687W * 47.9°C/W = 118°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance JA for 32-LeadLQFP, Forced Convection
JA by Velocity (Linear Feet per Minute)
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
47.9°C/W
42.1°C/W
39.4°C/W
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Table 7B. JA vs. Air Flow Table for a 32-Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
REVISION 1 04/02/15
15
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate power dissipation per output due to loading, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V– (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V– 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
16
REVISION 1 04/02/15
8735BI-01 Data Sheet
Reliability Information
Table 8A. JA vs. Air Flow Table for a 32-Lead LQFP
JA by Velocity (Linear Feet per Minute)
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
47.9°C/W
42.1°C/W
39.4°C/W
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Table 8B. JA vs. Air Flow Table for a 32-Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Transistor Count
The transistor count for 8735BI-01 is: 2969
REVISION 1 04/02/15
17
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
32-Lead LQFP Package Outline and Package Dimensions
Package Outline - Y Suffix for 32-Lead LQFP
Table 9. Package Dimensions for 32-Lead LQFP
Symbol
N
A
A1
A2
b
c
D&E
D1 & E1
D2 & E2
e
L
ccc
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Minimum
Nominal
32
0.05
1.35
0.30
0.09
0.45
0°
0.10
1.40
0.37
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
Maximum
1.60
0.15
1.45
0.45
0.20
0.75
7°
0.10
Reference Document: JEDEC Publication 95, MS-026
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
18
REVISION 1 04/02/15
8735BI-01 Data Sheet
32-Lead VFQFN Package Outline and Package Dimensions
Package Outline - NL Suffix for 32 Lead VFQFN
NOTE: The drawing and dimension data originates from IDT
package outline drawing PSC-4171, Rev. 05.
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
A3
0.2 Ref.
b
0.18
0.25
0.30
D&E
5.00 Basic
D2 & E2
3.00
3.15
3.30
e
0.50 Basic
L
0.30
0.40
0.50
REVISION 1 04/02/15
1.
All dimensions are in millimeters. All angles are in degrees.
2.
Coplanarity applies to the exposed pad as well as the
terminals.
Coplanarity shall not exceed 0.08mm.
3.
19
Warpage should not exceed 0.10mm.
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8735BYI-01LF
ICS8735BI01L
32-Lead LQFP, Lead-Free
Tray
-40°C to 85°C
8735BYI-01LFT
ICS8735BI01L
32-Lead LQFP, Lead-Free
Tape & Reel
-40°C to 85°C
8735BKI-01LF
ICS735BI01L
32-Lead VFQFN, Lead-Free
Tray
-40°C to 85°C
8735BKI-01LFT
ICS735BI01L
32-Lead VFQFN, Lead-Free
Tape & Reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
20
REVISION 1 04/02/15
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