879893AYILFT

879893 Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator Datasheet General Description Features The 879893 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two LVCMOS/LVTTL clock signals from which it generates 12 new LVCMOS/LVTTL clock outputs. External PLL feedback is used to also provide zero delay buffer performance. • Twelve LVCMOS/LVTTL outputs (two banks of six outputs); One QFB feedback clock output • • Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs The 879893 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the nALARM for that CLK will be latched (LOW). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. • • • • • • • • • • Automatically detects clock failure CLK0, CLK1 supports the following input types: LVCMOS, LVTTL IDCS on-chip intelligent dynamic clock switch Maximum output frequency: 200MHz Output skew: 50ps (maximum), within bank Cycle-to-cycle (FSEL3=0, VDD=3.3V±5%): 150ps (maximum) Smooth output phase transition during clock fail-over switch Full 3.3V or 2.5V supply modes -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package For functional replacement part use 87973i VDD nALARM_RST REF_SEL nPLL_EN GND FSEL0 FSEL1 GND FSEL2 FSEL3 nOE/MR Pulldown FSEL0 FSEL1 FSEL2 QA Pulldown REF CLK1 Pulldown REF_SEL nMAN/A nALARM_RST Pulldown Pullup Pullup nPLL_EN Pulldown FSEL3 PLL 0 VCO RANGE 240MHz - 500MHz FB FB FSEL[0:2] 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷2 ÷2 ÷2 ÷4 ÷2 ÷16 ÷8 ÷4 6 D Q 0 IDCS ÷2 6 D Q D Q QA0:QA5 QB0:QB5 1 FSEL0 FSEL1 FSEL2 QB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ÷16 ÷8 ÷6 ÷8 ÷4 ÷16 ÷8 ÷4 QFB GND QA0 QA1 VDD GND QA2 QA3 VDD GND QA4 QA5 VDD Pulldown nALARM0 nALARM1 CLK_IND Pulldown 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 20 41 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 GND QFB FB nMAN/A VDD CLK0 CLK1 VDDA nALARM0 nALARM1 CLK_IND CLK0 GND QB0 QB1 VDD GND QB2 QB3 VDD GND QB4 QB5 VDD GND nOE/MR VDD Pin Assignment Simplified Block Diagram 879893 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ©2017 Integrated Device Technology, Inc. 1 Revision B, January 10, 2017 879893 Datasheet Block Diagram CLK0 Pulldown 1 0 REF CLK1 Pulldown PLL 1 0 D Q D Q D Q 6 QA0:QA5 6 QB0:QB5 VCO RANGE 240MHz - 500MHz FB Pulldown REF_SEL Pulldown nMAN/A Pullup FB IDCS DATA GENERATOR nALARM_RST Pullup nPLL_EN Pulldown FSEL[0:3] Pulldown QFB nALARM0 nALARM1 CLK_IND nOE/MR Pulldown ©2017 Integrated Device Technology, Inc. 2 Revision B, January 10, 2017 879893 Datasheet Table 1. Pin Descriptions Number Name Type 1, 12, 16, 20, 29, 32, 37, 41, 45 GND Power Power supply ground. 2 QFB Output Clock feedback output. LVCMOS / LVTTL interface levels. 3 FB Input Pulldown Pullup Description Feedback control input. LVCMOS / LVTTL interface levels. Manual alarm input. Selects automatic switch mode or manual reference clock. Clock failure detection, and nALARM_RST and CLK_IND output flags are enabled. When LOW, IDCS is disabled. When HIGH, IDCS is enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation requires nPLL_EN = 0. LVCMOS / LVTTL interface levels. 4 nMAN/A Input 5, 13, 17, 21, 25, 36, 40, 44, 48 VDD Power 6, 7 CLK0, CLK1 Input 8 VDDA Power Analog supply pin. 9 nALARM0 Output When LOW, indicates clock failure on CLK0. LVCMOS / LVTTL interface levels. 10 nALARM1 Output When LOW, indicates clock failure on CLK1. LVCMOS / LVTTL interface levels. 11 CLK_IND Output Indicates currently selected input reference clock. When LOW, CLK0 is the reference clock. When HIGH, CLK1 is the reference clock. LVCMOS / LVTTL interface levels. 14, 15, 18, 19, 22, 23 QB5, QB4, QB3, QB2, QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. Core supply pins. Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 26 nOE/MR Input Pulldown Active High Master Reset. Active Low Output Enable. When logic LOW, the internal dividers and the outputs are enabled. When logic HIGH, the internal dividers are reset and the outputs are in a high-impedance state. LVCMOS / LVTTL interface levels. 27, 28, 30, 31 FSEL3, FSEL2, FSEL1, FSEL0 Input Pulldown Clock frequency selection and configuration of clock divider modes. LVCMOS / LVTTL interface levels. 33 nPLL_EN Input Pulldown Selects PLL or static test mode. When LOW, PLL is enabled. When HIGH, PLL is bypassed and IDCS is disabled. The VCO output is replaced by the reference clock signal fREF. LVCMOS / LVTTL interface levels. 34 REF_SEL Input Pulldown Selects the primary reference clock. When LOW, selects CLK0 as the primary clock source. When HIGH, selects CLK1 as the primary clock source. LVCMOS / LVTTL interface levels. 35 nALARM_RST Input Pullup 38, 39 42, 43, 46, 47 QA0, QA1, QA2, QA3, QA4, QA5 Output Resets the alarm flags and selected reference clock. LVCMOS / LVTTL interface levels. Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ©2017 Integrated Device Technology, Inc. 3 Revision B, January 10, 2017 879893 Datasheet Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor Minimum Typical Maximum Units 4 pF VDD = 3.465V 9 pF VDD = 2.625V 9 pF 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT 14  Output Impedance Function Tables Table 3. Clock Frequency Function Table Inputs FSEL0 FSEL1 FSEL2 FSEL3 0 0 0 0 0 0 0 1 0 0 1 0 Ratio fQAx (MHz) 15 – 25 fREF * 8 120 – 200 fREF * 4 120 – 200 fREF * 3 120 – 200 fREF * 2 60 – 125 fREF * 2 120 – 200 fREF 15 – 31.25 fREF 30 – 62.5 fREF 60 – 100 30 – 50 0 0 1 1 0 1 0 0 40 – 66.66 0 1 0 1 0 1 1 0 30 – 62.5 0 1 1 1 1 0 0 0 60 – 100 1 0 0 1 1 0 1 0 15 – 31.25 1 0 1 1 1 1 0 0 30 – 62.5 1 1 0 1 1 1 1 0 60 – 100 1 1 1 1 ©2017 Integrated Device Technology, Inc. Outputs fREF Range (MHz) 4 Ratio fQBx (MHz) QFB fREF * 8 120 – 200 fREF fREF * 4 60 – 100 fREF fREF * 4 120 – 200 fREF fREF * 2 60 – 100 fREF fREF * 3 120 – 200 fREF fREF * 3 ÷ 2 60 – 100 fREF fREF * 2 60 – 125 fREF fREF * 1 30 – 75 fREF fREF * 2 120 – 200 fREF fREF 60 – 100 fREF fREF 15 – 31.25 fREF fREF ÷ 2 7.5 – 15.62 fREF fREF 20 – 62.5 fREF fREF ÷ 2 15 – 31.25 fREF fREF 60 – 100 fREF fREF ÷ 2 30 – 50 fREF Revision B, January 10, 2017 879893 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 195 mA IDDA Analog Supply Current 13 mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 173 mA IDDA Analog Supply Current 13 ©2017 Integrated Device Technology, Inc. Test Conditions 5 Revision B, January 10, 2017 879893 Datasheet Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Maximum Units 2 VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V FSEL[0:3], FB, nOE/MR, nMAN/A, nALARM_RST[0:1], nPLL_EN, REF_SEL VDD = 3.465V -0.3 0.8 V FSEL[0:3], FB, nOE/MR, nMAN/A, nALARM_RST, nPLL_EN, REF_SEL VDD = 2.625V -0.3 0.7 V VDD = 3.465V or 2.625V -0.3 1.3 V CLK0, CLK1 IIH IIL VOH VOL Input High Current Input Low Current Test Conditions Minimum VDD = 3.465V Typical nMAN/A, nALARM_RST VDD = VIN = 3.465V or 2.625V 5 µA CLK0, CLK1, FB, nOE/MR, FSEL[0:3], nPLL_EN, REF_SEL VDD = VIN = 3.465V or 2.625V 200 µA nMAN/A, nALARM_RST VDD = 3.465V or 2.625V, VIN = 0V -200 µA CLK0, CLK1, FB, nOE/MR, FSEL[0:3], nPLL_EN, REF_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA VDD = 3.465V, IOH = -24mA 2.4 V VDD = 2.625V, IOH = -15mA 1.8 V Output High Voltage Output Low Voltage VDD = 3.465V, IOL = 24mA 0.55 V VDD = 3.465V, IOL = 12mA 0.30 V VDD = 2.625V, IOL = 15mA 0.6 V Unless otherwise noted, outputs terminated with 50 to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams. ©2017 Integrated Device Technology, Inc. 6 Revision B, January 10, 2017 879893 Datasheet AC Electrical Characteristics Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Parameter Symbol Test Conditions Minimum fOUT Output Frequency 7.5 fREF Input Frequency 15 BW PLL Closed Loop Bandwidth t(Ø) Propagation Delay, (Static Phase Offset, CLKx to FB); NOTE 1, 2, 3 tsk(o) Output Skew; NOTE 1, 2, 3, 4 Typical 200 MHz 100 MHz MHz VDD = 3.3V±5%; FSEL = 111x -35 120 ps VDD = 3.3V±5% -35 130 ps within bank 50 ps bank-to-bank 135 ps any output to QFB 315 ps 160 ps/ cycle Rate of Period Change; NOTE 2 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2, 3 tCYCLE Output Clock Period Deviation when switching from primary input to secondary; NOTE 2 tjit(per) Period Jitter; NOTE 2, 3 tjit(Ø) Units 0.8 to 4 fREF = 62.5MHz, FSEL = 1000 t Maximum I/O Phase Jitter, (1); NOTE 2, 3 FSEL = XXX0 100 280 ps/ cycle FSEL = XXX1 200 425 ps/ cycle FSEL3 = 0 150 ps FSEL3 = 1 190 ps -600 700 ps -800 800 ps FSEL3 = 0 150 ps FSEL3 = 1, measured on QBx 150 ps FB = 4; FSEL [0:2] = 100 or 111 (1) 25 ps FB = 6; FSEL [0:2] = 010 (1) 25 ps FB = 8; FSEL [0:2] = 001, 011 or 110 (1) 35 ps FB = 16; FSEL [0:2] = 000 or 101 (1) 25 ps fREF = 62.5MHz, FSEL = 1000 t R / tF Output Rise/Fall Time 600 ps tPZL, tPZH Output Enable Time; NOTE 2 20% to 80% 250 10 ns tPLZ, tPHZ Output Disable Time; NOTE 2 10 ns tL PLL Lock Time; NOTE 2 10 ms odc Output Duty Cycle 55 % 45 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. ©2017 Integrated Device Technology, Inc. 7 Revision B, January 10, 2017 879893 Datasheet Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Parameter Symbol fOUT Output Frequency 7.5 200 MHz fREF Input Frequency 15 100 MHz BW PLL Closed Loop Bandwidth t(Ø) Propagation Delay, (Static Phase Offset, CLKx to FB); NOTE 1, 2, 3 tsk(o) Output Skew; NOTE 1, 2, 3, 4 t Test Conditions Typical Maximum 0.8 to 4 Units MHz VDD = 3.3V±5%; FSEL = 111x -55 120 ps VDD = 3.3V±5% -55 130 ps within bank 50 ps bank-to-bank 135 ps any output to QFB 280 ps fREF = 62.5MHz, FSEL = 1000 175 ps/ cycle FSEL = XXX0 260 ps/ cycle FSEL = XXX1 350 ps/ cycle FSEL3 = 0 180 ps FSEL3 = 1 245 ps -600 700 ps -800 850 ps FSEL3 = 0 150 ps FSEL3 = 1, measured on QBx 150 ps FB = 4; FSEL [0:2] = 100 or 111 (1) 30 ps FB = 6; FSEL [0:2] = 010 (1) 40 ps FB = 8; FSEL [0:2] = 001, 011 or 110 (1) 25 ps FB = 16; FSEL [0:2] = 000 or 101 (1) 30 ps Rate of Period Change; NOTE 2 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2, 3 tCYCLE Output Clock Period Deviation when switching from primary input to secondary; NOTE 2 tjit(per) Period Jitter; NOTE 2, 3 tjit(Ø) Minimum I/O Phase Jitter, (1); NOTE 2, 3 fREF = 62.5MHz, FSEL = 1000 t R / tF Output Rise/Fall Time 600 ps tPZL, tPZH Output Enable Time; NOTE 2 20% to 80% 250 10 ns tPLZ, tPHZ Output Disable Time; NOTE 2 10 ns tL PLL Lock Time; NOTE 2 10 ms odc Output Duty Cycle 55 % 45 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. ©2017 Integrated Device Technology, Inc. 8 Revision B, January 10, 2017 879893 Datasheet Parameter Measurement Information 1.25V±5% 1.65V±5% SCOPE VDD, VDDA SCOPE VDD, VDDA Qx Qx GND GND -1.65V±5% -1.25V±5% 3.3V Output Load AC Test Circuit 2.5V Output Load AC Test Circuit V DD QA[0:5], QB[0:5] 2 ➤ V tcycle n DD Qy tcycle n+1 ➤ Qx ➤ ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles 2 tsk(o) Output Skew Cycle-to-Cycle Jitter VOH VDD CLK0, CLK1 2 VOL VDD FB 2 VREF VOH tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter t(Ø) mean = Static Phase Offset and I/O Phase Jitter Reference Point (Trigger Edge) Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges Histogram Mean Period (First edge after trigger) Input/Output Phase Jitter ©2017 Integrated Device Technology, Inc. VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements VOL ➤ ➤ t(Ø) VOH Period Jitter 9 Revision B, January 10, 2017 879893 Datasheet Parameter Measurement Information, continued CLK0, CLK1 FB QA[0:5], QB[0:5] Propagation Delay 80% 80% tR tF 20% 20% Output Rise/Fall Time V DDO 2 QA[0:5], QB[0:5] t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period ©2017 Integrated Device Technology, Inc. 10 Revision B, January 10, 2017 879893 Datasheet Application Information CLOCK REDUNDANCY AND REFERENCE SELECTION OUTPUT TRANSITIONING The 879893 accepts two LVCMOS/LVTTL single ended input clocks, CLK0 and CLK1, for the purpose of redundancy. Only one of these clocks can be selected at any given time for use as the reference. The clock that is used by default as the reference is referred to as the primary clock, while the remaining clock is the redundant or secondary clock. Input signal REF_SEL determines which input is to be used as the primary and which is to be used as the secondary. When REF_SEL is driven HIGH, the primary clock input is CLK1, otherwise an internal pull down pulls this input LOW so that the primary clock input is CLK0. The output signal CLK_IND indicates which clock input is being used as the reference (LOW = CLK0, HIGH = CLK1), and will initially be at the same level as REF_SEL. After a successful manual or IDCS initiated clock switch, the 879893’s internal PLL will begin slewing to phase/frequency alignment, and will eventually achieve lock with the new input with minimal phase disturbance at the outputs. MASTER RESET OPERATION Applying logic HIGH to the nOE/MR input resets the internal dividers of the 879893 and disables the outputs QA0:QA5 and QB0:QB5 in high-impedance state. Logic LOW state at the nOE/MR input enables the outputs and internal dividers. RECOMMENDED POWER-UP SEQUENCE FAILURE DETECTION AND ALARM SIGNALING Within the 879893 device, CLK0 and CLK are continuously monitored for failures. A failure on either of these clocks is detected when one of the clock signals is stuck HIGH or LOW for at least 1 period. Upon detection of a failure, the corresponding alarm signal, nALARM0 or nALARM1, is latched LOW. A HIGH-to-LOW transition on input signal nALARM_RST causes the alarm outputs to be reset HIGH, and the primary clock input is selected as the reference clock. Otherwise, an internal pull-up holds nALARM_RST HIGH, and the IDCS flags remain unchanged. If n_ALARM_RST is asserted when both of the alarm flag outputs are LOW, CLK0 is selected as the reference input. The device’s internal PLL is able to maintain phase/frequency alignment, and lock with the input as long as the input used as the reference clock does not fail. 1. Hold nOE/MR HIGH, drive nMAN/A LOW, and drive REF_SEL to the desired value during power up in order to reset internal dividers, disable the outputs in high-impedance state (nOE/MR = HIGH), select manual switching mode, and select the primary input clock. 2. Once powered up, assuming a stable clock free of failures is present at the primary input, the PLL will begin phase/frequency slewing as it attempts to achieve lock with the input reference clock. 3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0 and nALARM1 alarm flag outputs. 4. (Optional) Drive nMAN/A HIGH to enable IDCS mode. MANUAL CLOCK SWITCHING ALTERNATE POWER-UP SEQUENCE When input signal nMAN/A is driven LOW, the primary clock, as selected by REF_SEL, is always used as the reference, even when a clock failure is detected at the reference. In order switch between CLK0 and CLK1 as the primary clock, the level on REF_SEL must be driven to the appropriate level. When the level on REF_SEL is changed, the selection of the new primary clock will take place, and CLK_IND will be updated to indicate which clock is now supplying reference. This process serves as a manual safety mechanism to protect the stability of the PLL when a failure occurs on the reference. If both input clocks are valid before power up, the device may be powered up in IDCS mode. DYNAMIC CLOCK SWITCHING 2. Once powered up, the PLL will begin phase/frequency slewing as it attempts to achieve lock with the input reference clock. 3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0 and nALARM1 alarm flag outputs. 1. During power up, select the desired primary clock input by REF_SEL and hold nOE/MR at logic HIGH level to reset the internal dividers and to disable the outputs QA0:QA5 and QB0:QB5 in high-impedance state. Logic high level at the nMAN/A input enables the IDCS mode. An internal bias resistor will pull the nMAN/A input to logic high level if nMAN/A is left open. When input signal nMAN/A is not driven LOW, an internal pull-up pulls it HIGH so that Intelligent Dynamic Clock Switching (IDCS) is enabled. If IDCS is enabled, once a failure occurs on the primary clock, the 879893 device will automatically deselect the primary clock as the reference and multiplex in the secondary clock, but only if it is valid and has no failures. When a successful switch from primary to secondary has been accomplished, CLK_IND will be updated to indicate the new reference. This process serves as an automatic safety mechanism to protect the stability of the PLL when a failure occurs on the reference. ©2017 Integrated Device Technology, Inc. 11 Revision B, January 10, 2017 879893 Datasheet Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK Inputs LVCMOS Outputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 879893 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. ©2017 Integrated Device Technology, Inc. 3.3V or 2.5V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering 12 Revision B, January 10, 2017 879893 Datasheet Schematic Example Figure 2 shows a schematic example of the 879893. In this example, the CLK1 input is selected as primary. Both CLK0 and CLK1 inputs are driven by LVCMOS drivers. For the LVCMOS outputs, series termination is shown in this example. Additional LVCMOS termination approached are shown in the LVCMOS Termination Application Note. In this example, feedback trace is assumed to be a long trace. The series termination near the QFB pin is required. If the feedback trace is short, series termination is not required. If this device is also used as a zero delay buffer, the application note ZDB Delay Affected by Feedback Trace provides additional information. For the power pins, it is recommended to have at least one decoupling capacitor per power pin. The decoupling capacitors should be physically located near the power pins. LVCMOS/LVTTL LVCMOS/LVTTL VDDO LVCMOS/LVTTL Zo = 50 Ohm QA5 R15 Zo = 50 Ohm R16 36 36 VDDO VDD VDD 3.3V LVCMOS/LVTTL Ro=14 Ohm VDDO R4 36 U1 VDD VDD QA5 QA4 GND VDD QA3 QA2 GND VDD QA1 QA0 GND 48 47 46 45 44 43 42 41 40 39 38 37 Zo = 50 Ohm Driv er_LVCMOS 1 2 3 4 5 6 7 8 9 10 11 12 nMAN/A VDD CLK0 CLK1 R5 36 VDDA C31 0.1u 1K 36 35 34 33 32 31 30 29 28 27 26 25 F_SEL0 F_SEL1 R2 F_SEL2 F_SEL3 1K VDD QB5 QB4 GND VDD QB3 QB2 GND VDD QB1 QB0 GND 10 VDD CLK_IND R8 nALARM0 Driv er_LVCMOS nALARM1 Zo = 50 Ohm R1 VDD nALARM_RST REF_SEL nPLL_EN GND F_SEL0 F_SEL1 GND F_SEL2 F_SEL3 nOE/MR VDD ICS879893i 13 14 15 16 17 18 19 20 21 22 23 24 Ro=14 Ohm GND QFB FB nMAN/A VDD CLK0 CLK1 VDD_PLL nALARM0 nALARM1 CLK_IND GND C40 10u VDDO Zo = 50 Ohm QB5 R25 36 3.3V LVCMOS/LVTTL VDD=3.3V Status indicator VDDO=3.3V Hardwire Logic Input Pin Examples (U1,25) VDD (U1,36) LVCMOS Set Logic Input to '1' VDD C5 0.1u C6 0.1u LVCMOS LVCMOS (U1,5) VDDO (U1,13) (U1,17) (U1,21) (U1,40) (U1,44) (U1,48) RU1 1K RU2 Not Install To Logic Input pins RD1 Not Install C1 0.1u C2 0.1u C3 0.1u C4 0.1u C7 0.1u C8 0.1u Set Logic Input to '0' VDD To Logic Input pins RD2 1K C9 0.1u Figure 2. 879893 Schematic Example ©2017 Integrated Device Technology, Inc. 13 Revision B, January 10, 2017 879893 Datasheet Reliability Information Table 6. JA vs. Air Flow Table for a 48 Lead LQFP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 879893 is: 4615 ©2017 Integrated Device Technology, Inc. 14 Revision B, January 10, 2017 879893 Datasheet Package Outline and Package Dimensions Package Outline - Y Suffix for 48 Lead LQFP Table 7. Package Dimensions for 48 Lead LQFP JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 48 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.4 1.45 b 0.17 0.22 0.27 c 0.09 0.15 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.50 Ref. e 0.50 Basic L 0.45 0.60 0.75  0° 7° ccc 0.08 Reference Document: JEDEC Publication 95, MS-026 ©2017 Integrated Device Technology, Inc. 15 Revision B, January 10, 2017 Ordering Information Table 8. Ordering Information Part/Order Number 879893AYILF 879893AYILFT Marking ICS879893AIL ICS879893AIL Package “Lead-Free” 48 Lead LQFP “Lead-Free” 48 Lead LQFP Shipping Packaging Tray Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Revision History Sheet Rev Table A Page A B Date 12 Updated Schematic Example text and diagram. 2/10/05 1 11 Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins and Power Supply Filtering Techniques Sections. Ordering Information Table - added lead-free Part/Order Number, Marking and Note. Updated datasheet format. 7/8/08 A A Description of Change T8 15 T8 16 Ordering Information - removed leaded devices. Updated data sheet format. 7/21/15 1 Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05. 11/6/15 Datasheet is obsolete per PDN# CQ-15-05. 1/10/17 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2017 Integrated Device Technology, Inc. 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