89HPES5T5ZBBCG8

® IDT™ 89EBPES8T5A Evaluation Board Manual (Eval Board: 18-636-002) July 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc. Table of Contents ® Notes Description of the EB8T5A Eval Board Introduction ..................................................................................................................................... 1-1 Board Features ............................................................................................................................... 1-2 Hardware ................................................................................................................................ 1-2 Software.................................................................................................................................. 1-2 Other....................................................................................................................................... 1-2 Revision History .............................................................................................................................. 1-3 Installation of the EB8T5A Eval Board EB8T5A Installation ........................................................................................................................ 2-1 Hardware Description ..................................................................................................................... 2-1 Host System ........................................................................................................................... 2-1 Reference Clocks............................................................................................................................ 2-1 Power Sources................................................................................................................................ 2-3 External Power Source........................................................................................................... 2-3 Vaux Support..........................................................................................................................2-4 PCI Express Serial Data Transmit Termination Voltage Converter ........................................ 2-6 PCI Express Digital Power Voltage Converter........................................................................ 2-6 PCI Express Analog Power Voltage Converter ......................................................................2-6 Core Logic Voltage Converter ................................................................................................ 2-6 3.3V I/O Power Module........................................................................................................... 2-6 Power-up Sequence ............................................................................................................... 2-6 Required Jumpers .................................................................................................................. 2-6 Reset............................................................................................................................................... 2-6 Fundamental Reset ................................................................................................................ 2-6 Downstream Reset ................................................................................................................. 2-7 Boot Configuration Vector............................................................................................................... 2-7 SMBus Interfaces............................................................................................................................ 2-8 SMBus Slave Interface ........................................................................................................... 2-8 SMBus Master Interface ....................................................................................................... 2-10 JTAG Header ................................................................................................................................ 2-10 Attention Buttons........................................................................................................................... 2-11 Miscellaneous Jumpers, Headers................................................................................................. 2-11 LEDs ............................................................................................................................................. 2-12 PCI Express Connectors............................................................................................................... 2-14 EB8T5A Board Figure................................................................................................................... 2-16 Software for the EB8T5A Eval Board Introduction ..................................................................................................................................... 3-1 Device Management Software........................................................................................................ 3-1 Schematics Schematics ..................................................................................................................................... 4-1 EB8T5A Eval Board Manual i July 23, 2009 IDT Table of Contents Notes EB8T5A Eval Board Manual ii July 23, 2009 List of Tables ® Notes Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 Table 2.18 EB8T5A Eval Board Manual Clock Source Selection ....................................................................................................... 2-1 Clock Frequency Selection ................................................................................................. 2-2 Spread Spectrum Clock Selection ...................................................................................... 2-2 SMA Connectors - Onboard Reference Clock .................................................................... 2-2 External Power Connector - J4 ........................................................................................... 2-3 Downstream Reset Selection ............................................................................................. 2-7 Boot Configuration Vector Signals ...................................................................................... 2-7 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1) ................................ 2-8 Slave SMBus Interface Connector ...................................................................................... 2-9 SMBus Slave Interface Address Configuration ................................................................... 2-9 PES8T5A SMBus Slave Interface Address Setting ............................................................ 2-9 EEPROM SMBus Address Setting ................................................................................... 2-10 JTAG Connector Pin Out .................................................................................................. 2-11 Attention Buttons .............................................................................................................. 2-11 Miscellaneous Jumpers, Headers ..................................................................................... 2-11 LED Indicators .................................................................................................................. 2-13 PCI Express x4 Connector Pinout .................................................................................... 2-14 PCI Express x1 Connector Pinout .................................................................................... 2-15 iii July 23, 2009 IDT List of Tables Notes EB8T5A Eval Board Manual iv July 23, 2009 List of Figures ® Notes Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 EB8T5A Eval Board Manual Function Block Diagram of the EB8T5A Eval Board ..........................................................1-1 Clock Distribution Block Diagram .......................................................................................2-3 Power Distribution Block Diagram ......................................................................................2-4 APWRDIS# Timing ............................................................................................................2-5 APWRDIS# Timing Circuit .................................................................................................2-5 v July 23, 2009 IDT List of Figures Notes EB8T5A Eval Board Manual vi July 23, 2009 Chapter 1 Description of the EB8T5A Eval Board ® Notes Introduction In this manual, references to the PES8T5A also apply to the PES6T5 and PES5T5 unless otherwise indicated. The 89HPES8T5A switch (also referred to as PES8T5A in this manual) is a member of IDT’s PCI Express® standard (PCIe®) based line of products. It is an 8-lane, 5-port switch. One upstream port is provided for connecting to the root complex (RC), and up to four downstream ports are available for connecting to PCIe endpoints or to another switch. More information on this device can be found in the appropriate User Manual (89HPES8T5A, 89HPES6T5, or 89HPES5T5). The 89EBPES8T5A Evaluation Board (also referred to as EB8T5A in this manual) provides an evaluation platform for the PES8T5A switch. It is also a cost effective way to add a PCIe downstream port (x1) to an existing system with a limited number of PCIe downstream ports. The EB8T5A eval board is designed to function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appropriate root complex, microprocessor(s), and four downstream ports. The EB8T5A is a vehicle to test and evaluate the functionality of the PES8T5A chip. Customers can use this board to get a headstart on software development prior to the arrival of their own hardware. The EB8T5A is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EB8T5A board. JTAG Header SSC Clock Buffer Clock Fanout Main Reset x1 PCI Express Switch PES8T5A 25 MHz PCIe x1 Downstream Slot x1 PCIe x1 Downstream Slot x1 PCIe x1 Downstream Slot x1 I/O Expander PCA9555 PCIe x1 Downstream Slot EEPROM 24LC512 Power SMBus x4 (PES8T5A) x2 (PES6T5) x1 (PES5T5) SMBUS HEADER PCIe x4 Upstream Edge Module PTH08T240 External Power Connector Voltages on board +12V, +3.3V, +1.5V, +1.0V Figure 1.1 Function Block Diagram of the EB8T5A Eval Board EB8T5A Eval Board Manual 1-1 July 23, 2009 IDT Description of the EB8T5A Eval Board Notes Board Features Hardware ‹ PCIe 5 port switch – PES8T5A — Five ports (one x4 port and four x1 ports), 8 PCIe lanes – PES6T5 — Five ports (one x2 port and four x1 ports), 6 PCIe lanes – PES5T5 — Five ports (five x1 ports), 5 PCIe lanes – PCIe Base Specification Revision 1.1 compliant – Integrates eight 2.5 Gbps embedded SerDes – Up to 256 byte maximum Payload Size – Automatic lane reversal and polarity inversion supported on all lanes – Automatic per port link width negotiation to x4, x2, x1 – Load configuration from an optional serial EEPROM via SMBUS ‹ Upstream, Downstream Port – One edge connector on the upstream port, to be plugged into a slot with at least x4 capable mechanical slot connector on a host motherboard – Four slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in. ‹ Numerous user selectable configurations set using onboard jumpers and DIP-switches – Source of clock - host clock or onboard clock generator – Two clock rates and spread spectrum settings – Boot mode selection ‹ Vaux Support ‹ SMBUS Slave Interface (4 pin header) ‹ SMBUS Master Interface connected to the Serial EEPROMs through I/O expander ‹ “Attention” button for each downstream port to initiate a hot swap event on each port ‹ Four pin connector for optional external power supply ‹ Push button for Warm Reset ‹ Several LEDs to display status, reset, power, “Attention”, etc. ‹ One 14-pin JTAG header Software There is no software or firmware executed on the board. However, useful software is provided along with the Evaluation Board to facilitate configuration and evaluation of the PES8T5A within host systems running popular operating systems. ‹ Installation programs – Operating Systems Supported: Windows2000, WindowsXP, Linux GUI based application for Windows and Linux ‹ – Allows users to view and modify registers in the PES8T5A – Binary file generator for programming the serial EEPROMs attached to the SMBUS. Other ‹ A metal bracket is required to firmly hold in place the four endpoints plugged into the EB8T5A board. EB8T5A Eval Board Manual ‹ An external power supply may be required under some conditions. ‹ SMBUS cable may be required for certain evaluation exercises. ‹ SMA connectors are provided on the EB8T5A board for specific test points. 1-2 July 23, 2009 IDT Description of the EB8T5A Eval Board Notes Revision History September 10, 2007: Initial publication of board manual. July 23, 2009: Added PES6T5 and PES5T5 devices to eval board manual. Updated Power Sources section, Table 2.15, and Schematics. Added Note after Table 2.17. EB8T5A Eval Board Manual 1-3 July 23, 2009 IDT Description of the EB8T5A Eval Board Notes EB8T5A Eval Board Manual 1-4 July 23, 2009 Chapter 2 Installation of the EB8T5A Eval Board ® Notes EB8T5A Installation This chapter discusses the steps required to configure and install the EB8T5A evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1. Configure jumper/switch options suitable for the evaluation or application requirements. 2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board. 3. Insert the evaluation board into the host system (motherboard with root complex chipset). 4. Apply power to the host system. The EB8T5A board is shipped with all jumpers and switches configured to their default settings. In most cases, the board does not require further modification or setup. Hardware Description The PES8T5 is an 8-lane, 5-port PCI Express® switch. It is a peripheral chip that performs PCI Express based switching with a feature set optimized for high performance applications such as servers and storage. It provides fan-out and switching functions between a PCI Express upstream port and 4 downstream ports or peer-to-peer switching between downstream ports. The EB8T5A has four PCI Express downstream ports, accessible through four x4 open-ended connectors. Basic requirements for the board to run are: – Host system with a PCI Express root complex supporting x4 configuration through a PCI Express x4 slot. – PCI Express Endpoint Cards capable of training x1 link. Host System The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI Express root complex supporting x4 configuration through a PCI Express x4 slot is required to take full advantage of the PES8T5’s capabilities. Reference Clocks The PES8T5A requires a differential reference clock. The EB8T5A derives this clock from a common source which is user-selectable. The common source can be either the host system’s reference clock or the onboard clock generator. Selection is made by resistor switch described in Table 2.1. Clock Configuration Switch - S3[3] S3[3] Clock Source ON Onboard Reference Clock – Use onboard clock generator OFF Upstream Reference Clock – Host system provides clock (Default) Table 2.1 Clock Source Selection EB8T5A Eval Board Manual 2-1 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes The source for the onboard clock is the ICS9FG104 clock generator device (U8) connected to a 25MHz oscillator (Y1). When using the onboard clock generator, the EB8T5A allows selection between multiple clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively. Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak energy over a wider bandwidth. Clock Frequency Switch - S3[1] S3[1] Clock Frequency OFF 125MHz ON 100MHz (Default) Table 2.2 Clock Frequency Selection Clock Spread Spectrum Switch - S3[2] S3[2] Spread Spectrum OFF Enable Spread Spectrum ON Disable Spread Spectrum (Default) Table 2.3 Spread Spectrum Clock Selection If the Clock Spread Spectrum is used to modulate data rate, then both ports must use same modulated clock source. Therefore, if your system uses SSC, the on-board clock generator must be disabled and the upstream reference clock should be used instead. The output of the onboard clock generator is accessible through two SMA connectors located on the Evaluation Board. See Table 2.4. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source. Onboard Reference Clock Output (Differential) – J18, J19 J19 Positive Reference Clock J18 Negative Reference Clock Table 2.4 SMA Connectors - Onboard Reference Clock Figure 2.1 illustrates the clock distribution block diagram for the EB8T5A evaluation board. EB8T5A Eval Board Manual 2-2 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes PEREFCLK0 Upstream PEREFCLK ICS557-06 SMA - J18,J19 ICS9DB803D 25MHz ISC9FG104 Port2 Port3 Port4 Port5 Figure 2.1 Clock Distribution Block Diagram Power Sources Power for the EB8T5A is generated from the 12.0V PCI Express upstream slot power or optionally from 3.3Vaux. A 12.0V to 3.3V DC-DC converter will be used to provide power to four DC-DC converters to generate VDDcore, VDDpe, VDDpea, and VTT voltages. The 3.3V from the 12.0V converter is used to power VDDio. When in power down mode the DC-DC converters is powered directly from 3.3Vaux through a MOSFET switch. If add-in cards require more power than the upstream slot can support, an external source is required to supply this extra power via an auxiliary 4-pin power connector on the board. Header W1, W5, and W11 (see Table 2.15) are used to select the proper power source for the switch and all downstream ports. External Power Source If necessary, external power is supplied to the EB8T5A board through a 4-pin auxiliary power connector attached to J4. The external power supply provides +12V to the EB8T5A as described in Table 2.5. The +5V is unused. Pin Signal 1 +12V 2 GND 3 GND 4 +5V Table 2.5 External Power Connector - J4 EB8T5A Eval Board Manual 2-3 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Figure 2.2 Power Distribution Block Diagram Vaux Support Power supply support will be provided to EB8T5A from 12.0V upstream power to 3.3Vaux upstream power when in sleep mode. The WAKE# signal direction, both an input and output will be supported by jumper selection. The APWRDIS# signal for auxiliary power disable requires the following timing on powerup. EB8T5A Eval Board Manual 2-4 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Figure 2.3 APWRDIS# Timing On initial power up APWRDIS# must be held low initially for 8 clocks after PERST# is removed. Then it must be sampled high 256 clocks after PERSTN# is removed to enable L2 mode. Subsequent PERST# will not affect the APWRDIS# state. This timing will be provided by the following circuit. Figure 2.4 APWRDIS# Timing Circuit EB8T5A Eval Board Manual 2-5 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes PCI Express Serial Data Transmit Termination Voltage Converter A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown as VTTPE or VPETVTT) to the PES8T5A. PCI Express Digital Power Voltage Converter A separate DC-DC converter (U16) provides a 1.0V PCI Express digital power voltage (VDDPE) to the PES8T5A. PCI Express Analog Power Voltage Converter A separate DC-DC converter (U7) provides a 1.0V PCI Express analog power voltage (shown as VDDAPE or VDDPEA) to the PES8T5A. Core Logic Voltage Converter A separate DC-DC converter (U1) provides the 1.0V core voltage (VDDCORE) to the PES8T5A. 3.3V I/O Power Module A 12V to 3.3V power module (U5) provides the 3.3V I/O voltage (VDDIO) to the PES8T5A. Power-up Sequence The power-up sequence must be as following: 1. VDDIO - 3.3V 2. VDDCORE, VDDAPE, VDDPE - 1.0V 3. VTTPE - 1.5V When powering up, each voltage level must ramp up and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations between sequential valid power level requirements. To insure that the sequencing requirements are met, a 0.047µF is used at the SOFTSTART cap on the VTTPE’s voltage converter (U6 pin 36) in the EB8T5A. Required Jumpers To deliver power to the PES8T5A switch, the following jumpers must be shunted: W4, W10, W23, W24, and W25. These jumpers were implemented so that the power consumption of the PES8T5A can be measured. Reset The PES8T5A supports two types of reset mechanisms as described in the PCI Express specification: – Fundamental Reset: This is a system-generated reset that propagates along the PCI Express tree through a single side-band signal PERST# which is connected to the Root Complex, the PES8T5A, and the endpoints. – Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to another. Hot Reset may be initiated by software. This is further discussed in the 89HPES8T5A User Manual. The EB8T5A evaluation board provides seamless support for Hot Reset. Fundamental Reset There are two types of Fundamental Resets which may occur on the EB8T5A evaluation board: – Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI Express Reset (PERSTN) input pin of the PES8T5A. – Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be initiated by two methods: • Pressing a push-button switch (S1) located on EB8T5A board EB8T5A Eval Board Manual 2-6 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes • The host system board IO Controller Hub asserting PERST# signal, which propagates through the PCIe upstream edge connector of the EB8T5A. Note that one can bypass the onboard voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W2. Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN) input of the PES8T5A while power is on. Downstream Reset The PES8T5A provides a a choice of either a software-controlled reset for each downstream port through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in Table 2.6. Port # Jumper Selection 5 W8 [1-2] Software controlled reset through GPIO10 [2-3] Fundamental reset PERST# (default) 4 W9 [1-2] Software controlled reset through GPIO1 [2-3] Fundamental reset PERST# (default) 3 W6 [1-2] Software controlled reset through GPIO9 [2-3] Fundamental reset PERST# (default) 2 W7 [1-2] Software controlled reset through GPIO0 [2-3] Fundamental reset PERST# (default) Table 2.6 Downstream Reset Selection Boot Configuration Vector A boot configuration vector consisting of the signals listed in Table 2.7 is sampled by the PES8T5A during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential parameters for switch operation and is set using DIP switches S3, S4, and S5 as defined in Table 2.8. Signal Description CCLKDS Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. Default: 0x1 CCLKUS Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. Default: 0x1 MSMBSMODE RSTHALT Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 kHz. Default: 0x0 Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES8T5A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the P0_SWCTL register through the SMBus. The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register. Default: 0x0 Table 2.7 Boot Configuration Vector Signals (Part 1 of 2) EB8T5A Eval Board Manual 2-7 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Signal Description SWMODE[2:0] Switch Mode. These configuration pins determine the PES8T5A switch operating mode. Default: 0x0 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM-based initialization 0x2 through 0x8 - Reserved REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. Default: 0x0 0x0 - 100 MHz 0x1 - 125 MHz MSMBADDR[2:0] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Default: 0x0 APWRDIS# Auxiliary Power Disable. When this pin is active, it disables the device from using auxiliary power supply. Default: 0x0 Table 2.7 Boot Configuration Vector Signals (Part 2 of 2) Signal Description Default S3[4] CCLKDS OFF S3[5] CCLKUS OFF S3[6] MSMBSMODE ON S5[6] RSTHALT ON S5[1] SWMODE[0] ON S5[2] SWMODE[1] ON S5[3] SWMODE[2] ON S5[5] APWRDIS# ON S4[5] MSMBADDR[1] ON S4[6] MSMBADDR[2] ON S4[7] MSMBADDR[3] ON S4[8] MSMBADDR[4] ON Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1) SMBus Interfaces The System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus signals in the PCI Express connector is optional and may not be present on the host system. The SMBus interface consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. The PES8T5A contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface. The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all software-visible registers. The Master SMBus interface provides connection to the external serial EEPROMs used for initialization and the I/O expander used for hot-plug signals. SMBus Slave Interface On the PES8T5A board, the slave SMBus interface is accessible through the PCI Express edge connector as well as a 4-pin header as described in Table 2.9. EB8T5A Eval Board Manual 2-8 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes . Slave SMBus Interface Connector J21 Pin Signal 1 N/C 2 SCL 3 GND 4 SDA Table 2.9 Slave SMBus Interface Connector A fixed slave SMBus address specified by the SSMBADDR[5,3:1] pins is used. For a fixed address, the SMBus address of the PES8T5A slave interface is 0b1110111 by default and is configurable using DIP switch S4 as described in Tables 2.10 and 2.11. Slave Interface Address Configuration Address Bit Signal 1 SSMBUSADDR[1] 2 SSMBUSADDR[2] 3 SSMBUSADDR[3] 4 0 5 SSMBUSADDR[5] 6 1 7 1 Table 2.10 SMBus Slave Interface Address Configuration SMBUS Slave Interface Address Setting S4[4] SSMBADDR[5] S4[3] SSMBADDR[3] S4[2] SSMBADDR[2] S4[1] SSMBADDR[1] Slave Interface Bus Address OFF OFF OFF OFF 0b1110111 (Default) OFF OFF OFF ON 0b1110110 OFF OFF ON OFF 0b1110101 OFF OFF ON ON 0b1110100 OFF ON OFF OFF 0b1110011 OFF ON OFF ON 0b1110010 OFF ON ON OFF 0b1110001 OFF ON ON ON 0b1110000 ON OFF OFF OFF 0b1100111 ON OFF OFF ON 0b1100110 Table 2.11 PES8T5A SMBus Slave Interface Address Setting (Part 1 of 2) EB8T5A Eval Board Manual 2-9 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes SMBUS Slave Interface Address Setting S4[4] SSMBADDR[5] S4[3] SSMBADDR[3] S4[2] SSMBADDR[2] S4[1] SSMBADDR[1] Slave Interface Bus Address ON OFF ON OFF 0b1100101 ON OFF ON ON 0b1100100 ON ON OFF OFF 0b1100011 ON ON OFF ON 0b1100010 ON ON ON OFF 0b1100001 ON ON ON ON 0b1100000 Table 2.11 PES8T5A SMBus Slave Interface Address Setting (Part 2 of 2) The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions: – Byte and Word Write/Read – Block Write/Read SMBus Master Interface Connected to the master SMBus interface are four 16-bit I/O Expanders (PCA9555) and a serial EEPROM (24LC512). Four I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B). The bus address for the selected EEPROM device is 0b1010000 by default and the lower four bits is configurable using switch S4 as described in Table 2.12. S4[8] S4[7] S4[6] S4[5] Bus Address OFF OFF OFF OFF 0b1111 OFF OFF OFF ON 0b1110 OFF OFF ON OFF 0b1101 OFF OFF ON ON 01100 OFF ON OFF OFF 0b1011 OFF ON OFF ON 0b1010 OFF ON ON OFF 0b1001 OFF ON ON ON 0b1000 ON ON ON ON 0b0000 (Default) Table 2.12 EEPROM SMBus Address Setting JTAG Header The PES8T5A provides a JTAG connector J4 for access to the PES8T5A JTAG interface. The connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.12 for the JTAG Connector J2 pin out. EB8T5A Eval Board Manual 2 - 10 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes JTAG Connector J2 Pin Signal Direction Pin Signal Direction 1 /TRST - Test reset Input 2 GND — 3 TDI - Test data Input 4 GND — 5 TDO - Test data Output 6 GND — 7 TMS - Test mode select Input 8 GND — 9 TCK - Test clock Input 10 GND — Table 2.13 JTAG Connector Pin Out Attention Buttons The PES8T5A features four attention buttons, shown in Table 2.13. Each button corresponds to a particular port and is used to initiate hot-swapping events. Button Description SW4 Port 5 Attention Button SW3 Port 4 Attention Button SW2 Port 3 Attention Button SW1 Port 2 Attention Button Table 2.14 Attention Buttons Miscellaneous Jumpers, Headers Miscellaneous Jumpers, Headers Ref. Designator Type Default S2[1] Switch OFF Port2: Manually-operated Retention Latch S2[2] Switch OFF Port3: Manually-operated Retention Latch S2[3] Switch OFF Port4: Manually-operated Retention Latch S2[4] Switch OFF Port5: Manually-operated Retention Latch S6[4] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and +3.3V) to Port 5 (Default) S6[3] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and +3.3V) to Ports 4 (Default) S6[2] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and +3.3V) to Ports 3 (Default) S6[1] Switch OFF Bypass hot-plug controller - Enables direct power (+12V and +3.3V) to Ports 2 (Default) Description Table 2.15 Miscellaneous Jumpers, Headers (Part 1 of 2) EB8T5A Eval Board Manual 2 - 11 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Miscellaneous Jumpers, Headers Ref. Designator Type Default W32 Header 2-3 Shunted 1-2: Port 2, +3.3V source base on hot-plug controller 2-3: Port 2, +3.3V source from upstream port power W31 Header 2-3 Shunted 1-2: Port 2, +12V source base on hot-plug controller 2-3: Port 2, +12V source from upstream port power W30 Header 2-3 Shunted 1-2: Port 2, +3.3Vaux source base on hot-plug controller 2-3: Port 2, +3.3Vaux source from upstream port power W35 Header 2-3 Shunted 1-2: Port 3, +3.3V source base on hot-plug controller 2-3: Port 3, +3.3V source from upstream port power W34 Header 2-3 Shunted 1-2: Port 3, +12V source base on hot-plug controller 2-3: Port 3, +12V source from upstream port power W33 Header 2-3 Shunted 1-2: Port 3, +3.3Vaux source base on hot-plug controller 2-3: Port 3, +3.3Vaux source from upstream port power W38 Header 2-3 Shunted 1-2: Port4, +3.3V source base on hot-plug controller 2-3: Port 4, +3.3V source from upstream port power W37 Header 2-3 Shunted 1-2: Port 4, +12V source base on hot-plug controller 2-3: Port 4, +12V source from upstream port power W36 Header 2-3 Shunted 1-2: Port 4, +3.3Vaux source base on hot-plug controller 2-3: Port 4, +3.3Vaux source from upstream port power W50 Header 2-3 Shunted 1-2: Port 5, +3.3V source base on hot-plug controller 2-3: Port 5, +3.3V source from upstream port power W40 Header 2-3 Shunted 1-2: Port 5, +12V source base on hot-plug controller 2-3: Port 5, +12V source from upstream port power W39 Header 2-3 Shunted 1-2: Port 5, +3.3Vaux source base on hot-plug controller 2-3: Port 5, +3.3Vaux source from upstream port power W15 Header Open S2[6] Switch On Power Good Enable Force On switch for ICS90DB803 clock output enable (OE2#) S2[1] Switch On Power Good Enable Force On switch for ICS90DB803 clock output enable (OE3#) S6[6] Switch On Power Good Enable Force On switch for ICS90DB803 clock output enable (OE4#) S6[5] Switch On Power Good Enable Force On switch for ICS90DB803 clock output enable (OE5#) W1, W5, W11 Header 1-2 Shunted W3 Header Shunted Description 1-2: Select WAKEN# as an input 2-3: Select WAKE# as in output 1-2: +12V source from upstream port (Default) 2-3: +12V source from external power connect Disable EEPROM Write protect feature (Default) Table 2.15 Miscellaneous Jumpers, Headers (Part 2 of 2) LEDs There are several LED indicators on the EB8T5A which convey status feedback. A description of each is provided in Table 2.15. EB8T5A Eval Board Manual 2 - 12 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Location Color Definition DS87 Green Port 2: Power-is-good indicator DS86 Green Port 3: Power-is-good indicator DS85 Green Port 4: Power-is-good indicator DS84 Green Port 5: Power-is-good indicator DS83 Amber Port2: Attention Input indicator DS82 Amber Port3: Attention Input indicator DS81 Amber Port4: Attention Input indicator DS80 Amber Port5: Attention Input indicator DS79 Green Port2: Presence Detect indicator DS78 Green Port3: Presence Detect indicator DS77 Green Port4: Presence Detect indicator DS76 Green Port5: Presence Detect indicator DS64 Amber Port2: Attention Output indicator DS63 Amber Port3: Attention Output indicator DS62 Amber Port4: Attention Output indicator DS61 Amber Port5: Attention Output indicator DS57 Green Port 2: Power indicator DS56 Green Port 3: Power indicator DS55 Green Port 4: Power indicator DS54 Green Port 5: Power indicator DS91 Red Port 2: MRL indicator DS90 Red Port 3: MRL indicator DS89 Red Port 4: MRL indicator DS88 Red Port 5: MRL indicator DS95 Red Port 2: Power Fault indicator DS94 Red Port 3: Power Fault indicator DS93 Red Port 4: Power Fault indicator DS92 Red Port 5: Power Fault indicator DS99 Green Port 2: Link Up indicator DS98 Green Port 3: Link Up indicator DS97 Green Port 4: Link Up indicator DS96 Green Port 5: Link Up indicator DS100 Green Port 0: Link Up indicator DS105 Amber Port0: Link Activity indicator DS104 Amber Port2: Link Activity indicator Table 2.16 LED Indicators (Part 1 of 2) EB8T5A Eval Board Manual 2 - 13 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Location Color Definition DS103 Amber Port3: Link Activity indicator DS102 Amber Port4: Link Activity indicator DS101 Amber Port5: Link Activity indicator Table 2.16 LED Indicators (Part 2 of 2) PCI Express Connectors Pin Side A Side B 1 +12V 12V power PRSNT1# 2 +12V 12V power +12V 12V power 3 RSVD Reserved +12V 12V power 4 GND Ground GND Ground 5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p 6 SMDAT SMBus Data JTAG TDI (Test Data Input) 7 GND Ground JTAG TDO (Test Data Output) 8 +3.3V 3.3V power JTAG TMS (Test Mode Select) 9 JTAG1 TRST# (Test/Reset) resets JTAG i/f +3.3V 3.3V power 10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power 11 WAKE# Signal for Link reactivation PERST# Hot-Plug presence detect Fundamental Reset Mechanical Key 12 RSVD Reserved GND 13 GND Ground REFCLK+ REFCLK Reference clock 14 PETp0 Transmitter differential REFCLK- (differential pair) 15 PETn0 pair, Lane 0 16 GND 17 PRSNT2# 18 GND 19 GND Ground Ground Ground PERp0 Receiver differential Hot-Plug presence detect PERn0 pair, Lane 0 Ground GND Ground PETp1 Transmitter differential RSVD Reserved 20 PETn1 pair, Lane 1 GND Ground 21 GND Ground PERp1 Receiver differential 22 GND Ground PERn1 pair, Lane 1 23 PETp2 Transmitter differential GND Ground 24 PETn2 pair, Lane 2 GND Ground 25 GND Ground PERp2 Receiver differential 26 GND Ground PERn2 pair, Lane 2 Table 2.17 PCI Express x4 Connector Pinout (Part 1 of 2) EB8T5A Eval Board Manual 2 - 14 July 23, 2009 IDT Installation of the EB8T5A Eval Board Notes Pin Side A Side B 27 PETp3 Transmitter differential GND Ground 28 PETn3 pair, Lane 3 GND Ground 29 GND Ground PERp3 Receiver differential 30 RSVD Reserved PERn3 pair, Lane 3 31 PRSNT2# 32 GND Hot-Plug presence detect GND Ground Ground RSVD Reserved Table 2.17 PCI Express x4 Connector Pinout (Part 2 of 2) Note: R347 should be populated with a 0 ohm resistor (0402) for systems that require PRSNT2# for the x1 width to be connected. Pin Side A Side B 1 +12V 12V power PRSNT1# 2 +12V 12V power +12V 12V power 3 RSVD Reserved +12V 12V power 4 GND Ground GND Ground 5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p 6 SMDAT SMBus Data JTAG TDI (Test Data Input) 7 GND Ground JTAG TDO (Test Data Output) 8 +3.3V 3.3V power JTAG TMS (Test Mode Select) 9 JTAG1 TRST# (Test/Reset) resets JTAG i/f +3.3V 3.3V power 10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power 11 WAKE# Signal for Link reactivation PERST# Hot-Plug presence detect Fundamental Reset Mechanical Key 12 RSVD Reserved GND 13 GND Ground REFCLK+ REFCLK Reference clock 14 PETp0 Transmitter differential REFCLK- (differential pair) 15 PETn0 pair, Lane 0 16 GND 17 PRSNT2# 18 GND GND Ground Ground Ground PERp0 Receiver differential Hot-Plug presence detect PERn0 pair, Lane 0 Ground GND Ground Table 2.18 PCI Express x1 Connector Pinout Note: These x4 and x1 PCI Express connectors comply with the PCIe specification. The EB8T5A uses x1 (mechanically x4) connector on all downstream ports. According to the PCI Express specification, the PRSNT1# pin should be wired to the farthest available PRSNT2# pin on the connector. In the EB8T5A, all PRSNT2# pins are tied together. This allows the board to be installed in a x1 or a x4 slot. The open-ended x4 slot allows the insertion of physical lane width greater than x4 to be installed without the need of slot reducer. EB8T5A Eval Board Manual 2 - 15 July 23, 2009 IDT Installation of the EB8T5A Eval Board EB8T5A Board Figure EB8T5A Eval Board Manual 2 - 16 July 23, 2009 Chapter 3 Software for the EB8T5A Eval Board ® Notes Introduction This chapter discusses some of the main features of the available software to give users a better understanding of what can be achieved with the EB8T5A evaluation board using the device management software. Device management software and related user documentation are available on a CD which is included in the Evaluation Board Kit. This information is also available on IDT’s FTP site. For more information, contact IDT at ssdhelp@idt.com. Device Management Software The primary use of the Device Management Software package is to enable users of the evaluation board to access all the registers in the PES8T5 device. This access can be achieved using the PCI Express in-band configuration cycles through the upstream port on the PES8T5. This software also enables users to save a snapshot of the current register set into a dump file which can be used for debugging purposes. An export/import facility is also available to create and use “Configuration” files which can be used to initialize the switch device with specific values in specific registers. A conversion utility is also provided to translate a configuration file into an EEPROM programmable data structure. This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES8T5, and then to populate that EEPROM onto the Evaluation Board. It is also possible to program the EEPROM directly on the Evaluation Board using a feature provided by the software package. The front end of the Device Management Software is a user-friendly Graphical User Interface which allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for the PES8T5 in the absence of the actual device. Much of the Device Management Software is written with device-independent and OS-independent code. The software will be guaranteed to work on Linux (/sys interface) and MS Windows XP. It may function flawlessly on various flavors of MS Windows, but may not be validated on all. The fact that the software is device-independent assures its scalability to future PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc. EB8T5A Eval Board Manual 3-1 July 23, 2009 IDT Software for the EB8T5A Eval Board Notes EB8T5A Eval Board Manual 3-2 July 23, 2009 Chapter 4 Schematics ® Notes Schematics EB8T5A Eval Board Manual 4-1 July 23, 2009 8 7 6 5 4 2 3 1 REVISIONS DCN BLOCK DIAGRAM REV PCB-0161R01 1.0 DESCRIPTION INTIAL RELEASE DATE 2008-04-14 CHANGE BY T. TRAN D D SHEET DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 C B TABLE OF CONTENTS POWER REGULATORS PES8T5A POWER MOSFETS FOR 3.3VAUX CLOCKS RESET,SMBUS,JTAG,DIPSW APWRDISN TIMING CIRCUIT EPROM ATTN_SW WAKE IO EXPANDERS IO EXPANDER LEDS HOT SWAP CONTROL PORT 2/4 HOT SWAP CONTROL PORT 3/5 PES8T5A - CLOCK,SMBUS,GPIO PES8T5A - PORT 0 PES8T5A - DOWNSTREAM PORTS DOWNSTREAM PORT 2/3 CONNECTORS DOWNSTREAM PORT 4/5 CONNECTORS PES8T5A - POWER C B A A TITLE 89HPES8T5A EVALUATION BOARD 89EBPES8T5A SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Tue Apr 15 14:25:57 2008 SHEET 2 1 OF 17 1 7 6 5 4 3 3_3V 12_0V +3.3V_core 12_0V W1 WHT TP24 R324 0% WHT TP11 0 WHT TP9 37 23 22 21 20 2 CW WHT TP6 PGND PGND PGND PGND PGND R325 0% PGND PGND PGND PGND D DISTRIBUTE EVENLY AROUND BOARD 0 AGND 9 10 11 12 8 2 35 1 33 XOV XFB POK R2 1% R142 1K ENABLE ROCP SOFTSTART VS0 VS1 VS2 PLACE R325 NEAR LOAD 10V 6 30 36 34 31 29 13 14 15 16 17 18 38 3 499 AVIN VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT_PAD VSENSE R57 1% 32 EN5330 1 4 5 19 7 24 12_0V W5 C SILKSCREEN -------------------------------------| 12V POWER SELECT | W1 | W5 | W11 | -------------------------------------| EDGE CONNECTOR | 1-2 | 1-2 | 1-2 | -------------------------------------| EXTERNAL INPUT | 2-3 | 2-3 | 2-3 | -------------------------------------- VIN VIN VIN VIN 2K C1 25V 12_0V_US 25 26 27 28 COMP EAIN EAOUT VDRAIN NC NC R55 1% 1.21K 0.015UF C2 330UF PTH08T240WAH 22UF Vo_Adj 0.1UF C37 4 3 0.1UF C36 GND2 GND1 0.1UF C35 7 0.1UF C32 5 0.1UF C34 8 Vout VO_SEN- 0.1UF C29 0.1UF C31 Track SYNC TURBOTRANS Inhibit U1 0.1UF C28 C10 25V C11 16V 10 1 9 11 VDD_CORE 1.0V 6 VO_SEN+ C16 10V D Vin 3 U5 2 22UF 1_0V_core 220UF TP3 YEL TP1 C15 TP2 1 2 3_3V 47UF YEL EXT P/S 12V -> 3.3V 10V YEL 47UF C7 8 C 12_0V DNP W11 J4 POWER CONN R302 DNP NA R303 NA DNP DNP C30 16V 37 23 22 21 20 R327 0% PGND PGND PGND PGND PGND 2 0 PGND PGND PGND PGND 1 9 10 11 12 R15 1% R145 1K AGND 8 2 35 10V 33 XOV XFB POK 499 ENABLE ROCP SOFTSTART VS0 VS1 VS2 PLACE R327 NEAR LOAD R326 0% 0 CW B R16 1% 6 30 36 34 31 29 13 14 15 16 17 18 38 3 2K AVIN CW VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT_PAD VSENSE 47UF C38 32 EN5330 3 R323 0% C27 VIN VIN VIN VIN COMP EAIN EAOUT VDRAIN NC NC PGND PGND PGND PGND 37 23 22 21 20 R322 0% 25 26 27 28 1 4 5 19 7 24 9 10 11 12 PGND PGND PGND PGND PGND U7 10UF AGND 8 2 35 0 2 3 33 XOV XFB POK 499 ENABLE ROCP SOFTSTART VS0 VS1 VS2 PLACE R323 NEAR LOAD R305 1% 6 30 36 34 31 29 13 14 15 16 17 18 38 3 47UF AVIN VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT_PAD VSENSE 1 4 5 19 7 24 0 32 EN5330 0.015UF C33 1 37 23 22 21 20 3 PGND PGND PGND PGND PGND R56 1% R125 1K PGND PGND PGND PGND 499 9 10 11 12 10V AGND 8 2 35 0 R320 0% R9 1% 33 XOV XFB POK 2 CW 2K ENABLE ROCP SOFTSTART VS0 VS1 VS2 PLACE R321 NEAR LOAD 47UF C14 AVIN 6 30 36 34 31 29 13 14 15 16 17 18 38 3 COMP EAIN EAOUT VDRAIN NC NC 32 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT_PAD VSENSE VIN VIN VIN VIN C66 DNP C67 DNP DNP C69 R308 NA DNP DNP R310 DNP NA R311 NA C91 DNP C93 DNP DNP C97 R312 NA A 1 4 5 19 7 24 C8 25V 0.015UF C9 22UF A EN5330 1_0V_pea VDDPEA 1.0V 604 U16 R321 0% VDDPE 1.0V 0.047UF C18 C17 25V TP4 22UF B 25 26 27 28 COMP EAIN EAOUT VDRAIN NC NC 1_0V_pe VIN VIN VIN VIN YEL TP7 VTT 1.5V YEL 25 26 27 28 C89 TP5 U6 +3.3V_pe DNP R309 NA 0 4 C87 DNP +3.3V_pea 1 +5V +3.3V_VTT R14 1K 3 DNP 1_5V_vtt R304 1% GND C80 YEL 10V GND 10UF C113 12_0V_PS 10UF C112 1 2 10UF C111 +12V 10UF C110 DNP R306 DNP NA R307 NA TITLE DNP DNP R299 DNP NA R300 NA C63 DNP C64 DNP DNP C65 89EBPES8T5A POWER REGULATORS 8T5A R301 NA SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang SHEET 2 OF 17 Thu Apr 24 10:22:10 2008 2 1 8 7 6 5 4 3 1 2 3_3VAUX +3.3V_pe 3_3VAUX +3.3V_VIO 10V 3 2 1 S3 S2 S1 D4 D3 D2 D1 487 R129 1% R131 1% 487 S3 S2 S1 D4 D3 D2 D1 C R130 1% R132 1% C47 MMBT3904 Q28 B 10V 47UF 1K 487 487 2 R120 1% 10V 47UF 487 TPS1101D 8 7 6 5 R121 1 5% DNP C79 3 C25 R116 1% R118 1% C 1K E 487 3_3V 3 2 1 R124 5% 1K 10K R119 1% Q18 4 R127 5% 10K D4 D3 D2 D1 D 8 7 6 5 2 R123 1% 487 S3 S2 S1 12_0V 1K 2 E 3_3VAUX 15 8 7 6 5 B DNP C77 MMBT3904 Q27 DNP C78 R115 1% R117 1% 487 E 3_3V 47UF C26 R353 1% 1K 3 D4 D3 D2 D1 10V S3 S2 S1 3 2 1 1K R81 1% 10V R72 1% R75 1% 487 1K 487 2 E 47UF C19 3 8 7 6 5 DNP C54 B C R85 1 5% 1K TPS1101D MMBT3904 Q23 B TPS1101D 10K D4 D3 D2 D1 4 R111 5% 4 R128 5% C 3 2 1 R105 5% R80 1% 3 2 1 S3 S2 S1 Q15 15 TPS1101D 3 R47 1% MMBT3904 Q24 Q16 8 7 6 5 2 R93 1% 10K 3_3VAUX 12_0V R65 5% 1K R45 1% 10K C R58 1 5% 1K DNP C76 R647 1% R649 1% 487 10K 487 DNP C52 R61 1% 2 Q9 4 R67 5% 15 +3.3V_pea 3_3VAUX 15 1 E 3_3V 47UF C24 R122 1% 1K 3 8 7 6 5 B 3_3VAUX 12_0V MMBT3904 Q22 1 E TPS1101D C MMBT3904 Q20 B Q14 4 R112 5% 15 10V 3 D4 D3 D2 D1 TPS1101D C C 47UF C683 3 2 1 4 R648 5% 15 S3 S2 S1 1K Q17 D 1 3_3VAUX 3_3VAUX R646 1% 3_3VAUX +3.3V_VTT 3_3VAUX 3_3VAUX +3.3V_core 3_3VAUX C22 47UF 10V S3 S2 S1 R106 1% R113 1% 487 10V 487 S3 S2 S1 R110 1% R114 1% DNP C59 E 2 R78 1% MMBT3904 Q26 B 487 1K 487 TITLE 10V 487 487 R79 1 5% 89EBPES8T5A POWER MOSFETS FOR 3.3VAUX 1K 47UF C21 E R73 1% R76 1% MMBT3904 Q25 B DNP C57 3 R59 1 5% 2 1K A 3 8 7 6 5 C 1K C TPS1101D 8 7 6 5 10K TPS1101D Q13 4 R86 5% 47UF C23 3 2 1 S3 S2 S1 4 10K R68 5% D4 D3 D2 D1 15 A 3_3V 3 2 1 R84 5% 1K R66 5% 1K R48 1% 15 D4 D3 D2 D1 R83 1% 12_0V R77 1% 10K 3_3V Q11 D4 D3 D2 D1 3_3VAUX 3_3VAUX 12_0V R49 1% E 10K R71 1% R74 1% 487 487 2 E MMBT3904 Q21 B DNP C58 8 7 6 5 DNP C55 B B 8 7 6 5 C 1 MMBT3904 Q19 1 TPS1101D 3 C20 D4 D3 D2 D1 3 C R60 1% 47UF TPS1101D Q12 4 R91 5% 15 2 4 R70 5% 15 10V 3 2 1 Q10 S3 S2 S1 1K B 1K 3 2 1 R82 1% R92 1% 3_3VAUX SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:11 2008 SHEET 3 OF 17 2 1 8 7 6 5 4 3 1 2 3_3V VDDA 13 14 CLK3P CLK3N 7 8 SDATA SCLK CLK2P CLK2N 11 12 22.1 22.1 R26 R27 1% 1% CLK1P CLK1N 19 18 22.1 22.1 R133 R28 1% 1% CLK0P CLK0N 23 22 15 5 ICS_SPREAD IN 12 5 ICS_FS SPREAD 17 SEL 4 10 20 27 22.1 22.1 22.1 22.1 1% 1% YEL TP30 4 4 TP32 YEL YEL REFOUT GND0 GND1 GND2 IREF 5 22 1% 1% 4 4 OUT OUT 9 8 10 7 YEL GNDA 475 IN IN IN IN P2PWRGOODN P3PWRGOODN P4PWRGOODN P5PWRGOODN VDD VDD VDD VDD VDD VDDA 0.1UF C766 0.1UF C365 SRC_IN SRC_IN# DIF_0 DIF_0# 8 9 DIF_1 DIF_1# R148 22.1 1% 12 R149 13 22.1 1% OE1# 15 OE2# DIF_2 DIF_2# 16 22.1 17 22.1 R150 R151 1% 1% DIF_3 DIF_3# 20 22.1 21 22.1 R152 R153 1% 1% DIF_4 DIF_4# 30 29 22.1 22.1 R154 R155 1% 1% DIF_5 DIF_5# 34 33 22.1 22.1 R156 R157 1% 1% DIF_6 DIF_6# 38 37 22.1 22.1 R158 R159 1% 1% DIF_7 DIF_7# 42 41 22.1 22.1 R161 R163 1% 1% LOCK 45 IREF GNDA GND GND 46 475 47 32 25 OE4# OE5# 36 OE6# 44 OE7# 27 26 28 40 22 23 24 1 3 10 18 DIFF_STOP PD HIGH_BW# OE_INV BYPASS#/PLL SCLK SDATA SRC_DIV# GND GND GND 10 TP35 R167 1% OE_INV=1 YEL TP37 R169 1% 0.1UF C765 0.1UF C764 ICS557-06 0.1UF C39 0.1UF C210 FB3 B S2_REFCLKP S2_REFCLKN S3_REFCLKP S3_REFCLKN S4_REFCLKP S4_REFCLKN S5_REFCLKP S5_REFCLKN 5 U_REFCLKP U_REFCLKN CLKREFP CLKREFN ICS_SEL 3 4 6 7 R64 R69 R87 1% DNP DNP 475 R89 4 4 IN IN IN IN IN R88 13 13 CLKDP CLKDN 12 11 22.1 22.1 R182 1% R183 1% CLKCP CLKCN 14 13 22.1 22.1 R94 R95 1% 1% CLKBP CLKBN 18 17 22.1 22.1 R96 R97 1% 1% CLKAP CLKAN 20 19 22.1 22.1 R188 1% R189 1% IN1P IN1N IN2P IN2N 1 SEL1 8 5 10 OE PDN IREF 9 16 GND GND J1 CONNSMA 0.1UF 0.1UF C104 C105 IREFCLKP IREFCLKN PEREFCLK0P PEREFCLK0N PEREFCLK1P PEREFCLK1N SMAOUT_CLKP SMAOUT_CLKN OUT OUT OUT OUT OUT OUT 4 4 1 3 3 221789-3 221789-3 12 12 J19 CONNSMA 5 4 1 J18 CONNSMA 5 2 3 4 221789-3 1 A 2 3 U17 1% 1% 1% 1% 1% 1% 1% 1% DNP DNP B 4 2 R98 R200 R201 R203 R205 R207 R99 R100 221789-3 TITLE 89EBPES8T5A 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 CLOCKS SIZE B FAB P/N DRAWING NO. SCH-00162 6 5 4 3 REV. 18-636-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 7 C 16 16 1 A 8 16 16 4 2 2 15 15 15 J3 CONNSMA 5 5 VDDIN VDDOUT 15 15 OUT OUT OUT OUT OUT OUT OUT OUT 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 10K 3_3V 1% 1% OE0# 35 9 8 11 R146 R147 6 OE3# YEL 22.1 22.1 14 7 9 8 11 7 11 31 48 4 5 43 TP34 R290 5% 26 IREFCLKP IREFCLKN TP33 CLKREFP CLKREFN YEL R29 R30 IN IN TP31 9 8 10 FS2 FS1 FS0 0.1UF C363 0.1UF C763 0.1UF C762 0.1UF C203 0.1UF C42 YEL TP36 10K 10K 10K R7 R8 R20 C 1% 1% 1% IN STOPN 16 6 24 25 0.1UF C41 CLKIN X2 2 19 39 1% 1% 1% 1% 1% 1% 1% 1% 1 2 R313 5% R23 5% R24 R25 R291 R292 R293 R294 R295 R296 R297 R314 22 25MHZ 10 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 4 3 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 VCC OUT R22 1% OE GND 3 9 21 28 D U20 ICS9DB803 R101 R202 R102 R103 R104 R107 R108 R219 R109 R223 R227 R231 R233 R235 R237 R239 VDD0 VDD1 VDD2 0.1UF C40 C109 25V U8 ICS9FG104 Y1 SG-8002CA25.0000-PCB 1 2 0.01UF C43 10K D 22UF 0.1UF C3 R5 5% FB1 0.1UF C361 3_3V 0.1UF C359 3_3V FB2 0.1UF C357 3_3V 3_3V 0.1UF C768 3_3V 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:12 2008 SHEET 4 OF 17 2 1 8 7 6 5 4 3 1 2 3_3V 3_3V POWER INDICATOR PLACE NEAR TOP EDGE LABEL 'POWER' 3_3V R6 5% D 3_3V R10 5% 3_3V TP16 DS1 3_3V 6 5 13 IN 3_3V PERSTN 52R-459-000 HAMILTON JTAG J2 JTAG GND C Y 4 OUT OUT IN OUT OUT DUT_JTAG_TRST_N DUT_JTAG_TDI DUT_JTAG_TDO DUT_JTAG_TMS DUT_JTAG_TCK 1 3 5 7 9 11 13 1 3 5 7 9 11 13 3_3V 2 4 6 8 10 12 14 2 4 6 8 10 12 14 C TSW-107-07-T-D 1K 1K R39 5% R43 5% SN74LVC1G125 12 12 12 12 12 1K 3 1K A 5 1K 2 VCC 10UF OE* 0.1UF C81 IN 1 47UF U2 PERSTN 330 RED DS2 VCC RESET RESETN GND 12 15 16 OUT GRN C12 6V RESINN SENSE CONTROL CT 8 6 5 4 R46 5% 2 7 1 3 2 4 S 6 5 13 D R35 5% U_PERSTN 3.3 R42 5% NO U4 TLC7733D R13 1% 10K NC 10K 10K S1 PB_SW C13 10V R1 5% BOARD RESET 1 3 3_3V W2 3_3V 7 8 12 SSMBDAT OUT SSMBCLK OUT 12 R11 5% R12 5% 1K 1K R53 5% 1K 8 7 12 LABEL PWR D DNP C PWR_SDA PWR_SCL J25 J20 MSMBDAT OUT MSMBCLK OUT J21 LABEL SLAVE D C 1K R51 5% R52 5% 1K LABEL MASTER D C 1K R50 5% 3_3V 12 10 11 OUT OUT 10 11 B B 3_3V 10K 10K 10K 10K 10K 10K 10K 10K 3_3V 10K 10K 10K 10K 10K 10K R134 R135 R136 R137 R138 R139 5% 5% 5% 5% 5% 5% A 1 2 3 4 5 6 S1A S2A S3A S4A S5A S6A S1B S2B S3B S4B S5B S6B 12 11 10 9 8 7 ICS_FS ICS_SPREAD ICS_SEL CCLKDS CCLKUS MSMBSMODE OUT OUT OUT OUT OUT OUT 4 12 4 4 12 12 12 5% 5% 5% 5% 5% 5% 5% 5% 3_3V 10K 10K 10K 10K 10K 10K SILKSCREEN: S4 SM_SW8 SILKSCREEN: S3 SM_SW6 R141 R144 R160 R162 R164 R166 R168 R170 ICS_FS ICS_SPREAD ICS_SEL CCLKDS CCLKUS MSMBSMODE 1 2 3 4 5 6 7 8 S1A S2A S3A S4A S5A S6A S7A S8A S1B S2B S3B S4B S5B S6B S7B S8B 16 15 14 13 12 11 10 9 SSMBADDR1 SSMBADDR2 SSMBADDR3 SSMBADDR5 MSMBADDR1 MSMBADDR2 MSMBADDR3 MSMBADDR4 OUT OUT OUT OUT OUT OUT OUT OUT 12 12 12 12 7 12 7 12 7 12 12 R171 R172 R173 R174 R175 R206 5% 5% 5% 5% 5% 5% SILKSCREEN: S5 SM_SW6 1 2 3 4 5 6 SSMBADDR1 SSMBADDR2 SSMBADDR3 SSMBADDR5 MSMBADDR1 MSMBADDR2 MSMBADDR3 MSMBADDR4 S1A S2A S3A S4A S5A S6A S1B S2B S3B S4B S5B S6B 12 11 10 9 8 7 SWMODE0 SWMODE1 SWMODE2 DIP_SPARE DIP_APWRDIS RSTHALT OUT OUT OUT OUT OUT OUT 12 12 12 6 12 SWMODE0 SWMODE1 SWMODE2 SPARE APWRDIS RSTHALT A TITLE 89EBPES8T5A RESET, JTAG, SMBUS, DIPSW SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:13 2008 SHEET 5 OF 17 2 1 8 7 6 5 4 3 1 2 D D 3_3VAUX 3_3VAUX 0.1UF C53 10K 0.1UF C6 0.1UF C50 3_3VAUX R140 5% 3_3VAUX Y2 SG-8002CA8.0000M-PCBB:ROHS 1 2 OE GND 4 3 VCC OUT R211 5% 22 5 3 8MHZ C C 16 8 U11 P G 2 15 6 5 4 3 P3 P2 P1 P0 11 12 13 14 4 NC 1 9 U10 VCC GND PE* TC 5 5 13 IN IN DIP_APWRDIS PERSTN 2 P G 2 U9 4 NC 1UF 1 B 5 3 U3 4 NC MR* 1 P G C48 25V 10K 5 3 R210 1% B 1 12 74AC161D 0.1UF C51 3_3VAUX CEP CET CP APWRDISN OUT 3_3VAUX 0.1UF C49 3_3VAUX 7 10 2 Q3 Q2 Q1 Q0 A A TITLE 89EBPES8T5A APWRDISN TIMING CIRCUIT SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:13 2008 SHEET 6 OF 17 2 1 8 7 6 5 2 A R41 5% U14 5 VCC 15 3 GND S3_WAKEN IN 1 OE* 2 A 3 GND VCC 5 Y 4 TP38 TP39 P3PWRGOODN 12 11 10 9 8 7 S1B S2B S3B S4B S5B S6B 4 Y YEL P2MRLIN P3MRLIN P4MRLIN P5MRLIN P2PWRGOODN OUT OUT OUT OUT OUT OUT D 11 4 8 9 8 9 8 9 8 9 8 9 10 4 8 9 1% 1% 1% 1% 1% 1% OE* S1A S2A S3A S4A S5A S6A YEL R315 R328 R329 R330 R331 R332 1 1 2 3 4 5 6 0.1UF C86 S2_WAKEN S2 SM_SW6 10K 0.1UF C83 R37 5% 10K U19 IN 1 2 3_3VAUX 3_3VAUX 15 3 3_3VAUX 3_3VAUX D 4 3_3V SN74LVC1G125 3_3VAUX 3_3VAUX 3_3VAUX 2 3 OE* 5 VCC 16 IN A GND S5_WAKEN 0.1UF C85 R234 5% 10K U12 1 U15 1 OE* 2 A 3 GND VCC 5 Y 4 3_3V 4 Y 0 R44 0% U_WAKEN_IN OUT 12 R212 1% R316 1% R317 1% R318 1% IN 0.1UF C82 10K 16 S4_WAKEN 3_3VAUX C R232 5% C 10K 10K 10K 10K 10K 10K SN74LVC1G125 SN74LVC1G125 10K 10K B 10K 10K SN74LVC1G125 B ITT_KSC201J 1 2 1 2 3 4 3 4 P2ATTNIN OUT 8 9 3 4 P3ATTNIN OUT 8 9 3 4 P4ATTNIN OUT 8 9 3 4 P5ATTNIN OUT 8 9 SW1 ITT_KSC201J 3_3V 1 2 PLACE EEPROM ON SOCKET SW2 1 2 R36 5% R38 5% 12 5 12 5 12 5 1 2 3 4 MSMBCLK MSMBDAT 6 5 SCL SDA MSMBADDR3 MSMBADDR2 MSMBADDR1 3 2 1 A2 A1 A0 VCC 8 WP 7 GND 4 SILKSCREEN: WP 0.1UF C84 EEPROM U13 24LC512 2.7K R40 5% SW3 2.7K 2.7K A IN IN IN IN IN 3 4 ITT_KSC201J 3_3V 12 8 5 12 8 5 1 2 ITT_KSC201J 1 2 1 2 3 4 SW4 W3 A 52-298-000 TITLE 89EBPES8T5A EEPROM ATTN_SW WAKE MRL SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:14 2008 SHEET 7 OF 17 2 1 8 7 6 5 4 3 1 2 3_3V R257 5% R259 5% R282 5% R216 5% R218 5% R222 5% 3_3V 3_3V 3_3V 21 2 3 A0 A1 A2 22 23 SCL SDA 12 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 VSS INT_N 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 P2ATTNIN P2PRDETN P2PWRFLTN P2MRLIN P2ATTNIND P2PWRIND P2PWREN P2INTRLCK P4ATTNIN P4PRDETN P4PWRFLTN P4MRLIN P4ATTNIND P4PWRIND P4PWREN P4INTRLCK 0 R285 0% 1 IOEXP0_INTN 7 9 16 9 10 9 7 9 9 9 10 12 8 7 5 12 7 8 5 IN BI U46 MAX7311AUG MSMBCLK MSMBDAT 8 12 3_3V 3_3V 0 B IN BI MSMBCLK MSMBDAT A0 A1 A2 22 23 SCL SDA 12 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 VSS INT_N 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 P2PWRGOODN P3PWRGOODN P4PWRGOODN P5PWRGOODN 1 24 V+ 21 2 3 A0 A1 A2 22 23 SCL SDA 12 VSS P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 INT_N P3ATTNIN P3PRDETN P3PWRFLTN P3MRLIN P3ATTNIND P3PWRIND P3PWREN P3INTRLCK P5ATTNIN P5PRDETN P5PWRFLTN P5MRLIN P5ATTNIND P5PWRIND P5PWREN P5INTRLCK 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 1 IN IN IN IN IOEXP2_INTN DNP R348 NA 0 R352 0% 7 7 10 10 10 11 4 11 4 9 4 9 9 4 9 IOEXP0_INTN GPIO4 C OUT 8 12 OUT 12 R287 0% 0 R288 0% DNP R289 NA IOEXP1_INTN DNP R215 NA 0 R350 0% IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 7 9 15 9 11 9 7 9 9 9 11 7 9 16 9 11 9 7 9 9 9 11 IOEXP0_INTN GPIO3 12 8 7 5 12 7 8 5 OUT 8 12 OUT 12 IN BI R590 1% 2.7K 2.7K MAX7311AUG R256 0% 0.1UF C672 12 8 7 5 12 7 8 5 U45 0 U48 MAX7311AUG MSMBCLK MSMBDAT 0.1UF C675 R254 0% 2.7K 1% 1% 1% 1% 0 R349 R177 1% R195 R208 R220 R253 NA V+ 21 2 3 3_3V 2K 1K 1K 1K 1K 2.7K 2.7K 2.7K DNP 24 R258 5% R281 5% R283 5% IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT OUT 7 9 15 9 10 9 7 9 9 9 10 2K V+ R319 1% R351 1% R284 NA 1K 24 3_3V R217 5% R221 5% R225 5% DNP 1K C R286 0% 0.1UF C673 MSMBCLK MSMBDAT 0.1UF C671 IN BI 0 MAX7311AUG R230 0% 0 12 8 7 5 12 7 8 5 U23 2.7K R229 0% 2.7K 0 2.7K R226 0% 2K 1K 1K 1K 1K 0 D R586 1% R176 R194 R204 R214 2.7K 2.7K 2.7K 1% 1% 1% 1% D 24 V+ 21 2 3 A0 A1 A2 22 23 SCL SDA 12 VSS P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 INT_N 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 P0_LINKUPN P2_LINKUPN P3_LINKUPN P4_LINKUPN P5_LINKUPN P0_ACTIVEN P2_ACTIVEN P3_ACTIVEN P4_ACTIVEN P5_ACTIVEN OUT OUT OUT OUT OUT 9 OUT OUT OUT OUT OUT 9 B 9 9 9 9 9 9 9 9 1 A A TITLE 89EBPES8T5A IO EXPANDERS SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:14 2008 SHEET 8 OF 17 2 1 8 7 6 5 4 3 1 2 3_3V 3_3V MRL LED (RED) POWER INDICATOR LED (GREEN) D 8 7 8 8 8 8 IN IN IN IN P5PWRIND 150 P4PWRIND 150 P3PWRIND 150 P2PWRIND 150 R823 5% R824 5% R825 5% R826 5% DS54 GRN DS55 GRN DS56 GRN DS57 GRN PORT PORT PORT PORT 5 4 3 2 8 7 8 7 8 7 IN IN IN IN P5MRLIN 1K P4MRLIN 1K P3MRLIN 1K P2MRLIN 1K R126 1% R854 1% R855 1% R856 1% DS88 RED DS89 RED DS90 RED DS91 RED DS92 RED DS93 RED DS94 RED DS95 RED PORT PORT PORT PORT 5 4 3 2 PORT PORT PORT PORT 5 4 3 2 5 4 3 2 D POWER FAULT LED (RED) ATTENTION OUTPUT LED (AMBER) 8 11 8 10 8 C 8 8 8 IN IN IN IN P5ATTNIND 1K P4ATTNIND 1K P3ATTNIND 1K P2ATTNIND 1K R838 1% R839 1% R840 1% R841 1% DS61 ORG DS62 ORG DS63 ORG DS64 ORG PORT PORT PORT PORT 5 4 3 2 8 11 8 10 IN IN IN IN PRESENCE DETECT LED (GREEN) 8 16 8 16 8 15 8 15 B IN IN IN IN P5PRDETN P4PRDETN 150 P3PRDETN 150 P2PRDETN 150 DS77 GRN DS78 GRN DS79 GRN 1K P2PWRFLTN 1K 150 P4_LINKUPN 150 P3_LINKUPN 150 8 IN IN IN IN P2_LINKUPN 150 8 IN P0_LINKUPN 150 8 GRN P3PWRFLTN R143 1% R869 1% R870 1% R871 1% C LINK UP LED (GREEN) 8 DS76 1K P5_LINKUPN 8 R62 5% R885 5% R886 5% R887 5% 1K P4PWRFLTN 3_3V 3_3V 150 P5PWRFLTN PORT PORT PORT PORT 5 4 3 2 R165 5% R915 5% R916 5% R917 5% DS96 GRN DS97 GRN DS98 GRN DS99 GRN PORT PORT PORT PORT R919 5% DS100 GRN PORT 0 B LINK ACTIVITY LED (AMBER) ATTENTION INPUT LED (AMBER) P5_ACTIVEN 1K P4_ACTIVEN 1K P3_ACTIVEN 1K 8 IN IN IN IN P2_ACTIVEN 1K 8 IN P0_ACTIVEN 1K 8 8 7 8 7 8 7 8 7 IN IN IN IN P5ATTNIN 1K P4ATTNIN 1K P3ATTNIN 1K P2ATTNIN 1K R63 1% R900 1% R901 1% R902 1% DS80 PORT PORT PORT PORT ORG DS81 ORG DS82 ORG DS83 ORG 8 5 4 3 2 8 R298 1% R931 1% R932 1% R933 1% DS101 ORG DS102 ORG DS103 ORG DS104 ORG PORT PORT PORT PORT R935 1% DS105 ORG PORT 0 5 4 3 2 3_3V A A POWER GOOD LED (GREEN) 8 4 11 10 8 4 10 8 4 11 7 8 4 10 7 IN IN IN IN P5PWRGOODN 150 P4PWRGOODN 150 P3PWRGOODN 150 P2PWRGOODN 150 R90 5% R947 5% R948 5% R949 5% DS84 GRN DS85 GRN DS86 GRN DS87 GRN PORT PORT PORT PORT 5 4 3 2 TITLE 89EBPES8T5A IO EXPANDER LEDS SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:15 2008 SHEET 9 OF 17 2 1 8 7 6 5 4 3 1 2 3_3VAUX 12_0V 3_3V POWER CONTROLLER PORT 2&4 C116 25V C117 10V 10UF RFILTERAB CFILTERA CFILTERB VAUXA 10K 10K 10K 10K 10K R248 2% 0.012 0.1UF C72 R247 2% 0.02 0.1UF C71 R245 2% 0.012 R243 2% 37 S2_3VAUX 15 12VINA 5 12VSENSEA 8 12VGATEA 3 12VOUTA 10 3VINA 12 3VSENSEA 13 3VGATEA 14 3VOUTA 16 12VINB 32 12VSENSEB 29 12VGATEB 34 12VOUTB 27 3VINB 25 3VSENSEB 24 Q1 15 4 R241 5% C S2_12V OUT 15 S2_3V OUT 15 44 43 ONA ONB 3_3V S4_12V OUT 16 8 7 6 5 D4 D3 D2 D1 SI4420DY Q3 4 R244 5% SI4435DY 8 7 6 5 15 SCL SDA 4 38 GPI_A0 GPI_B0 3VGATEB 23 3VOUTB 21 VAUXB 22 PWRGDA_N PWRGDB_N FAULTA_N FAULTB_N 6 31 1 36 GND1 GND2 GND3 17 33 46 B 8 7 6 5 47 48 Q4 15 R246 5% D4 D3 D2 D1 A2 A1 A0 4 SI4420DY S4_3V S4_3VAUX 3 2 1 PWR_SCL PWR_SDA 39 40 41 S3 S2 S1 B R333 R334 R335 R786 R787 R788 4 3 2 1 AUXENA AUXENB R242 5% S3 S2 S1 R782 R783 0 0 45 42 Q2 15 S3 S2 S1 11 11 4 8 9 10 4 8 9 DNP DNP DNP 0 0 0 IN IN FORCE_ONA_N FORCE_ONB_N D4 D3 D2 D1 P2PWREN P4PWREN 9 28 11 YEL TP41 10K R224 5% R228 5% 0.01UF = 5MS 0.1 UF = 50MS 7 18 19 30 0.01UF C62 10K 0.01UF C61 TP40 NC1 NC2 NC3 NC4 15 SI4435DY 3 2 1 OUT OUT OUT OUT OUT 3 2 1 R240 20 1% 110K INT_N VSTBYA VSTBYB 8 7 6 5 IN IN YEL TP42 S3 S2 S1 10K 10K 10K 10K 10K 10K 12 S2_FORCE_ON 11 S3_FORCE_ON 10 S4_FORCE_ON 9 S5_FORCE_ON 8 P5PWRGOODN 7 P4PWRGOODN 11 5 11 5 YEL MIC2592B_2YTQ S6 SM_SW6 8 8 0.1UF C70 5% 5% 5% 5% 5% 5% R3 R4 R236 R238 R336 R337 U21 C S1B S2B S3B S4B S5B S6B 0.02 0.1UF C68 0.1UF C60 3_3VAUX 3_3V 2 35 S1A S2A S3A S4A S5A S6A R249 5% R250 5% R251 5% R252 5% R255 5% D 47UF 11 26 1 2 3 4 5 6 3_3V D4 D3 D2 D1 D P2PWRGOODN P4PWRGOODN P2PWRFLTN P4PWRFLTN OUT OUT OUT OUT OUT OUT 16 16 7 4 8 9 10 4 8 9 8 9 8 9 53R-1120-000 A A TITLE 89EBPES8T5A HOT SWAP CONTROL PORT 2/3 SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:16 2008 SHEET 10 OF 17 2 1 8 7 6 5 4 3 1 2 3_3VAUX 12_0V POWER CONTROLLER PORT 3&5 3_3V 3_3V D C4 25V C5 10V D 10K 10K 10K 10K R274 2% 0.1UF C103 0.012 R273 2% 0.1UF C101 0.02 R271 2% 0.012 0.1UF C99 R269 2% 0.1UF C95 R262 R263 R264 R265 R341 R342 U22 YEL TP45 MIC2592B_2YTQ S3_3VAUX OUT 15 5 12VSENSEA 8 12VGATEA 3 12VOUTA 10 3VINA 12 3VSENSEA 13 3VGATEA 14 3VOUTA 16 12VINB 32 12VSENSEB 29 12VGATEB 34 12VOUTB 27 3VINB 25 3VSENSEB 24 3VGATEB 23 3VOUTB 21 VAUXB 22 PWRGDA_N PWRGDB_N FAULTA_N FAULTB_N 6 31 1 36 GND1 GND2 GND3 17 33 46 Q5 15 R267 5% 4 SI4435DY S3_12V OUT 15 44 43 ONA ONB 3_3V S3_3V OUT 15 S5_12V OUT 16 8 7 6 5 D4 D3 D2 D1 Q7 4 R270 5% 15 SI4435DY PWR_SCL PWR_SDA A2 A1 A0 47 48 SCL SDA 4 38 GPI_A0 GPI_B0 B 8 7 6 5 39 40 41 15 R272 5% Q8 4 SI4420DY S5_3V S5_3VAUX 3 2 1 IN IN SI4420DY D4 D3 D2 D1 B R338 R339 R340 R33 R34 R54 4 S3 S2 S1 DNP DNP 0 0 0 DNP 10 5 10 5 YEL AUXENA AUXENB Q6 3 2 1 R31 R32 45 42 R268 5% 15 S3 S2 S1 0 0 FORCE_ONA_N FORCE_ONB_N D4 D3 D2 D1 P3PWREN P5PWREN IN IN 9 28 S3 S2 S1 S3_FORCE_ON S5_FORCE_ON 8 7 6 5 8 8 IN IN 3 2 1 10 10 YEL 10K R260 5% R261 5% 0.01UF = 5MS 0.1 UF = 50MS 0.01UF C75 10K 0.01UF C74 TP44 TP43 7 18 19 30 NC1 NC2 NC3 NC4 15 C 8 7 6 5 CFILTERA CFILTERB VAUXA 12VINA 3 2 1 2 35 C RFILTERAB 37 S3 S2 S1 R266 20 1% 110K INT_N VSTBYA VSTBYB D4 D3 D2 D1 11 26 10K 10K 10K 10K 10K 10K 0.02 3_3VAUX 5% 5% 5% 5% 5% 5% 3_3V 0.1UF C108 0.1UF C73 47UF 10K R275 5% R276 5% R277 5% R278 5% R279 5% 10UF P3PWRGOODN P5PWRGOODN P3PWRFLTN P5PWRFLTN OUT OUT OUT OUT OUT OUT 16 16 7 4 8 9 10 4 8 9 8 9 8 9 53R-1120-000 A A TITLE 89EBPES8T5A HOT SWAP CONTROL PORT 3/5 SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:16 2008 SHEET 11 OF 17 2 1 8 7 6 5 4 3 1 2 D YEL U18 89HPES8T5AXXBCG F3 E2 F2 E1 D1 D2 L1 K1 J1 J3 J2 DUT_JTAG_TCK DUT_JTAG_TDI DUT_JTAG_TDO DUT_JTAG_TMS DUT_JTAG_TRST_N YEL TP28 TP29 TP46 TP47 D L13 L14 K13 K14 J13 H12 J14 H13 H14 G13 F12 P5RSTN P3RSTN GPIO8 GPEN TSTCLK1 TSTCLK0 GPIO4 GPIO3 IOEXP0_INTN P4RSTN P2RSTN R346 5% C M13 SSMBADDR5 SSMBADDR3 SSMBADDR2 SSMBADDR1 SSMBCLK SSMBDAT GPIO_10 GPIO_09 GPIO_08 MSMBSMODE 2 of 7 GPIO_07 SSMBADDR_5 GPIO_06 SSMBADDR_3 GPIO_05 SSMBADDR_2 GPIO_04 SSMBADDR_1 GPIO_03 SSMBCLK GPIO_02 GPIO_01 SSMBDAT GPIO_00 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST* YEL 10K 5 5 5 5 5 MSMBSMODE MSMBADDR_4 MSMBADDR_3 MSMBADDR_2 MSMBADDR_1 MSMBCLK MSMBDAT 10K 5 G1 H3 H2 H1 G2 F1 10K 5 5 5 5 5 MSMBADDR4 MSMBADDR3 MSMBADDR2 MSMBADDR1 MSMBCLK MSMBDAT 10K 5 IN IN IN IN IN IN IN IN IN IN IN BI BI IN IN IN IN IN YEL R343 5% R344 5% R213 5% R345 5% 5 5 5 5 5 5 TP17 TP27 YEL 10K 7 7 7 8 7 7 8 YEL OUT OUT BI OUT OUT OUT IN IN IN OUT OUT 16 15 8 8 8 16 15 C R280 5% 3_3VAUX 6 B 4 4 4 5 5 5 16 15 5 5 5 5 5 7 IN IN IN IN IN IN IN IN IN IN IN IN APWRDISN PEREFCLK0P PEREFCLK0N C2 APWRDISN P1 N1 REFCLKP REFCLKN ICS_FS M12 REFCLKM CCLKUS CCLKDS C3 C10 CCLKUS CCLKDS U_PERSTN F13 PERSTN RSTHALT G14 RSTHALT SWMODE2 SWMODE1 SWMODE0 D13 D14 C14 SWMODE_2 SWMODE_1 SWMODE_0 WAKEN W15 2.7K U18 89HPES8T5AXXBCG C1 U_WAKEN DUT_WAKEN 13 OUT B 1 0f 7 U_WAKEN_IN A A TITLE 89EBPES8T5A PES8T5A CLOCK, SMBUS, GPIO SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:17 2008 SHEET 12 OF 17 2 1 8 7 6 5 4 3 1 2 12_0V_US P1 PCIE_X4_EDGE 12 13 13 U_WAKEN IN U_PERN0 U_PERP0 IN IN DNP C 13 13 13 13 13 13 IN IN U_PERP1 U_PERN1 IN IN U_PERP2 U_PERN2 IN IN U_PERP3 U_PERN3 R347 NA B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND PRSTN1# +12V +12V GND JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS +3.3V +3.3V PERST# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 GND REFCLK+ REFCLKGND PERP0 PERN0 GND RSVD GND PERP1 PERN1 GND GND PERP2 PERN2 GND GND PERP3 PERN3 GND RSVD A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 C56 25V +12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG_TRSTN 3.3VAUX WAKE# 6.8UF B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 D C46 25V 6.8UF 10UF 3_3VAUX 10UF D C45 25V C44 25V 3_3V_US PORT 0 UPSTREAM EDGE CONNECTOR PROVIDES ALL POWER FOR BOARD PERSTN OUT 5 6 U_REFCLKP U_REFCLKN OUT OUT OUT OUT 4 4 U_PETP0 U_PETN0 13 13 C U_PETP1 U_PETN1 OUT OUT 13 13 U_PETP2 U_PETN2 OUT OUT 13 13 U_PETP3 U_PETN3 OUT OUT 13 13 B B U18 89HPES8T5AXXBCG 13 13 13 13 13 13 13 13 IN IN IN IN IN IN IN IN A13 B13 B8 A8 B7 A7 A2 B2 U_PERP0 U_PERN0 U_PERP1 U_PERN1 U_PERP2 U_PERN2 U_PERP3 U_PERN3 PE0RP00 PE0TP00 PE0RN00 PE0TN00 PE0RP01 PE0TP01 PE0RN01 PE0TN01 3 of 7 PE0TP02 PE0RP02 PE0TN02 PE0RN02 PE0TP03 PE0RP03 PE0TN03 PE0RN03 B11 A11 A10 B10 A5 B5 B4 A4 0.1UF C152 0.1UF 0.1UF C153 0.1UF 0.1UF C154 0.1UF 0.1UF C155 C160 0.1UF C161 C162 C163 U_PETP0 U_PETN0 U_PETP1 U_PETN1 U_PETP2 U_PETN2 U_PETP3 U_PETN3 OUT OUT OUT OUT OUT OUT OUT OUT 13 13 13 13 13 13 13 13 A A TITLE 89EBPES8T5A PES8T5A PORT 0 EDGE CONN SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang SHEET 13 OF 17 Thu Apr 24 10:22:17 2008 2 1 8 7 6 5 4 3 1 2 D D U18 89HPES8T5AXXBCG 15 15 C 15 15 IN IN S2_PERP0 S2_PERN0 IN IN S3_PERP0 S3_PERN0 P3 N3 P8 N8 PE2RP00 PE2RN00 PE3RP00 PE3RN00 PE2TP00 PE2TN00 PE3TP00 PE3TN00 N5 P5 0.1UF 0.1UF C88 C96 S2_PETP0 S2_PETN0 OUT OUT 15 15 C P6 N6 0.1UF 0.1UF C90 C98 S3_PETP0 S3_PETN0 OUT OUT 15 15 4 of 7 16 16 IN IN S4_PERP0 S4_PERN0 N9 P9 PE4RP00 PE4RN00 PE4TP00 PE4TN00 P11 N11 0.1UF 0.1UF C92 C100 S4_PETP0 S4_PETN0 OUT OUT 16 16 16 16 IN IN S5_PERP0 S5_PERN0 P14 N14 PE5RP00 PE5RN00 PE5TP00 PE5TN00 N12 P12 0.1UF 0.1UF C94 C102 S5_PETP0 S5_PETN0 OUT OUT 16 16 B B A A TITLE 89EBPES8T5A PES8T5A DOWNSTREAM PORTS SIZE B FAB P/N DRAWING NO. SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:18 2008 SHEET 14 OF 17 2 1 8 7 6 5 4 3 1 2 3_3VAUX 1-2 : HOT-PLUG 2-3 : PC PWR 12_0V W30 J14 10 IN S2_3VAUX 10 IN S2_12V PCIE_CONN_x4_OPEN_SLOT 3_3V W31 D 10 IN W32 S2_3V 7 OUT S3_WAKEN C107 25V C118 25V C119 25V 10UF 10UF 10UF IN IN S3_PETP0 S3_PETN0 3_3V 5.1K C106 25V 10UF 14 14 DNP R209 NA 3_3V R190 5% C 9 8 J9 P3PRDETN OUT PCIE_CONN_x4_OPEN_SLOT OUT P2PRDETN RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND GND REFCLK+ REFCLKGND PERP0 PERN0 GND RSVD GND PERP1 PERN1 GND GND PERP2 PERN2 GND GND PERP3 PERN3 GND RSVD A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 0 R193 0% D S3_RSTN IN S3_REFCLKP S3_REFCLKN IN IN OUT OUT S3_PERP0 S3_PERN0 15 4 4 14 14 C LABEL: PORT 3 PCIE X4 (1) S2_RSTN S2_REFCLKP S2_REFCLKN S2_PERP0 S2_PERN0 1-2 : HOT-PLUG 2-3 : PC PWR 15 IN W6 3_3VAUX 4 4 IN IN OUT OUT W33 14 14 11 11 IN IN 12_0V 15 S3_3VAUX OUT U_PERSTN IN 5 12 15 16 P3RSTN IN 12 U_PERSTN IN 5 12 15 16 P2RSTN IN 12 B S3_RSTN W34 S3_12V W7 W35 3_3V 11 IN S3_3V 15 108051-301AC LABEL: PORT 2 PCIE X4 (1) A B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 OUT S2_RSTN C123 25V 9 8 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 10UF R196 5% 5.1K 3_3V GND REFCLK+ REFCLKGND PERP0 PERN0 GND RSVD GND PERP1 PERN1 GND GND PERP2 PERN2 GND GND PERP3 PERN3 GND RSVD PRSTN1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# 108051-301AC C122 25V S2_PETP0 S2_PETN0 IN IN RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND +12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG1 3.3VAUX WAKE# R199 0% 10UF 14 14 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 0 C121 25V B A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 10UF S2_WAKEN PRSTN1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# C120 25V OUT +12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG1 3.3VAUX WAKE# 10UF 7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 A TITLE 89EBPES8T5A PORT 2 AND PORT 3 SIZE B DRAWING NO. FAB P/N SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:18 2008 SHEET 15 OF 17 2 1 8 7 6 5 4 3 1 2 3_3VAUX 1-2 : HOT-PLUG 2-3 : PC PWR 10 IN W36 S4_3VAUX 12_0V 3_3V W37 J17 PCIE_CONN_x4_OPEN_SLOT D 10 10 IN S4_12V IN S4_3V W38 S5_WAKEN C127 25V OUT 14 14 S5_PETP0 S5_PETN0 IN IN 10UF C126 25V 10UF C125 25V 10UF 10UF C124 25V 7 3_3V 5.1K C R178 5% J16 PCIE_CONN_x4_OPEN_SLOT A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND GND REFCLK+ REFCLKGND PERP0 PERN0 GND RSVD GND PERP1 PERN1 GND GND PERP2 PERN2 GND GND PERP3 PERN3 GND RSVD A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 0 R181 0% D S5_RSTN S5_REFCLKP S5_REFCLKN S5_PERP0 S5_PERN0 IN IN IN OUT OUT 16 4 4 14 14 C 108051-301AC S4_RSTN S4_REFCLKP S4_REFCLKN S4_PERP0 S4_PERN0 1-2 : HOT-PLUG 2-3 : PC PWR IN IN IN OUT OUT LABEL: PORT 5 PCIE X4 (1) 16 3_3VAUX 4 4 W8 W39 B 12_0V 14 14 11 IN 11 IN W40 16 OUT IN 5 12 15 16 P5RSTN IN 12 U_PERSTN IN 5 12 15 16 P4RSTN IN 12 S5_RSTN S5_12V W50 3_3V 11 IN U_PERSTN S5_3VAUX W9 S5_3V 108051-301AC A PRSTN1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# LABEL: PORT 4 PCIE X4 (1) C131 25V A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 P5PRDETN OUT 10UF OUT GND REFCLK+ REFCLKGND PERP0 PERN0 GND RSVD GND PERP1 PERN1 GND GND PERP2 PERN2 GND GND PERP3 PERN3 GND RSVD 9 8 10UF 9 8 P4PRDETN RSVD GND PETP0 PETN0 GND PRSTN2# GND PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSTN2# GND R187 0% +12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG1 3.3VAUX WAKE# 16 S4_RSTN OUT 10UF R184 5% 5.1K 3_3V B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 0 C130 25V S4_PETP0 S4_PETN0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 C129 25V IN IN PRSTN1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# 10UF 14 14 B OUT S4_WAKEN +12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG1 3.3VAUX WAKE# C128 25V 7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 A TITLE 89EBPES8T5A PORT 4 AND PORT 5 SIZE B DRAWING NO. FAB P/N SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:19 2008 SHEET 16 OF 17 2 1 8 7 1_5V_vtt 6 5 1_0V_pe 4 3 1 2 1_0V_core +3.3V_VIO W4 W23 W10 W25 JUMPERS MUST BE POPULATED FOR NORMAL OPERATION D D DUT_VTT 1.0UF DUT_VDDPE C212 1.0UF C170 DUT_VDDCORE DUT_3_3V 1.0UF D5 D6 D9 D11 E4 E10 E13 F6 F7 F9 F10 G5 G8 H4 H6 H7 H10 H11 J4 J6 J8 J9 K5 K11 L5 L6 L9 L10 M2 M3 C214 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C215 C216 C217 C218 C219 C220 1.0UF C246 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C247 C248 C249 C250 C251 C252 C253 C254 C255 U18 89HPES8T5AXXBCG C7 C8 K3 M7 M8 VDDAPE1 VDDAPE2 VDDAPE3 VDDAPE4 VDDAPE5 VDDPE1 VDDPE2 VDDPE3 VDDPE4 D7 D8 L7 L8 C 5 of 7 0.1UF 0.1UF 0.1UF 0.1UF 47UF 47UF 0.1UF 0.1UF 0.1UF 0.1UF C191 C192 C193 C194 47UF C168 47UF 10V 10V 47UF C243 10V C169 47UF 10V C171 C172 C173 C174 C189 C190 10V 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C244 10V C221 C222 C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 U18 U18 89HPES8T5AXXBCG VDDCORE1 VDDCORE2 VDDCORE3 VDDCORE4 VDDCORE5 VDDCORE6 VDDCORE7 VDDCORE8 VDDCORE9 VDDCORE10 VDDCORE11 VDDCORE12 VDDCORE13 VDDCORE14 VDDCORE15 VDDCORE16 VDDCORE17 VDDCORE18 VDDCORE19 VDDCORE20 VDDCORE21 VDDCORE22 VDDCORE23 VDDCORE24 VDDCORE25 VDDCORE26 VDDCORE27 VDDCORE28 VDDCORE29 VDDCORE30 89HPES8T5AXXBCG VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VTT1 VTT2 VTT3 VTT4 C12 D4 D10 E3 E12 F4 F11 G3 G12 J11 J12 K2 L4 M5 M10 M11 A1 A3 A6 A9 A12 A14 B1 B3 B6 B9 B12 B14 C4 C5 C11 C13 D3 D12 E5 E6 E7 E8 E9 E11 E14 F5 F8 F14 G4 G6 G7 G9 C6 C9 M6 M9 6 of 7 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 7 of 7 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 G10 G11 H5 H8 H9 J5 J7 J10 K4 K6 K7 K8 K9 K10 K12 L2 L3 L11 L12 M1 M4 M14 N2 N4 N7 N10 N13 P2 P4 P7 P10 P13 C B B 1_0V_pea FB6 W24 DUT_VDDPEA C278 10V 47UF C233 C234 C235 C236 10V A 0.1UF 0.1UF 0.1UF 0.1UF 1.0UF C213 A 0.1UF C188 1.0UF C187 FB5 47UF C277 FB4 TITLE 89EBPES8T5A PES8T5A POWER SIZE B DRAWING NO. FAB P/N SCH-00162 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 8 7 6 5 4 3 REV. 18-636-002 1.0 CHECKED BY T. Tran D. Huang Thu Apr 24 10:22:19 2008 SHEET 17 OF 17 2 1 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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